Normally-off trench JFET technology in 4H silicon carbide

A double gate normally-off silicon carbide (SiC) trench junction field effect transistors (JFET) design is considered. Innovative migration enhanced embedded epitaxial (ME³) growth process was developed to replace the implantation process and realize high device performance. Strong anisotropic behavior in electrical characteristics of the pn junction fabricated on (1 1 −2 0) and (1 −1 0 0) trench a-planes was observed, although quality of the pn diodes was found to be independent of trench plane orientations. Fabricated normally-off trench 4H-SiC JFET demonstrates the potential for lower specific on-resistance (R_onS) in the range of 5-10 mΩ cm² (1200 V class). A relative high T^−2.6 dependence of R_onS is observed. A breakdown voltage of 400 V in the avalanche mode was confirmed at zero gate bias conditions for cell design without edge termination. It was demonstrated that the normally-off JFETs are suitable for high temperature applications. Average temperature coefficient of threshold voltage (V_th) was calculated as −1.8 mV/°C, which is close to the MOS based Si power devices.     

Low gate interface traps AlGaN/GaN HEMTs using a lattice matched ZrZnO transparent gate design

AlGaN/GaN metal–insulator–semiconductor high electron mobility transistors (MIS-HEMTs) using a radio-frequency magnetron sputtered ZrZnO transparent oxide layer as a gate insulator are investigated and compared with traditional GaN HEMTs. A negligible hysteresis voltage shift in the C–V curves is seen, from 0.09 V to 0.36 V, as the thickness of ZrZnO films increases. The composition of ZrZnO at different annealing temperatures is observed using X-ray photoelectron spectroscopy (XPS). The ZrZnO thin film achieves good thermal stability after 600 °C, 700 °C and 800 °C post-deposition annealing (PDA) because of its high binding energy. Based on the interface trap density analysis, D_it has a value of 2.663 × 10¹² cm⁻²/eV for 10-nm-thick ZrZnO-gate HEMTs and demonstrates better interlayer characteristics, which results in a better slopes for the I_ds degradation (5.75 × 10⁻¹ mA/mm K⁻¹) for operation from 77 K to 300 K. The 10-nm-thick ZrZnO-gate device also exhibits a flat and a stable 1/f noise, as V_GS–V_th, and at various operating temperatures. Therefore, ZrZnO has good potential for use as the transparent film for a gate insulator that improves the GaN-based FET threshold voltage and improves the number of surface defects at various operating temperatures.     

Ferroelectric and leakage current characteristics of (Pb0.72La0.28)Ti0.93O3 thin films prepared by a sol-gel process

(Pb_1 − xLa_x)Ti_1 − x/4O₃(x = 28 mol%, denoted as PLT) thin films were grown on Pt/Ti/SiO₂/Si substrates by using a sol-gel process. The Pt/PLT/Pt film capacitor showed well-saturated hysteresis loops at an applied electric field of 500 kV/cm with spontaneous polarization (P_s), remanent polarization (P_r) and coercive electric field (E_c) values of 9.23 μC/cm², 0.53 μC/cm² and 19.7 kV/cm, respectively. At 100 kHz, the dielectric constant and dissipation factor of the film were 748 and 0.026, respectively. The leakage current density is lower than 1.0 × 10⁻⁷ A/cm²over the electric field range of 0 to 200 kV/cm. And the Pt/PLT interface exist a Schottky emission characteristics.     

Air-stability and bending properties of flexible organic field-effect transistors based on poly[N-9′-heptadecanyl-2,7-carbazole-alt-5,5-(4′,7′-di-2-thienyl-2′,1′,3′-benzothiadiazole)]

We have fabricated flexible field-effect transistors (FETs) using poly[N-9′-heptadecanyl-2,7-carbazole-alt-5,5-(4′,7′-di-2-thienyl-2′,1′,3′-benzothiadiazole)], PCDTBT, as an active channel, poly(methyl methacrylate) (PMMA) as gate dielectric and biaxially oriented polyethyleneterephthalate (BOPET) as supporting substrate. The output and transfer characteristics of the devices were measured as a function of channel length. It has been observed that various OFET parameters viz. on–off ratio (∼10⁵), mobility (μ ∼ 10⁻⁴ cm² V⁻¹ s⁻¹), threshold voltage (V_th ∼ −14 V), switch-on voltage (V_so ∼ −6 V), subthreshold slope (S ∼ 7 V/decade) and trap density (N_it ∼ 10¹⁴ cm⁻² V⁻¹) are almost independent of the channel length, which suggested a very high uniformity of the PCDTBT active layer. These devices were highly stable under atmospheric conditions (temperature: 20–35 °C and relative humidity: 70–85%), as no change in mobility was observed on a continuous exposure for 70 days. The studies on the effect of strain on mobility revealed that devices are stable up to a compressive or tensile strain of 1.2%. These results indicate that PCDTBT is a very promising active layer for the air stable and flexible FETs.     

The influence of visible light on the gate bias instability of In-Ga-Zn-O thin film transistors

We investigated the effect of photon irradiation with various energies on the gate bias instability of indium-gallium-zinc oxide transistors. The illumination of red and green light on the transistor caused positive threshold voltage (V_th) shifts of 0.23 V and 0.18 V, respectively, while it did not affect the V_th value in blue light after a positive bias stress. However, the stability of transistors was deteriorated with increasing photon energy after a negative bias stress: negative V_th shifts for red (−0.23 V) and blue light (−3.7 V). This difference can be explained by the compensation effect of the electron carrier trapping and the creation of meta-stable donors via photon excitation.     

Sidewall defects of AlGaN/GaN HEMTs evaluated by low frequency noise analysis

The traditional dry etching isolation process in AlGaN/GaN HEMTs causes the gate metal to contact the mesa sidewalls region, forming a parasitic gate leakage path. In this paper, we suppress the gate leakage current from the mesa-sidewall to increase the gate-to-drain breakdown voltage and thereby reduce the interface trap density by using the ion implantation (I/I) isolation technology. According to the capacitance–voltage (C–V) measured curve, the hysteresis voltage was 9.3 mV and the interface state density was 5.26 × 10¹² cm⁻² for the I/I isolation sample. The 1/f noise phenomena and Schottky characteristics are particularly studied to indicate device linearity, which is sensitive to the semiconductor surface. The fluctuation that causes trapping/detrapping of free carriers near the gate interface can be reduced because side-wall plasma-induced damages were eliminated. The reduced DC and flicker noise variation of I/I isolation HEMTs is beneficial for high power transistor applications.     

Thermally annealed Ni/n-GaAs(Si)/In Schottky barrier diodes

We have identically prepared as many as eight Ni/n-GaAs/In Schottky barrier diodes (SBDs) using an n-type GaAs substrate with a doping density of about 7.3 × 10¹⁵ cm⁻³. The thermal stability of the Ni/n-GaAs/In Schottky diodes has been investigated by means of current-voltage (I-V) techniques after annealed for 1 min in N₂ atmosphere from 200 to 700 °C. For Ni/n-GaAs/In SBDs, the Schottky barrier height Φ_b and ideality factor n values range from 0.853 ± 0.012 eV and 1.061 ± 0.007 (for as-deposited sample) to 0.785 ± 0.002 eV and 1.209 ± 0.005 (for 600 °C annealing). The ideality factor values remained about unchanged up to 400 °C annealing. The I-V characteristics of the devices deteriorated at 700 °C annealing.     

Improvement of the field emission characteristics of an oxidized porous polysilicon using annealed Pt/Ti surface emitter electrode

The field emission characteristics of an oxidized porous polysilicon were investigated with different annealing temperatures. Pt/Ti, Ir, and Au/NiCr were used as surface emitter electrodes, and Pt/Ti emitter showed highly efficient and stable electron emission characteristic compared with the conventional Au/NiCr electrode. Thin Ti layer played an important role in promotion of adhesion of Pt to SiO₂ surface and uniform distribution of electric field on the OPPS surface. Additionally, the Ti layer efficiently blocked the diffusion of emitter metal, which resulted in more reliable emission characteristics. Pt/Ti emitter annealed at 350 °C/1 h showed the highest efficiency of 3.36% at V_ps=16 V, which resulted from the improvement of interfacial contact characteristics of thin emitter metal to an oxidized porous polysilicon. Annealing above 400 °C showed that Pt/Ti and Ir emitter electrode were thermally more stable than Au/NiCr emitter.     

Doping compensation for increased robustness of fast recovery silicon diodes

High-power diodes with the radiation enhanced diffusion (RED) of Pd are shown to have much higher ruggedness during the reverse recovery compared to that of the Pt. Anode doping profiles measured by spreading resistance technique after a 10 MeV He implantation with subsequent annealing between 500 and 800 °C reveal different compensation effects between the Pd and Pt. The in-diffusing Pd converts the n-type background doping concentration of N_D = 3 × 10¹³ cm⁻³ in the position of radiation defects to that of a p-type with about one order higher concentration. The created low-doped p-layer significantly increases ruggedness of diodes during reverse recovery. In the diodes with the Pt layer, only a modest compensation is observed, a conversion to a p-type layer is missing and robustness is much lower. The DLTS spectra for the Pt and Pd devices show a similar electronic structure and introduction rates of defects at 700 °C, while they differ significantly at 600 and 650 °C both for the majority and minority carriers. It is preliminary suggested that the strong compensation effect after the RED of Pd is caused by a high introduction rate of an acceptor deep level at the lower half of the silicon bandgap.     

Organic nonvolatile memory transistors based on fullerene and an electron-trapping polymer

We report for the first time organic n-type nonvolatile memory transistors based on a fullerene (C₆₀) semiconductor and an electron-trapping polymer, poly(perfluoroalkenyl vinyl ether) (CYTOP). The transistors with a Si++/SiO₂/CYTOP/C₆₀/Al structure show good n-type transistor performance with a threshold voltage (V_th) of 2.8 V and an electron mobility of 0.4 cm² V⁻¹ s⁻¹. Applying gate voltages of 50 or −45 V for about 0.1 s to the devices induces the reversible shifts in their transfer characteristics, which results in a large memory window (ΔV_th) of 10 V. A memory on/off ratio of 10⁵ at a small reading voltage below 5 V and a retention time greater than 10⁵ s are achieved. The memory effect in the transistor is ascribed to electrons trapped at the CYTOP/SiO₂ interface. Because of the use of high-electron-mobility C₆₀, the switching voltages of our memory transistors become significantly lower than those of conventional memory transistors based on pentacene.     

Molybdenum and low-temperature annealing of a silicon power P-i-N diode

High-power P⁺P-N-N⁺ diodes (V_RRM = 2.5 kV, I_FAV = 150 A) with sputtered Mo layer at anode were annealed in the range 550-800 °C with and without the presence of radiation defects from helium implantation (10 MeV, 1 × 10¹² cm⁻²). The devices were characterized using DLTS, spreading resistance, OCVD lifetime, leakage current, forward voltage drop and reverse recovery measurements. The diffusion of Mo from the 50 nm thick surface layer was not registered even after 4 h between 550 and 800 °C in a rough vacuum. The DLTS confirms the existence of hole deep levels H1 and H2 in the He implanted devices with the Mo anode layer. Similar levels have been already found in the devices with Pt and Pd anode layers, but with different annealing behavior between 600 and 700 °C. Contrary to that of the Pt and Pd, no radiation enhanced diffusion was found from the 50 nm thick Mo surface layer in a rough vacuum.     

Hydrated bovine serum albumin as the gate dielectric material for organic field-effect transistors

Bovine serum albumin (BSA) is a natural protein with good hydration ability which contains acidic and basic amino acid residues of ca. 34% in total. In vacuum, pentacene organic field-effect transistors (OFETs) with BSA as the gate dielectric exhibits a field-effect mobility value (μ_FE,sat) of 0.3 cm² V⁻¹ s⁻¹ in the saturation regime and a threshold voltage (V_TH) of ca. −16 V. BSA is easy to be hydrated in air ambient. Electrical properties of BSA in vacuum and hydrated BSA in air ambient are characterized. Similar to polyelectrolyte, hydrated BSA may act the gate dielectric with the formation of electric double-layer capacitors (EDLCs) to improve the device performance. In a relative humidity of 47%, the μ_FE,sat value increases to 4.7 cm² V⁻¹ s⁻¹ and the V_TH reduces to −0.7 V. Generation of mobile ions in hydrated BSA and the formation of EDLCs are discussed.     

Annealing temperature effect on electrical and structural properties of Cu/Au Schottky contacts to n-type GaN

Schottky contacts were fabricated on n-type GaN using a Cu/Au metallization scheme, and the electrical and structural properties have been investigated as a function of annealing temperature by current-voltage (I-V), capacitance-voltage (C-V), Auger electron spectroscopy (AES) and X-ray diffraction (XRD) measurements. The extracted Schottky barrier height of the as-deposited contact was found to be 0.69 eV (I-V) and 0.77 eV (C-V), respectively. However, the Schottky barrier height of the Cu/Au contact slightly increases to 0.77 eV (I-V) and 1.18 eV (C-V) when the contact was annealed at 300 °C for 1 min. It is shown that the Schottky barrier height decreases to 0.73 eV (I-V) and 0.99 eV (C-V), 0.56 eV (I-V) and 0.87 eV (C-V) after annealing at 400 °C and 500 °C for 1 min in N₂ atmosphere. Norde method was also used to extract the barrier height of Cu/Au contacts and the values are 0.69 eV for the as-deposited, 0.76 eV at 300 °C, 0.71 eV at 400 °C and 0.56 eV at 500 °C which are in good agreement with those obtained by the I-V method. Based on Auger electron spectroscopy and X-ray diffraction results, the formation of nitride phases at the Cu/Au/n-GaN interface could be the reason for the degradation of Schottky barrier height upon annealing at 500 °C.     

n-GaAs Schottky diodes metallized with Ti and Pt/Ti

The electrical characteristics and interdiffusion in n-GaAs Schottky diodes containing Ti and Pt/Ti have been studied using I-V, C-V, X-ray diffraction and Rutherford backscattering measurements. Thermal aging of the diodes was carried out in vacuo at 350 and 500°C. The Ti/n-GaAs diodes show near-ideal forward I-V characteristics with the ideality parameter $\text{n ? 1·03}$ and the barrier height φ_B ～ 0·84V. C-V data yield the same φ_B. No interdiffusion was observed at 350°C. At 500°C, TiAs forms but the φ_B remains unchanged. Pt/Ti/n-GaAs diodes behave “Pt-like” upon aging at 500°C with φ_B ～ 0·9V and n ～ 1·1. The TiAs formed at 500°C is ineffective in preventing a subsequent Pt/GaAs interaction which leads to a layered arrangement of reaction products consisting of Pt₃Ga/TiAs/PtAs₂/n-GaAs.     

Influence of rapid thermal annealing temperature on structure and electrical properties of high permittivity HfTiO thin film used in MOSFET

HfTiO thin films were prepared by r.f. magnetron co-sputtering on Si substrate. To improve the electrical properties, HfTiO thin films were post heated by rapid thermal annealing (RTA) at 400 °C, 500 °C, 600 °C and 700 °C in nitrogen. It was found that the film is amorphous below 700 °C and at 700 °C monoclinic phase HfO₂ has occurred. With the increase of the annealing temperature, the film becomes denser and the refractive index increases. By electrical measurements, we found at 500 °C annealed condition, the film has the best electrical property with the largest dielectric constant of 44.0 and the lowest leakage current of 1.81 × 10⁻⁷ A/cm², which mainly corresponds to the improved microstructure of HfTiO thin film. Using the film annealed at 500 °C as the replacement of SiO₂ dielectric layer in MOSFET, combining with TiAlN metal electrode, a 10 μm gate-length MOSFET fabricated by three-step photolithography processes. From the transfer (I_DS–V_G) and output (I_DS–V_DS) characteristics, it shows a good transistor performance with a threshold voltage (V_th) of 1.6 V, a maximum drain current (I_ds) of 9 × 10⁻⁴ A, and a maximum transconductance (G_m) of 2.2 × 10⁻⁵ S.     

Electrical properties of vacuum annealed La2O3 thin films grown by E-beam evaporation

In this article, the conduction mechanisms of metal-oxide-semiconductor with vacuum annealed Lanthana (La₂O₃) oxide film are investigated. Lanthana films with thicknesses of 3.5, 4.7, and 11 nm were deposited by E-beam evaporation on n-Si (100), and annealed at various temperatures (300-500 °C) in ultra-high vacuum (10⁻¹⁰-10⁻⁹ Torr) for 90 min. From the measurement of spectroscopic ellipsometry, it is found that film thickness is increased with annealing temperature, which would be cause of flat-band voltage shift (ΔV_FB) due to the growth of interfacial layer. From the capacitance measurement, it is found that ΔV_FB of the film is reduced by post-deposition anneal (PDA) compared to that of as-deposited film, but increase again at high temperature annealing, especially in the case of thin film (3.5 nm). From the applied voltage and temperature dependence of the leakage current of the film, with different gate electrode materials (Ag, Al, and Pt), it is shown that the leakage currents are associated with ohmic and Poole-Frenkel (P-F) conductions when flat-band voltage (V_FB) is less than zero, and ohmic and Space-Charge-Limited Current (SCLC) conductions when V_FB is greater than zero. The dielectric constants obtained from P-F conduction for Al gate electrode case is found to be 11.6, which is consistent with the C-V result 11.9. Barrier height of trap potential well is found to be 0.24 eV from P-F conduction. Based on SCLC theory, leakage currents of 3.5 and 11 nm films with different PDA temperatures are explained in terms of oxide trap density.     

Characterization of polycrystalline 3C-SiC thin film diodes for extreme environment applications

This paper describes the fabrication and characteristics of polycrystalline (poly) 3C-SiC thin film diodes for extreme environment applications, in which the poly 3C-SiC thin film was deposited onto oxidized Si wafers by APCVD using HMDS as a precursor. In this work, the optimized growth temperature and HMDS flow rate were 1100 °C and 8 sccm, respectively. A Schottky diode with a Au, Al/poly 3C-SiC/SiO₂/Si(n-type) structure was fabricated and its threshold voltage (V_d), breakdown voltage, thickness of depletion layer, and doping concentration (N_D) values were measured as 0.84 V, over 140 V, 61 nm, and 2.7 × 10¹⁹ cm³, respectively. To produce good ohmic contact, Al/3C-SiC were annealed at 300, 400, and 500 °C for 30 min under a vacuum of 5.0 × 10⁻⁶ Torr. The obtained p-n junction diode fabricated by poly 3C-SiC had similar characteristics to a single 3C-SiC p-n junction diode.     

Effect of plasma process-induced damage on bias temperature instability of MOSFETs

For a surface-channel n-MOSFET and a buried-channel p-MOSFET, the effect of plasma process-induced damage on bias temperature instability (BTI) was investigated. The gate oxide thickness, t_ox, of the test MOSFETs was 2.0, 3.0, or 4.5 nm. The shifts of threshold voltage V_th and of linear drain current I_dlin were measured after applying a BTI stress at a temperature of 125 °C. The measured shifts of V_th and I_dlin indicate that BTI on ultra-thin gate CMOS devices appears only in the form of SiO₂/Si interface degradation, and that the positive BTI for the n-MOSFET as well as the negative BTI for the p-MOSFET is important for the reliability evaluation of CMOS devices. Because of positive plasma charging to the gate, a protection diode was very efficient at reducing BTI for the p-MOSFET, but it was much less effective for the n-MOSFET.     

AlGaN/GaN self-aligned MODFET with metal oxide gate for millimeter wave application

As promising candidates for future microwave power devices, GaN-based high-electron mobility transistors (HEMTs) have attracted much research interest. An investigation of the operation of AlGaN/GaN n type self-aligned MOSFET with modulation doped GaN channels is presented. Liquid phase deposited (LPD) SiO₂ is used as the insulating material. An analytical model based on modified charge control equations is developed. The investigated critical parameters of the proposed device are the maximum drain current (I_Dmax), the threshold voltage (V_th), the peak DC trans-conductance (g_m), break down voltage (V_br) and unity current gain cut-off frequency (f_T). The typical DC characteristics for a gate length of 1 μm with 100 μm gate width are following: I_max=800 mA/mm, V_break-down=50 V, g_{m_extrinsic}=200 mS/mm, V_pinchoff=−10 V. The analysis and simulation results on the transport characteristics of the MOS gate MODFET structure is compared with the previously measured experimental data. The calculated values of f_T (20-130 GHz) suggest that the operation of the proposed device effectively, has sufficiently high current gain cutoff frequencies over a wide range of drain voltage, which is essential for high-power performance at microwave frequencies. The proposed device offers lower on-state resistance. The results so obtained are in close agreement with the experimental data.     

Charge trapping and interface characteristics in normally-off Al2O3/GaN-MOSFETs

Normally-off GaN-MOSFETs with Al₂O₃ gate dielectric have been fabricated and characterized. The Al₂O₃ layer is deposited by ALD and annealed under various temperatures. The saturation drain current of 330 mA/mm and the maximum transconductance of 32 mS/mm in the saturation region are not significantly modified after annealing. The subthreshold slope and the low-field mobility value are improved from 642 to 347 mV/dec and from 50 to 55 cm² V⁻¹ s⁻¹, respectively. The I_D-V_G curve shows hysteresis due to oxide trapped charge in the Al₂O₃ before annealing. The amount of hysteresis reduces with the increase of annealing temperature up to 750 °C. The Al₂O₃ layer starts to crystallize at a temperature of 850 °C and its insulating property deteriorates.