SafeResynth: A new technique for physical synthesis

Physical synthesis is a relatively young field in Electronic Design Automation. Many published optimizations for physical synthesis end up hurting the quality of the final design, often because they neglect important physical aspects of the layout, such as long wires or routing congestion. Our work defines and explores the concept of physical safeness and evaluates empirically its impact on route length, via count and timing. In addition, we propose a new physically safe and logically sound optimization, called SafeResynth, which provides immediately measurable improvements without altering the design's functionality. SafeResynth can enhance circuit timing without detrimental effects on route length and congestion. We achieve these improvements by performing a series of netlist transformations and re-placements that are individually evaluated for logical soundness (that is, they do not alter the logic functionality) and for physical safeness. When used alone, SafeResynth improves circuit delay of IWLS’05 benchmarks by 11% on average after routing, while increasing route length by less than 0.2%. Since transistors are not affected by SafeResynth, it can also be applied to post-silicon debugging, where only metal fixes are possible.     

Minimizing detection-to-boosting latency toward low-power error-resilient circuits

Dynamic voltage scaling (DVS) has become one of the most effective approaches to achieve ultra-low-power SoC. To eliminate timing errors arising from DVS, several error-resilient circuit design techniques were proposed to detect and/or correct timing violations. The most recently proposed time-borrowing-and-local-boosting (TBLB) technique has the advantage of lower power consumption and less performance degradation due to the needlessness of pipeline stalls. On the other hand, to make the best use of the TBLB technique, the latency from error detection to voltage boosting for TBLB latches must be carefully considered, especially during physical design. To address this issue, this paper first introduces the behavior of TBLB circuits, and then presents two major design styles of TBLB latches, including TBLB macros and multi-bit TBLB latches, for reducing detection-to-boosting latency. The corresponding physical synthesis methodologies for both design styles are further proposed. Experimental results based on the IWLS benchmarks show that the proposed physical synthesis approach for resilient circuits with multi-bit TBLB latches is very effective in reducing the delay of both combinational and error-detection circuits, which indicates better circuit reliability. To our best knowledge, this is the first work in the literature which introduces the physical synthesis methodologies for TBLB resilient circuits.     

Crosstalk noise reduction in synthesized digital logic circuits

As CMOS technology scales into the deep submicrometer regime, digital noise is becoming a metric of importance comparable to area, timing, and power, for analysis and design of CMOS VLSI systems. Noise has two detrimental effects in digital circuits: First, it can destroy logical information carried by a circuit net. Second, it causes delay uncertainty: Non critical paths might become critical because of noise. As a result, circuit speed becomes limited by noise, primarily because of capacitive coupling between wires. Most design approaches address the crosstalk noise problem at the layout generation stage, or via postlayout corrections. With continued scaling, too many circuit nets require corrections for noise, causing a design convergence problem. This work suggests to consider noise at the gate-level netlist generation stage. The paper presents a simplified analysis of on-chip crosstalk models, and demonstrates the significance of crosstalk between local wires within synthesized circuit blocks. A design flow is proposed for automatically synthesizing CMOS circuits that have improved robustness to noise effects, using standard tools, by limiting the range of gate strengths available in the cell library. The synthesized circuits incur a penalty in area/power, which can be partially recovered in a single postlayout corrective iteration. Results of design experiments indicate that delay uncertainty is the most important noise-related concern in synthesized static CMOS logic. Using a standard synthesis methodology, critical path delay differences up to 18% of the clock cycle time have been observed in functional blocks of microprocessor circuits. By using the proposed design flow, timing uncertainty was reduced to below 3%, with area and power penalties below 20%.     

Accurate circuit model of interdigital capacitor and itsapplication to design of new quasi-lumped miniaturized filters withsuppression of harmonic resonance

A general-purpose circuit model of a microstrip interdigital capacitor (IDC) is presented in this paper for use in the design of new quasi-lumped miniaturized filters. This computer-aided-design-oriented model is developed as a versatile admittance π-network with the short-open calibration technique that we have recently proposed for accurate parameter extraction of a circuit from its physical layout. This technique is self-contained in our method of moments, which accounts for frequency dispersion and fringing effects. A J-inverter topology is further conceived to explicitly formulate the coupling behavior of three types of IDC's. This model provides a unique way for the IDC-related circuit synthesis and optimization based on the accurate equivalent-circuit network extracted from the field theory algorithm. It is validated theoretically and experimentally through an example of a line resonator connected with two IDC's. The proposed scheme is used in the design and optimization of new low-loss miniaturized quasilumped integrated circuits, namely, two types of three-pole direct-coupled bandpass filters. Our measured and predicted results show interesting features of the proposed filter structure such as size reduction and suppression of harmonic resonance if the line resonator is attached by series-connected equivalent inductance     

Verification of physical designs using an integrated reverse engineering flow for nanoscale technologies

Considering the potential risks of piracy and malicious manipulation of complex integrated circuits using worldwide distributed manufacturing sites, an effective and efficient reverse engineering process allows the verification of the physical layout against the reference design. This paper provides an overview of the current process and details on a new tool for the acquisition and synthesis of large area images and the recovery of the design from a physical device. Using this reverse engineering process on a physical chip layout, a circuit graph based partitioning of circuit blocks and an Elliptic Curve Cryptography (ECC) module identification will be performed. For the first time, the error between the generated layout and the design GDS layout will be compared quantitatively as a figure of merit (FoM). We propose a new classification of malicious manipulations based on their layout impact.     

基于多级协同混淆的硬件IP核安全防护设计

传统硬件混淆从物理级、逻辑级、行为级等进行单层次混淆,没有发挥多级协同优势,存在安全隐患。该文通过对物理版图、电路逻辑和状态跳变行为的关系研究,提出多级协同混淆的硬件IP核防护方法。该方案首先在自下而上协同混淆中,采用虚拟孔设计版图级伪装门的方式进行物理-逻辑级混淆,采用过孔型物理不可克隆函数(PUF)控制状态跳变的方式实现物理-行为级混淆;然后,在自上而下协同混淆中,利用密钥控制密钥门进行行为-逻辑级混淆,利用并行-支路混淆线的方法完成行为-物理级混淆;最后提出混淆电路在网表的替换机制,设计物理-逻辑-行为的3级协同混淆,实现多级协同混淆的IP核安全防护。ISCAS-89基准电路测试结果表明,在TSMC 65 nm工艺下,多级协同混淆IP核在较大规模测试电路中的面积开销占比平均为11.7%,功耗开销占比平均为5.1%,正确密钥和错误密钥下的寄存器翻转差异低于10%,所提混淆方案可有效抵御暴力攻击、逆向工程、SAT等攻击。     

An MTCMOS technology for low-power physical design

Multi-threshold CMOS (MTCMOS) technology is an effective sub-threshold leakage power reduction method in CMOS circuits, which satisfies high-performance and low-power design requirements. The optimization of virtual supply network plays an important role in MTCMOS low-power design. Existing low-power works are mainly on gate level, without any optimization on physical design level, which can lead to a large amount of virtual supply networks. Merging the objective of virtual networks minimization into physical design, this paper presents (1) a low-power-driven physical design flow; (2) a novel low-power placement to simultaneously place standard cells and sleep transistors; and (3) the sleep transistor relocation technique to further reduce the virtual supply networks. Experimental results are promising for both achieving up to 28.15% savings for virtual supply networks and well controlling the increase of signal nets.     

基于矩阵变换的线性最近邻量子线路综合与优化

为了构造线性最近邻量子线路,降低线性量子可逆线路的量子代价,提出了一种基于矩阵变换的线性量子线路综合与优化方法.该方法给出了线路的矩阵表示和基于矩阵的近邻CNOT（Controlled NOT Gate）门判定,并提出矩阵分组的最佳方案,保证了线路综合中CNOT门数量最优.为了实现量子线路近邻化,提出了swap门的矩阵表示及线路近邻化规则,证明了两种swap门添加方式的等效性;提出了不同情况下swap门的消除规则,降低了近邻化后量子线路的量子代价.选择benchmark例题库中具有代表性的线路进行实验,与已有的量子线路近邻化算法相比,线路量子代价平均优化率为34.31%.     

3V/5V标准单元混合使用的芯片设计

讨论了 0 .9μm标准单元正向设计流程中当电路中存在 5 V和 3 V两种电压时芯片的设计方法 ,包括网表产生与验证 ,版图设计 ,电压转换单元的加入原则。     

Design of Parasitic and Process-Variation Aware Nano-CMOS RF Circuits: A VCO Case Study

This paper proposes a novel flow for parasitic and process-variation aware design of radio-frequency integrated circuits (RFICs). A nano-CMOS current-starved voltage controlled oscillator (VCO) circuit has been designed using this flow as a case study. The oscillation frequency is considered as the objective optimization function with the area overhead as constraint. Extensive Monte Carlo simulations have been carried out on the parasitic extracted netlist of the VCO to study the effect of process variation on the oscillation frequency. In the design cycle, a performance degradation of 43.5% is observed when the parasitic extracted netlist is subjected to worst-case process variation. The proposed design flow could bring the oscillation frequency within 4.5% of the target, leading to convergence of the complete design in only one design iteration. To the best of the authors' knowledge, this paper presents the first work focussed on a current starved VCO in which the combined effect of parasitics and process variations has been considered.      

具有高资源利用率特征的改进型查找表电路结构与优化方法

该文着重研究了FPGA芯片中核心模块基本可编程逻辑单元(BLE)的电路结构与优化设计方法,针对传统4输入查找表(LUT)进行逻辑操作和算术运算时资源利用率低的问题,提出一种融合多路选择器的改进型LUT结构,该结构具有更高面积利用率;同时提出一种对映射后网表进行统计的评估优化方法,可以对综合映射后网表进行重新组合,通过预装箱产生优化后网表;最后,对所提结构进行了实验评估和验证。结果表明:与Intel公司Stratix系列FPGA相比,采用该文所提优化结构,在MCNC电路集和VTR电路集下,资源利用率平均分别提高了10.428% 和 10.433%,有效提升了FPGA的逻辑效能。     

Novel design of a fast reversible Wallace sign multiplier circuit in nanotechnology

Today, reversible logic is emerging as an intensely studied research topic, having applications in diverse fields, such as low-power design, optical information processing, and quantum computation. In this paper, we have proposed two reversible Wallace signed multiplier circuits through modified Baugh-Wooley approach, which are much better than the two available counterparts in all the terms. The multiplier is an essential building block for the construction of computational units of quantum computers. Besides, we need signed multiplier circuits for numerous operations. However, only two reversible signed multiplier circuits have been presented so far. In the first proposed architecture, our goals are to decrease the depth of the circuit and to increase the speed of the circuit. In the second proposed circuit, we aimed to improve the quantum cost, garbage outputs, and other parameters. All the proposed circuits are in the nanometric scales and can be used in the design of very complex systems.     

An ant colony based mapping of quantum circuits to nearest neighbor architectures

Although this decade is witnessing tremendous advancements in fabrication technologies for quantum circuits, this industry is facing several design challenges and technological constraints. Nearest Neighbor (NN) enforcement is one such design constraint that demands the physical qubits to be adjacent. In the last couple of years, this domain has made progress starting from designing advanced algorithms to improved synthesis methodologies, even though developing efficient design solutions remains an active area of research.Here, we propose such a synthesis technique that efficiently transforms quantum circuits to NN designs. To find the NN solution, we have taken help of an ant colony algorithm which completes the circuit conversion in two phases: in the first phase, it finds the global qubit ordering for the input circuit and, in the second phase, a heuristic driven look-ahead scheme is executed for local reordering of gates. The proposed algorithm is first fitted into a 1D design and, later, mapped to 2D and 3D configurations. The combination of such heuristic and the meta-heuristic schemes has resulted promising solutions in the transformation of quantum circuits to NN-compliant architectures. We have tested our algorithm over a wide spectrum of benchmarks and comparisons with state-of-the-art design approaches showed considerable improvements.     

Automatic layout synthesis of analog ICs using circuit recognition and constraint analysis techniques

A systematic method for automatic layout synthesis of analog integrated circuit modules is presented. This method uses analog circuit recognition and critical net analysis techniques to derive proper layout constraints for analog circuit performance optimization. These layout constraints are analyzed and prioritized according to the recognized analog circuit topologies and classified net sensitivities. The weighted constraints are then used to drive the physical layout generation process to obtain a high-quality custom circuit layout. An efficient, constraint-driven analog floorplanning technique based on a zone-sensitivity partitioning algorithm is specially developed to generate a slicing floorplan incorporating the layout constraints. This layout synthesis approach has three key advantages. First, it can produce a satisfactory analog circuit performance with negligible degradation due to the layout-introduced parasitic effects. Second, it allows a complete automation for netlist-to-layout synthesis so that the layout tool can be used by VLSI system designers. Finally, this method is quite general and can be applied to handle a wide variety of analog circuits. Experimental results in CMOS operational amplifiers and a comparator are presented.     

基于矩阵初等变换的四量子比特可逆电路综合算法

 量子可逆电路实现信息变换的过程可用一个酉矩阵算子表示,采用酉矩阵表示量子可逆电路能更好地反映量子系统的演化,体现量子计算所特有的属性.本文提出基于矩阵初等变换的4量子比特可逆电路综合算法.该算法恰当地利用量子电路的矩阵表示及变换和邻接矩阵的电路转化规则,总能以较小的量子代价综合出任意给定置换的4量子比特可逆逻辑电路.     

基于改进遗传算法的量子可逆电路综合

针对可逆电路到量子电路的有效映射问题,提出了带禁忌表的大变异自适应遗传算法,用于量子可逆电路的综合.选取量子非门、控制非门、控制V门与控制V+门(NCV)构成量子门库,建立了量子电路计算模型.采用二进制串行编码方案,设计了适应度函数、进化算子及优化规则,实现了带禁忌表大变异自适应遗传算法的量子可逆电路综合,并用Revlib电路库进行了测试.结果表明该综合方法能同时得到多个功能解,且所生成电路的量子代价优于库中电路,验证了提出算法用于量子可逆电路综合的正确性和有效性.     

一种适用于门级网表的混合式静态功耗优化方法

进入深亚微米集成电路设计阶段,静态功耗所占整体功耗的比例快速增大,使之成为当前设计流程中的关键优化步骤。该文提出一种适用于门级网表的混合式静态功耗优化方法。该方法结合了整数规划和启发式算法,以减小电路时序裕量的方式换取电路静态功耗的改善。整体优化流程从一个满足时序约束的设计开始,首先利用整数规划为网表中的逻辑门单元寻找一个较低静态功耗的最优替换单元;其次结合当前所用门单元和最优替换单元的物理和电学参数,按优先级方式逐层替换电路中所有的逻辑门节点;最后利用启发式方法修复可能出现的最大延时违规情况。整体优化流程将在上述步骤中不断迭代直至无法将现有时序裕量转换为功耗的改善。针对通用测试电路的实验结果表明,采用该方法优化后电路静态功耗平均减小10%以上,最高达26%;与其它方法相比,该方法不仅大幅降低了功耗,而且避免了优化后电路最大延时的过度恶化,其最大延时违反量小于5 ps。