Soft error modeling and remediation techniques in ASIC designs

Soft errors due to cosmic radiations are the main reliability threat during lifetime operation of digital systems. Fast and accurate estimation of soft error rate (SER) is essential in obtaining the reliability parameters of a digital system in order to balance reliability, performance, and cost of the system. Previous techniques for SER estimation are mainly based on fault injection and random simulations. In this paper, we present an analytical SER modeling technique for ASIC designs that can significantly reduce SER estimation time while achieving very high accuracy. This technique can be used for both combinational and sequential circuits. We also present an approach to obtain uncertainty bounds on estimated error propagation probability (EPP) values used in our SER modeling framework. Comparison of this method with the Monte-Carlo fault injection and simulation approach confirms the accuracy and speed-up of the presented technique for both the computed EPP values and uncertainty bounds.Based on our SER estimation framework, we also present efficient soft error hardening techniques based on selective gate resizing to maximize soft error suppression for the entire logic-level design while minimizing area and delay penalties. Experimental results confirm that these techniques are able to significantly reduce soft error rate with modest area and delay overhead.     

Characterizing,modeling, and analyzing soft error propagation in asynchronous and synchronous digital circuits

Soft errors, due to cosmic radiations, are one of the major challenges for reliable VLSI designs. In this paper, we present a symbolic framework to model soft errors in both synchronous and asynchronous designs. The proposed methodology utilizes Multiway Decision Graphs (MDGs) and glitch-propagation sets (GP sets) to obtain soft error rate (SER) estimation at gate level. This work helps mitigate design for testability (DFT) issues in relation to identifying the controllable and the observable circuit nodes, when the circuit is subject to soft errors. Also, this methodology allows designers to apply radiation tolerance techniques on reduced sets of internal nodes. To demonstrate the effectiveness of our technique, several ISCAS89 sequential and combinational benchmark circuits, and multiple asynchronous handshake circuits have been analyzed. Results indicate that the proposed technique is on average 4.29 times faster than the best contemporary state-of-the-art techniques. The proposed technique is capable to exhaustively identify soft error glitch propagation paths, which are then used to estimate the SER. To the best of our knowledge, this is the first time that a decision diagram based soft error identification approach is proposed for asynchronous circuits.     

Sequential Element Design With Built-In Soft Error Resilience

This paper presents a built-in soft error resilience (BISER) technique for correcting radiation-induced soft errors in latches and flip-flops. The presented error-correcting latch and flip-flop designs are power efficient, introduce minimal speed penalty, and employ reuse of on-chip scan design-for-testability and design-for-debug resources to minimize area overheads. Circuit simulations using a sub-90-nm technology show that the presented designs achieve more than a 20-fold reduction in cell-level soft error rate (SER). Fault injection experiments conducted on a microprocessor model further demonstrate that chip-level SER improvement is tunable by selective placement of the presented error-correcting designs. When coupled with error correction code to protect in-pipeline memories, the BISER flip-flop design improves chip-level SER by 10 times over an unprotected pipeline with the flip-flops contributing an extra 7-10.5% in power. When only soft errors in flips-flops are considered, the BISER technique improves chip-level SER by 10 times with an increased power of 10.3%. The error correction mechanism is configurable (i.e., can be turned on or off) which enables the use of the presented techniques for designs that can target multiple applications with a wide range of reliability requirements     

Analytical Techniques for Soft Error Rate Modeling and Mitigation of FPGA-Based Designs

Radiation-induced soft errors are the major reliability threat for digital VLSI systems. In particular, field-programmable gate-array (FPGA)-based designs are more susceptible to soft errors compared to application-specific integrated circuit implementations, since soft errors in configuration bits of FPGAs result in permanent errors in the mapped design. In this paper, we present an analytical approach to estimate the soft error rate of designs mapped into FPGAs. Experimental results show that this technique is orders of magnitude faster than the fault injection method while more than 96% accurate. We also present a highly reliable and low-cost soft error mitigation technique which can significantly improve the availability of FPGA-mapped designs. Experimental results show that, using this technique, the availability of an FPGA mapped design can be increased to more than 99.99%.     

Obtaining FPGA soft error rate in high performance information systems

Soft errors due to cosmic particles are a growing reliability threat for VLSI systems. The vulnerability of FPGA-based designs to soft errors is higher than ASIC implementations since the majority of chip real estate is dedicated to memory bits, configuration bits, and user bits. Moreover, Single Event Upsets (SEUs) in the configuration bits of SRAM-based FPGAs result in permanent errors in the mapped design.FPGAs are widely used in the implementation of high performance information systems. Since the reliability requirements of these high performance information sub-systems are very stringent, the reliability of the FPGA chips used in the design of such systems plays a critical role in the overall system reliability. In this paper, we compare and validate the soft error rate of FPGA-based designs used in the Logical Unit Module board of a commercial information system with the field error rates obtained from actual field failure data. This comparison confirms that our analytical tool is very accurate (there is an 81% overlap in FIT rate range obtained with our analytical modeling framework and the field failure data studied). It can be used for identifying vulnerable modules within the FPGA for cost-effective reliability improvement.     

Fault Tolerant Single Error Correction Encoders

Soft errors are an important issue for circuit reliability. To mitigate their effects on the system functionality, different techniques are used. In many cases Error Correcting Codes (ECC) are used to protect circuits. Single Error Correction (SEC) codes are commonly used in memories and can effectively remove errors as long as there is only one error per word. Soft errors however may also affect the circuits that implement the Error Correcting Codes: the encoder and the decoder. In this paper, the protection against soft errors in the ECC encoder is studied and an efficient fault tolerant implementation is proposed.     

A cross-layer SER analysis in the presence of PVTA variations

As the technology scaling enters into the nanoscale regime, soft errors become one of the major challenging issues for VLSI chips. Susceptibility to soft error is even becoming more severe in the presence of workload-dependent Process, Voltage, Temperature, and Transistor Aging (PVTA) variations. In this paper, we propose a systematic cross-layer methodology to model and analyze the impact of different abstraction layers on the PVTA variations and in turn on the susceptibility of processors to soft error. To do so, the workload is divided into several fine-grained timing windows. Based on a top-down profiling approach, the effects of each window is projected into the circuit-level model of the processor in order to extract PVTA profiles of “each cell” in the circuit. Finally, at circuit-level, an “instance-based” simulation flow is exploited to capture both spatial and temporal PVTA-aware Soft Error Rate (SER) variations within/across applications for every functional block of the processor. The simulation results for various ITC’99 benchmark circuits and the LEON3 processor running different benchmark applications show that disregarding PVTA information results in significant error in the estimated SER.     

Soft error estimation and mitigation of digital circuits by characterizing input patterns of logic gates

Soft errors caused by particles strike in combinational parts of digital circuits are a major concern in the design of reliable circuits. Several techniques have been presented to protect combinational logic and reduce the overall circuit Soft Error Rate (SER). Such techniques, however, typically come at the cost of significant area and performance overheads. This paper presents a low area and zero-delay overhead method to protect digital circuits’ combinational parts against particles strike. This method is made up of a combination of two sub-methods: (1) a SER estimation method based on signal probability, called Estimation by Characterizing Input Patterns (ECIP) and (2) a protection method based on gate sizing, called Weighted and Timing Aware Gate Sizing (WTAGS). Unlike the previous techniques that either overlook internal nodes signal probability or exploit fault injection, ECIP computes the sensitivity of each gate by analytical calculations of both the probability of transient pulse generation and the probability of transient pulse propagation; these calculations are based on signal probability of the whole circuit nodes which make ECIP much more accurate as well as practical for large circuits. Using the results of ECIP, WTAGS characterizes the most sensitive gates to efficiently allocate the redundancy budget. The simulation results show the SER reduction of about 40% by applying the proposed method to ISCAS’89 benchmark circuits while imposing no delay overhead and 5% area overhead.     

CEP: Correlated Error Propagation for Hierarchical Soft Error Analysis

Due to the continuous technology scaling, soft error becomes a major reliability issue at nanoscale technologies. Single or multiple event transients at low levels can result in multiple correlated bit flips at logic or higher abstraction levels. Addressing this correlation is essential for accurate low-level soft error rate estimation, and more importantly, for the cross-level error abstraction, e.g. from bit errors at logic level to word errors at register-transfer level. This paper proposes a novel error estimation method to take into consideration both signal and error correlations. It unifies the treatment of error-free signals and erroneous signals, so that the computation of error probabilities and correlations can be carried out using techniques for signal probabilities and correlations calculation. The proposed method not only reports accurate error probabilities when internal gates are impaired by soft errors, but also gives quantification of the error correlations in their propagation process. This feature enables our method to be a versatile technique used in high-level error estimation. The experimental results validate our proposed technique showing that compared with Monte-Carlo simulation, it is 5 orders of magnitude faster, while the average inaccuracy of error probability estimation is only 0.02.     

Soft errors induced by alpha particles

Soft errors induced by alpha particles can be a reliability concern for microelectronics, especially semiconductor memory devices packaged in ceramic. In dynamic random-access memory devices (DRAM), the data are stored as the presence or absence of minority carrier charges on storage capacitors. For example, in n-channel MOS memory devices, the charge carriers are electrons and the capacitors are potential wells in the p-type silicon. Alpha particles emitted from trace levels of uranium and thorium in the packaging materials can penetrate the surface of the semiconductor die. As the alpha particle passes through the semiconductor device, electrons an dislodged from the crystal lattice sites along the track of the alpha particle. If the total number of generated electrons collected by an empty storage well exceeds the number of electrons that differentiates between a 1 and a 0, the collected electron charge can flip a 1 to a 0 generating a soft error in the memory device. The trend toward increased chip density, smaller device dimensions, and lower voltages further increases the susceptibility of DRAM to soft errors. The susceptibility of DRAM to soft errors is typically measured by accelerated tests or real-time SER tests, each of which have strengths and weaknesses. Knowledge of the factors which lead to soft errors can be used to improve reliability in DRAM by using a physics-of-failure approach to monitor variables in the manufacturing process resulting in building reliability into the manufacturing process     

An accurate model for soft error rate estimation considering dynamic voltage and frequency scaling effects

Due to shrinking feature size and higher transistor count in a single chip in modern fabrication technologies, power consumption and soft error reliability have become two critical challenges which chip designers are facing in new silicon integrated circuits. Recent studies have shown that these issues have compromising effects on each other. Besides, power consumption and reliability significantly vary across workloads and among pieces of a single application which can be exploited to design adaptive runtime fault tolerant and low power systems. These attractions have been exploited in prior studies to design online reconfigurable fault tolerant systems with power management schemes. However, those attempts are driven by complicated simulations and hardly deliver a sense of direction to the designers. To achieve maximum efficiency in terms of power, performance, and reliability in dynamic scaling of voltage and frequency, it is critical to have a simple and accurate reliability model which estimates the value of fault rate considering supply voltage and operating frequency of a circuit. In this paper, we propose an accurate formula for analytic modeling of the soft error rate of a system which can be used to precisely track the reliability of the system under dynamic voltage and frequency adjustments. The experimental results of this paper prove that our proposed model offers precise estimates of reliability in accordance with the results of accurate soft error rate (SER) estimation algorithm for ISCAS85’s benchmark circuits.     

A Stage-Wise Soft-Error Detection Scheme for Flip-Flop Based Pipelines in Secure Cloud Servers

The shrinking feature sizes make transistors increasingly susceptible to soft errors, which can severely degrade the systems’ RAS (Reliability, Availability, and Serviceability). The tough challenge results from not only increasing SER (soft error rate) of storage cells, but also the increasing susceptibility of combinational logics to soft errors. How to efficiently detect soft errors becomes the primary problem in the Backward Error Recovery (BER) schemes that are cost-effective in soft error tolerance. This paper presents a soft error detection scheme, AUDITOR, for flip-flop based pipelines. The AUDITOR copes with both types of soft errors—single event upset (SEU) and single event transient (SET). We propose a “local-audit” fault detection mechanism, by which each pipeline stage is verified independently and the verifying result registers with a dedicated “audit” bit (V-bit). All the V-bits are distributed across the whole pipeline and synergically monitor the pipeline execution. To relax the constraint of SET detection capability imposed by the inherent fully synchronous operation mode in flip-flop based pipelines, we firstly propose using path-compensation technique to address this constraint. Furthermore, a reuse-based design paradigm is employed to reduce the implementation complexity and area overhead. The AUDITOR possesses robust detection capability and short detection latency, at the expense of about 29 % and 50 % increase in area and power consumption, respectively.     

超深亚微米IC的宇宙射线辐射软失效研究

辐射引起的软失效一直是影响半导体可靠性的一个重大问题.特别是宇宙射线引起的在地球表面的高能中子,由于其特有的高穿透性很难有效屏蔽防护.介绍了其造成半导体器件软失效的失效机理,并利用加速软失效测试模型分别对90,65和45nm工艺的随机静态存储器的软失效率进行了分析,研究了该类中子造成的软失效率的影响因素及相关规律.据此预测了更高工艺技术产品的中子软失效率,在为芯片设计和制造阶段就对中子辐射可靠性的防护提供了一定的参考和依据.     

Design for Testability Techniques at the Behavioral and Register-Transfer Levels

Improving testability during the early stages of the design flow can have several benefits, including significantly improved fault coverage, reduced test hardware overheads, and reduced design iteration times. This paper presents an overview of high-level design methodologies that consider testability during the early (behavior and architecture) stages of the design flow, and their testability benefits. The topics reviewed include behavioral and RTL test synthesis approaches that generate easily testable implementations targeting ATPG (full and partial scan) and BIST methodologies, and techniques to use high-level information for ATPG.     

Soft errors issues in low-power caches

As technology scales, reducing leakage power and improving reliability of data stored in memory cells is both important and challenging. While lower threshold voltages increase leakage, lower supply voltages and smaller nodal capacitances reduce energy consumption but increase soft errors rates. In this work, we present a comprehensive study of soft error rates on low-power cache design. First, we study the effect of circuit level techniques, used to reduce the leakage energy consumption, on soft error rates. Our results using custom designs show that many of these approaches may increase the soft error rates as compared to a standard 6T SRAM. We also validate the effects of voltage scaling on soft error rate by performing accelerated tests on off-the-shelf SRAM-based chips using a neutron beam source. Next, we study the impact of cache decay and drowsy cache, which are two commonly used architectural-level leakage reduction approaches, on the cache reliability. Our results indicate that the leakage optimization techniques change the reliability of cache memory. More importantly, we demonstrate that there is a tradeoff between optimizing for leakage power and improving the immunity to soft error. We also study the impact of error correcting codes on soft error rates. Based on this study, we propose an adaptive error correcting scheme to reduce the leakage energy consumption and improve reliability.     

A practical metric for soft error vulnerability analysis of combinational circuits

Besides the advantages brought by technology scaling, soft errors have emerged as an important reliability challenge for nanoscale combinational circuits. Hence, it is important for vulnerability analysis of digital circuits due to soft errors to take advantage of practical metrics to achieve cost-effective and reliable designs. In this paper, a new metric called Triple Constraint Satisfaction probability (TCS) is proposed to evaluate the soft error vulnerability of combinational circuits. TCS is based on a concept called Probabilistic Vulnerability Window (PVW) which is an inference of the necessary conditions for soft-error occurrence in the circuit. We propose a computation model to calculate the PVW’s for all circuit gate outputs. In order to show the efficiency of the proposed metric, TCS is used in the vulnerability ranking of the circuit gates as the basic step of the vulnerability reduction techniques. The experimental results show that TCS provides a distribution of soft error vulnerability similar to that obtained with fault injections performed with HSPICE or with an event driven simulator while it is more than three orders of magnitude faster. Also, the results show that using the proposed metric in the well-known filter insertion technique achieves up to 19.4%, 34.1%, and 55% in soft error vulnerability reduction of benchmark circuits with the cost of increasing the area overhead by 5%, 10%, and 20%, respectively.     

Reducing vulnerability to soft errors in sub-100 nm content addressable memory circuits

We first study the impacts of soft errors on various types of CAM for different feature sizes. After presenting a soft error immune CAM cell, SSB-RCAM, we propose two kinds of reliable CAM, DCF-RCAM and DCK-RCAM.In addition, we present an ignore mechanism to protect dual cell redundancy CAMs against soft errors. Experimental results indicate that the 11T-NOR CAM cell has an advantage in soft error immunity. Based on 11T-NOR, the proposed reliable CAMs reduce the SER by about 81% on average with acceptable overheads. The SER of dual cell redundancy CAMs can also be decreased using the ignore mechanism in specific applications.