Enhancement of Johnson figure of merit in III‐V HEMT combined with discrete field plate and AlGaN blocking layer

The performance of AlGaN/GaN HEMT is enhanced by using discrete field plate (DFP) and AlGaN blocking layer. The AlGaN blocking layer provides an excellent confinement of electrons toward the GaN channel, resulting very low subthreshold drain current of 10^?8 A/mm. It reveals very high off state breakdown voltage (BV) of 342 V for 250 nm gate technology HEMT. The breakdown voltage achieved for the proposed HEMT is 23% higher when compared to the breakdown voltage of conventional field plate HEMT device. In addition, the DFP reduces the gate capacitance (C_G) from 12.04 × 10^?13 to 10.48 × 10^?13 F/mm. Furthermore, the drain current and transconductance (g_m) reported for the proposed HEMT device are 0.82 A/mm and 314 mS/mm, respectively. Besides, the cut‐off frequency (f_T) exhibited for the proposed HEMT is 28 GHz. Moreover, the proposed HEMT records the highest Johnson figure of merit (JFOM) of 9.57 THz‐V for 250 nm gate technology without incorporating T‐gate.     

Novel high voltage RESURF AlGaN/GaN HEMT with charged buffer layer

A novel reduced surface field (RESURF) Al GaN /GaN high electron mobility transistor(HEMT)with charged buffer layer is proposed. Its breakdown mechanism and on-state characteristics are investigated.The HEMT features buried Fluorine ions in the GaN buffer layer both under the Drift and the Gate region (FDG). The section of FDG under the drift region (FD) not only reduces the electric field (E-field) peak at the gate edge but also enhances the E-field in the drift region by the assisted depletion, leading to a significant improvement in breakdown voltage (BV). Moreover, the section of FDG under the gate (FG) enhances the back barrier and effectively prevents electron injecting from the source to form leakage current, thus a higher BV is achieved. The BV of the proposed HEMT sharply increases to 750 V from 230 V of conventional AlGaN /GaN HEMT with the same dimensional parameters, and the specific on-resistance (Ron,sp) just increases to1.21 m?·cm~2from 1.01 m?·cm~2.     

Breakdown voltage analysis for the new RESURF AlGaN/GaN HEMTs

This paper demonstrates that the depletion process for AlGaN/GaN high electron mobility tran-sistors(HEMTs)is different than that for silicon power devices by analyzing active region depletion.Based on the special breakdown principle that occurs in AlGaN/GaN HEMTs,we propose a new reduced surface field AlGaN/GaN HEMT with a double low-density drain(LDD)and a positively charged region near the drain to optimize the surface electric field and increase the breakdown voltage.In this structure,two negative charge regions with different doses are introduced into the polarization AlGaN layer to form a double LDD and decrease the high electric field near the gate by depleting two-dimensional electron gas.A positively charged region is added to the electrode near the drain to decrease the high electric field peak at the drain edge.By applying ISE(integrated systems engineering)simulation software,we verify that the virtual gate effect occurs in the AlGaN/GaN HEMTs.The breakdown voltage is improved from 257 V in the conventional structure to 550 V in the proposed structure.     

Electrical performance of static induction transistor with transverse structure

A novel static induction transistor with transverse surface gate structure was designed and successfully fabricated in this paper. Its basic electrical characteristics and frequency performance was investigated in depth. The optimum technological parameters such as source-gate space and epitaxial layer thickness for obtaining excellent frequency performance and high blocking voltage capacity were represented and discussed in detail. The main advantage of this work is that the performances of device were improved with simple structure and technological processes. The experimental and simulated results demonstrate the trans-conductance g_m and gate-source breakdown voltage BV_GS of the transverse type SIT increase from 60 to 87 ms and 20 to 26 V, respectively, in addition to obtaining higher than 100 MHz operating frequency under relatively simple technology processes compared with those of traditional vertical SIT.     

具有高斯型的倾斜表面漂移区的LDMOS的器件特性研究

本文提出一种具有高斯型的倾斜表面漂移区的LDMOS结构。P阱、沟道、源区、栅极等位于高斯中心的一侧,而漏端位于高斯中心的另一侧并靠近高斯中心,器件既具有倾斜表面漂移区的高耐压性,又具有VDMOS结构的高开态击穿特性和良好的安全工作区域。我们研究了高斯表面的弯曲程度对高斯型倾斜表面漂移区的影响。结果表明,P阱的长时间退火对具有高斯表面的漂移区的掺杂浓度分布有一定影响。具有高斯表面的倾斜漂移区的LDMOS结构在不同弯曲程度下器件耐压性和表面电场分布均匀性不同。高斯弯曲参数P在0.5左右时开态耐压性能最优,并且表面电场分布相对均匀;当弯曲参数P增大时,击穿特性基本饱和或略有下降。     

新型RESURF AlGaN/GaN HEMTs器件耐压分析

本文首先从器件有源区耗尽过程分析表明AlGaN/GaN HEMTs器件具有与传统Si功率器件不同的耗尽过程,针对AlGaN/GaN HEMTs器件特殊的耐压机理,提出了一种降低表面电场,提高击穿电压的新型RESURF AlGaN/GaN HEMTs结构.新结构通过在极化的AlGaN层中引入分区负电荷,辅助耗尽二维电子气,有效降低了引起器件击穿的栅极边缘高电场,并首次在漏极附近引入正电荷使漏端高电场峰降低.利用仿真软件ISE分析验证了AlGaN/GaN HEMTs器件具有的"虚栅"效应,通过电场和击穿特性分析获得,新结构使器件击穿电压从传统结构的257V提高到550V.     

高压CMOS电路的设计及制造工艺研究

介绍了一种与常规CMOS电路兼容的高压CMOS电路版图设计及工艺加工技术。在该技术中采用了非自对准的场区掺杂,增加场区掺杂浓度,轻掺杂漏区以形成漂移区等提高MOS晶体管击穿电压的一系列技术措施,使MOS晶体管的源漏击穿电压提高至35V以上,电路在24V电压下可以正常工作。     

Micromechanical switches fabricated using nickel surfacemicromachining

Micromechanical switches have been fabricated in electroplated nickel using a four-level surface micromachining process. The simplest devices are configured with three terminals, a source, a drain, and a gate and are 30 μm wide, 1 μm thick, and 65 μm long. A voltage applied between the gate and source closes the switch, connecting the source to the drain. Devices switch more than 10⁹ cycles before failure and exhibit long-lifetime hot switching currents up to 5 mA. The initial contact resistance is less than 50 mΩ. The breakdown (stand-off) voltage between the source and the drain is greater than 100 V and the off-current is less than 20 fA at 100 V     

空间激光通信系统精跟踪单元PZT驱动电源的设计

压电陶瓷驱动电源是压电陶瓷微位移器应用中的关键部件。PA85是一种高电压、高功率MOSFET的带宽运算放大器,采用双电源供电,输出电流高达200mA,输出电压更可高达±215V。该文详细介绍了基于PA85的一种电源复合放大器的设计及仿真,通过对各项性能指标的仿真表明,该驱动电源具有精度高、分辨率高、稳定性好、纹波小和电路结构简单等优点。     

Ultra-thin films and multigate devices architectures for future CMOS scaling

The nanoelectronics industry is facing historical challenges to scale down CMOS devices to meet demands for low voltage, low power, high performance and increased functionality. Using new materials and devices architectures is necessary. HiK gate dielectrics and metal gates have been introduced and have shown their ability to reduce power consumption. Fully depleted ultra-thin SOI devices are a good alternative to bulk for low power applications. Multigate devices are the current goal in device architecture...     

High-voltage constraints for vacuum packaged microstructures

In order to understand the details of high-field breakdown in microstructures that are vacuum packaged, a series of experiments are used to determine characteristics of microdischarges. The results support a reinterpretation of conventional assumptions based upon large scale discharges. When planar microelectrodes are used, Paschen's curve is not applicable in the traditional sense: the breakdown voltage is relatively insensitive to pressure in the 1-20 torr range, and remains at /spl sim/400 V for air ambient. However, the spatial distribution of discharge current does vary with the pressure and the power. Large voltage gradients are supported in the glow region which is confined to a few millimeters directly above the cathode, and within a few hundred microns of its lateral edge. Their magnitudes range from 100,000-500,000 V/m for operating pressures ranging from 1.2-6 torr. Based on these results, guidelines are provided for the design of high-voltage microsystems.     

低功耗高性能的全MOS电压基准源设计

设计了一种基于亚阈值技术的全MOS电压基准源,采用共源共栅结构来增大PSRR,使用MOS管代替电阻,优化温度特性,使电路中大部分MOS管工作于亚阈值区。基于0.18μm CMOS工艺进行设计、版图绘制、和前、后仿真,在后仿真中得出相关参数值。对各参数做出详细分析,包括:一定温度范围内的温度系数;常温下基准输出电压;不同电源电压条件下的线性调整率、基准源静态电流及功耗,并对不同频率下的电源电压抑制比进行了对比。实验结果表明达到了低功耗高性能的设计目标。     

A novel gate driver circuit for depletion‐mode a‐IGZO TFTs

In this paper, a novel gate driver circuit, which can achieve high reliability for depletion mode in a‐InGaZnO thin‐film transistors (TFTs), was proposed. To prevent the leakage current paths for Q node effectively, the new driving method was proposed by adopting the negative gate‐to‐source voltage (V_GS) value for pull‐down units. The results showed all the V_OUT voltage waveforms were maintained at VGH voltage despite depletion‐mode operation. The proposed circuit could also obtain stable V_OUT voltage when the threshold voltage for all TFTs was changed from ?6.5 to +11.5 V. Therefore, the circuit can achieve high reliability regardless of threshold voltage value for a‐IGZO TFTs. In addition, the output characteristics and total power consumption were shown for the alternating current (AC)–driven and direct current (DC)–driven methods based on 120‐Hz full‐HD graphics (1920 × 1080) display panel. The results showed that the AC‐driven method could achieve improved V_OUT characteristics compared with DC‐driven method since the leakage current path for Q node can be completely eliminated. Although power consumption of the AC‐driven method can be slightly increased compared with the DC‐driven method for enhancement mode, consumption can be lower when the operation has depletion‐mode characteristics by preventing a leakage current path for pull‐down units. Consequently, the proposed gate driver circuit can overcome the problems caused by the characteristics of a‐IGZO TFTs.     

时延约束下快速门级双电压分配算法

针对门级电压分配算法速度慢的问题,提出了一种时延约束下基于门分组的双电压分配算法。通过门工作在低、高电压下的延时差与时延裕量的比较,将门分为高电压门组和低电压门组;针对违反时延约束的关键路径上的低电压门（称为关键低电压门）,采用最小割法逐渐升高其电压至电路满足时延约束。通过对ISCAS’85标准电路测试的实验结果表明,与已发表的算法比较,不但功耗有一定改进,且算法速度快。     

Deviation-tolerant floating gate structures as a way to design an on-chip learning neural networks

 Hardware implementation of artificial neural networks (ANN) based on MOS transistors with floating gate (Neuron MOS or νMOS) is discussed. Choosing analog approach as a weight storage rather than digital improves learning accuracy, minimizes chip area and power dissipation. However, since weight value can be represented by any voltage in the range of supplied voltage (e.g. from 0 to 3.3 V), minimum difference of two values is very small, especially in the case of using neuron with large sum of weights. This implies that ANN using analog hardware approach is weak against V _dd deviation. The purpose of this paper is to investigate main parts of analog ANN circuits (synapse and neuron) that can compensate all kinds of deviation and to develop their design methodologies.     

High frequency performance of nano-scale ultra-thin-body Schottky-barrier n-MOSFETs

The high frequency performances of nano-scale ultra-thin-body (UTB) Schottky-barrier n-MOSFETs (SB-nMOSFETs) are investigated using 2D full-band self-consistent ensemble Monte Carlo method. The UTB SB-nMOSFET devices offer excellent RF performance with high values of f T and f max.The significant dependence of f T and f max on gate voltage and weak dependence on barrier height are demonstrated.Meanwhile,the significant dependence of g m and g ds on both gate voltage and SB height are shown. Moreover,the sca...     

An improved empirical large‐signal model for the GaAs‐ and GaN‐based HEMTs

A complete empirical large‐signal model for the GaAs‐ and GaN‐based HEMTs is presented. Three generalized drain current I–V models characterized by the multi‐bias Pulsed I–V measurements are presented along with their dependence on temperature and quiescent bias state. The new I–V equations dedicated for different modeling cases are kept accurate enough to the higher‐order derivatives of drain‐current. Besides, an improved charge‐conservative gate charge Q–V formulation is proposed to extract and model the nonlinear gate capacitances. The composite nonlinear model is shown to accurately predict the S‐parameters, large‐signal power performances as well as the two‐tone intermodulation distortion products for various types of GaAs and GaN HEMTs. © 2011 Wiley Periodicals, Inc. Int J RF and Microwave CAE , 2011.     

Novel self‐aligned top‐gate oxide TFT for AMOLED displays

Abstract— A novel highly reliable self‐aligned top‐gate oxide‐semiconductor thin‐film transistor (TFT) formed by using the aluminum (Al) reaction method has been developed. This TFT structure has advantages such as small‐sized TFTs, lower mask count, and small parasitic capacitance. The TFT with a 4‐μm channel length exhibited a field‐effect mobility of 21.6 cm²/V‐sec, a threshold voltage of ?1.2 V, and a subthreshold swing of 0.12 V/decade. Highly reliable TFTs were obtained after 300°C annealing without increasing the sheet resistivity of the source/drain region. A 9.9‐in.‐diagonal qHD AMOLED display was demonstrated with self‐aligned top‐gate oxide‐semiconductor TFTs for a low‐cost and ultra‐high‐definition OLED display. Excellent brightness uniformity could be achieved due to small parasitic capacitance.     

High‐reliability gate driver circuit to prevent ripple voltage

In this paper, a high‐reliability gate driver circuit is proposed to prevent multiple outputs. The proposed circuit ensures reliability of the pull‐up thin‐film transistor (TFT) by periodically discharging the Q node voltage to the low‐level voltage (VGL) in the off stage. In addition, the output node is composed of two pull‐down TFTs that are driven alternately to ensure stability against bias stress. Thus, because the reliabilities of the pull‐up and pull‐down TFTs can be guaranteed simultaneously, the stability of the entire circuit is improved. Based on the simulation results, the rising and falling times of the output pulse are stable within 1.77 and 1.28 μs, respectively, even when the threshold voltage of the entire TFT is shifted by +10.0 V. In addition, the ripple voltage of the proposed circuit is almost eliminated and is within 0.79% of the total swing voltage. Moreover, through current is prevented in the proposed circuit because the turn‐on durations of the pull‐up and pull‐down units are completely nonoverlapping, which suggests that unnecessary power consumption can be eliminated. Therefore, based on 2,160 stages, the total power consumption of the proposed circuit is reduced by 34.7 mW from 276.3 to 241.6 mW.     

基于DSP和CPLD的四相容错电机控制系统硬件设计

主要完成了一个以DSP2808为控制核心,结合CPLD进行组合逻辑控制的四相容错电机控制系统的硬件设计;系统通过CPLD发出控制信号控制H桥来驱动电机,通过霍尔电流、位置传感器来进行电机驱动电流、转子位置、电机转速信号的采集,将采集信号送入CPLD和DSP进行闭环控制;对280V供电电压条件下,IGBT的栅极电压和电机的相电压进行了测试,电压波形符合要求,电机运行良好;实际测试结果表明基于此硬件系统的控制电机具有功率大、运行可靠、带负载能力强等优点.