共查询到18条相似文献,搜索用时 78 毫秒
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高速数字电路设计中电源完整性分析 总被引:1,自引:0,他引:1
本文针对高速数字电路设计中的电源完整性问题,从地弹效应、多电源和地平面的分割以及电源模块的选择三方面进行分析,并结合具体设计探讨了解决电源完整性问题的方法。 相似文献
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研究了高速电路领域中的一类重要的电源完整性问题,即电源地平面之间激发的地弹噪声问题。地
弹噪声的存在严重破坏了电源/ 地平面的完整性,导致供电电压幅度的不稳定,严重之时甚至导致电路的误判。针
对这一问题,设计了一种超宽带电磁带隙结构。实验结果表明,这种电磁带隙结构可以在0. 5 ~5. 5GHz(11 倍频程)
频段内实现优于30dB 的噪声抑制能力。文章还探讨了带隙结构作为电源平面时信号传输的完整性。研究表明,如
果电路工作频率高达GHz 或更高,在电源/ 地平面采用这种带隙结构,可以有效地避免地弹噪声带来的影响,并保证
电源和信号的完整性。 相似文献
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高速PCB中旁路电容的分析 总被引:1,自引:0,他引:1
在当今高速数字系统设计中,电源完整性的重要性日益突出。其中,电容的正确使用是保证电源完整性的关键所在。本文针对旁路电容的滤波特性以及理想电容和实际电容之间的差别,提出了旁路电容选择的一些建议;在此基础上,探讨了电源扰动及地弹噪声的产生机理,给出了旁路电容放置的解决方案,具有一定的工程应用价值。 相似文献
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高速电路板的电磁兼容性分析 总被引:1,自引:1,他引:0
文章介绍了基于信号完整性(SI)、电源完整性(PI)与电磁兼容性(EMI)的高速PCB的设计方法,并利用Cadence软件针对高速PCB设计中的信号完整性、电源完整性及电磁兼容性中的基本问题进行仿真与分析。 相似文献
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信号完整性与电源完整性的仿真分析与设计 总被引:2,自引:0,他引:2
为了使设计人员对信号完整性与电源完整性有个全面的了解,文中对信号完整性与电源完整性的问题进行了仿真分析与设计,也从系统的角度对其进行了探讨. 相似文献
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引言电源完整性这一概念是以信号完整性为基础的,两者的出现都源自电路开关速度的提高。当高速信号的翻转时间和系统的时钟周期可以相比时,具有分布参数的信号传输线、电源和地就和低速系统中的情况完全不同了。与信号完整性是指信号在传输线上的质量相对应,电源完整性是指高速 相似文献
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提出了一种基于区域分解的二维有限元法分析多层印制电路板电源/地平面中过孔转换结构的信号完整性.过孔电流产生的电磁场呈三维结构,其中,一部分电磁波沿过孔轴向传输,另一部分电磁波在电源/地平面间沿径向传播.采用一虚拟柱面将求解区域分割为过孔区和电源/地平面区.将过孔区建模为以周向磁场为主分量的二维轴对称问题,而将电源/地平面区建为以垂直电场为主分量的二维模型.首先求解电源/地平面区的二维边值问题获得分割边界上节点的波阻抗,然后将该波阻抗代入过孔区模型中分割边界节点的边界条件,从而计算出过孔信号传输的S参数.所提方法通过模型缩减可实现对微细过孔结构信号完整性的精确快速计算,且采用全波电磁场分析软件对算法的有效性和准确性进行了验证. 相似文献
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文章针对高速数字电路信号完整性与电源完整性问题进行了分析,希望能够为高速数字产品的研究人员提供一定的参考。 相似文献
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基于传统AI-EBG结构,提出了一种小尺寸的增强型电磁带隙结构,实现了从0.5~9.4 GHz的宽频带-40 dB噪声抑制深度,且下截止频率减少到数百MHz,可有效抑制多层PCB板间地弹噪声。文中同时研究了EBG结构在高速电路应用时的信号完整性问题,使用差分信号方案可改善信号完整性。 相似文献
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Bipin Kumar Verma Shyam Akashe Sanjay Sharma 《International Journal of Electronics》2013,100(9):1486-1501
In this paper, various parameters are used to reduce leakage power, leakage current and noise margin of circuits to enhance their performance. A multiplier is proposed with low-leakage current and low ground bounce noise for the microprocessor, digital signal processors (DSP) and graphics engines. The ground bounce noise problem appears when a conventional power-gating circuit transits from sleep-to-active mode. This paper discusses a reduction in leakage current in the stacking power-gating technique by three modes – sleep, active and sleep-to-active. The simulation results are performed on a 4 × 4 carry-save multiplier for leakage current, active power, leakage power and ground bounce noise, and comparison made for different nanoscales. Ground bounce noise is limited to 90%. The leakage current of the circuit is decimated up to 80% and the active power is reduced to 31%. We performed simulations using cadence virtuoso 180 and 45 nm at room temperature at various supply voltages. 相似文献
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Resonance noise, or power/ground bounce noise, between the power and ground planes of high-speed circuit packages is one of the main concerns of signal integrity or power integrity issues. A novel time-domain approach is proposed to extract the equivalent circuit models of power/ground planes by time-domain reflection and time-domain transmission waveforms. The extracted model can accurately predict the resonance behaviour of power/ground planes over a wide frequency range. These models can be efficiently incorporated into the HSPICE simulator for the consideration of power/ground bouncing noise in high-speed circuits. 相似文献
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本文介绍了串扰和SSN的基本原理,并结合实例,利用Sigrity公司的软件对串扰和SSN的影响及其解决办法做了介绍。并重点介绍了通过减小布线层和参考层间的介质厚度来减小串扰,且通过添加去耦电容来使SSN对驱动电压和平面反弹的影响最小化。 相似文献
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As system clock rates race to 100 MHz and beyond, designers of printed-circuit boards and multichip modules must watch out for such high-speed effects as ground bounce, ringing, reflections, and crosstalk. The author describes how today's high-speed printed-circuit boards and multichip modules require integrated design systems that include signal integrity analysis tools 相似文献
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Heydari P. Pedram M. 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2003,11(2):180-193
This paper is concerned with the analysis and optimization of the ground bounce in digital CMOS circuits. First, an analytical method for calculating the ground bounce is presented. The proposed method relies on accurate models of the short-channel MOS device and the chip-package interface parasitics. Next the effect of ground bounce on the propagation delay and the optimum tapering factor of a multistage buffer is discussed and a mathematical relationship for total propagation delay in the presence of the ground bounce is obtained. Effect of an on-chip decoupling capacitor on the ground bounce waveform and circuit speed is analyzed next and a closed form expression for the peak value of the differential-mode component of the ground bounce in terms of the on-chip decoupling capacitor is provided. Finally, a design methodology for controlling the switching times of the output drivers to minimize the ground bounce is presented. 相似文献