Ni/Ti/Si形成硅化物的特性分析

随着MOSFET的特征尺寸进入20nm技术节点,源漏接触电阻成为源漏寄生电阻的主导部分,后栅工艺对硅化物的高温特性提出了更高的要求。分析了Ni/Ti/Si结构在不同温度退火下形成的硅化物的薄膜特性和方块电阻。分别采用J-V和C-V方法,提取硅化物与n-Si(100)接触的势垒高度。Ni/Ti/Si结构形成的镍硅化物在高温下具有良好的薄膜特性,并且可以得到低势垒的肖特基接触。随着退火温度的升高,势垒高度逐渐降低。研究了界面态的影响,在低于650℃的温度下退火,界面态密度随退火温度升高而逐渐增大,高于750℃后,界面电荷极性翻转。     

NiSi/Si界面的剖面透射电镜研究

采用不同硅化工艺制备了NiSi薄膜并用剖面透射电镜(XTEM)对样品的NiSi/Si界面进行了研究.在未掺杂和掺杂(包括As和B)的硅衬底上通过物理溅射淀积Ni薄膜,经快速热处理过程(RTP)完成硅化反应.X射线衍射和喇曼散射谱分析表明在各种样品中都形成了NiSi.还研究了硅衬底掺杂和退火过程对NiSi/Si界面的影响.研究表明:使用一步RTP形成NiSi的硅化工艺,在未掺杂和掺As的硅衬底上,NiSi/Si界面较粗糙;而使用两步RTP形成NiSi所对应的NiSi/Si界面要比一步RTP的平坦得多.高分辨率XTEM分析表明,在所有样品中都形成了沿衬底硅〈111〉方向的轴延-NiSi薄膜中的一些特定晶面与衬底硅中的(111)面对准生长.同时讨论了轴延中的晶面失配问题.     

不同退火温度对4H SiC 金半接触的影响

采用高真空电子束蒸发法制作了基于4H SiC外延材料的肖特基二极管,其中欧姆接触材料为Ti/Ni,肖特基接触材料为Ni。常温下,电流-电压(I-V)测试表明Ni/4H SiC肖特基二极管具有良好的整流特性,热电子发射是其主要输运机理。对比分析不同快速退火温度下器件的I-V特性,实验结果表明875 ℃退火温度下欧姆接触特性最好,400 ℃退火温度下器件肖特基接触I-V特性最好,理想因子为1.447,肖特基势垒高度为1.029 eV。     

大束流离子注入形成P-Si CoSi2/Si肖特基结的电学特性

采用金属离子注入法形式 Co Si2 /Si肖特基结并分析电学特性。分别测量不同退火条件下样品的 I-V、C-V特性 ,得出了各样品的势垒高度、串联电阻和理想因子。结果表明 ,采用快速热退火方法形成的结性能较好     

过渡层和界面电荷对金属硅化物/硅肖特基接触特性的影响

针对金属硅化物／硅接触存在过渡层，提出了分析这种结构的肖特基接触特性的模型；讨论了过渡层厚度、界面电行及有关参数的影响，分析了不同退火条件下PtSi／Si肖特基二极管的特性。     

Al/TiSi_2/Si系统与肖特基势垒二极管的热稳定性

本文用x射线衍射及I—V测量法研究了Al/TiSi_2/Si系统热稳定性及肖特基势垒特性。热稳定性的研究结果表明;系统在550℃以下退火是热稳定的;在更高的温度下退火,Al开始与TiSi_2起反应,形成了(Ti_7Al_5)Si-(12)三元化合物。在进行电特性研究时,发现系统在450℃退火时,Al已渗透TiSi_2而使肖特基势垒二极管失效。     

Al-Si接触的快速热退火

本文报道了用常规管式炉30秒钟快速热退火代替常规热合金化做Al-Si欧姆接触的简捷方法.通过俄歇电子能谱、扫描电子显微镜、接触电阻率和PN结反向电流的研究证实该法能有效地抑制导致浅结器件失效的Al-Si互扩散现象,从而达到保持良好结特性的欧姆接触.     

关于石墨烯上Ge/Au/Ni/Au欧姆接触的对比研究

Superior graphene-metal contacts can improve the performance of graphene devices. We report on an experimental demonstration of Ge/Au/Ni/Au-based ohmic contact on graphene. The transfer length method （TLM） is adopted to measure the resistivity of graphene-metal contacts. We designed a process flow, which can avoid residual photoresist at the interface of metal and graphene. Additionally, rapid thermal annealing （RTA） at different temperatures as a post-processing method is studied to improve graphene-metal contact. The results reveal that the contact resistivity of graphene and Ge/Au/Ni/Au can reach 10^-5 Ω· cm^2 after RTA, and that 350 ℃ is optimum annealing temperature for the contact of graphene-Ge/Au/Ni/Au. This paper provides guidance for fabrication and applications of graphene devices.     

InAs/AlSb异质结的Pd/Ti/Pt/Au合金化欧姆接触

为了得到较低的接触电阻, 研究了帽层未掺杂的InAs/AlSb异质结的Pd/Ti/Pt/Au合金化欧姆接触.利用传输线模型 (TLM) 测量了接触电阻Rc.在最佳的快速热退火条件为275℃和20s时, InAs/AlSb异质结的Pd/Ti/Pt/Au接触电阻值为0.128Ω·mm.TEM观察发现经过快速热退火后Pd已经扩散到半导体中有利于高质量欧姆接触的形成.研究表明经过Pd/Ti/Pt/Au合金化欧姆接触后Rc有明显减小, 适用于InAs/AlSb异质结的应用.     

二次退火对Al/Ti/n-GaN/Si欧姆接触的影响

采用热壁外延的方法在硅衬底上生长出n-GaN晶体,制成了Ti/Al双层电极的欧姆接触。通过对不同退火条件下的I-V特性曲线、X射线衍射及二次离子质谱分析,揭示了界面固相反应对该接触的影响,并提出了一种新的二次退火的方法。结果表明,经过二次退火后,Al、Ti、GaN发生了界面固相反应,其接触性能明显提高。     

A study of self-aligned formation of C54 Ti(Si1−xGex)2 to P+ and N+ Si0.7Ge0.3 alloys using rapid thermal annealing

In this paper, solid state reactions of titanium with boron and phosphorus doped Si_0.7Ge_0.3 alloys have been investigated for application in a self-aligned germanosilicide process. Wet chemical etching of the germanosilicide with respect to unreacted Ti in a solution of 1:1:5 NH₄OH:H₂O₂:H₂O has been investigated. Characterization was performed using four-point probe sheet resistance measurements, x-ray diffraction, cross-sectional transmission electron microscopy, Nomarski optical imaging, and scanning electron microscopy. The C54 Ti(Si_1−yGe_y)₂ phase was observed to form for reactions on both boron and phosphorus doped Si_0.7Ge_0.3 alloys. Grain structures of the C54 phases were found to be similar to grain structures of intrinsic alloy reactions with lateral grain dimensions on the order of 0.3 Μm. Resistivities of 22 ΜΩ-cm have been determined for the boron and phosphorus reactions. Although the germanosilicide phases were observed to etch slowly in 1:1:5 NH₄OH:H₂O₂:H₂O, which is conventionally used in the self-aligned titanium silicide process, the much higher etch rate of titanium nitride compounds and unreacted Ti provided for a self-aligned germanosilicide process. A first anneal in a nitrogen ambient was found to be necessary to eliminate lateral silicidation over surrounding oxide during self-aligned germanosilicide formation.     

Electrical properties of W/Si interfaces with embedded Ge/Si islands

In this work, we investigated electrical and morphological properties of W/p-type Si Schottky diodes with intentional inhomogeneities introduced by macroscopic Ge-islands embedded beneath the interface. The Si-cap layer thickness (or the island-distance to the interface) was progressively reduced by successive chemical etching cycles. Electrical characterizations were achieved through reverse current–voltage (I–V) at room temperature and forward I–V measurements as a function of the temperature. In parallel, Rutherford backscattering spectroscopy analyses were performed to follow the Si-cap/Ge islands chemical thinning down with increasing the number of etching cycles. In addition, the comparison of topographical and electrical properties of the etched silicon-cap layer was carried out by conductive atomic force microscopy analyses with a nanometer-scale resolution. Our results indicate that the areas on the top of islands exhibit lower resistance than those which covered the wetting layer. This lateral variation of resistance at the surface of the semiconductor may correspond to Schottky barrier height inhomogeneities observed on broad area I–V characteristics of Schottky contacts.     

Effect of annealing temperature on the electrical characteristics of Platinum/4H-SiC Schottky barrier diodes

Pt/4H-SiC Schottky barrier diodes have been fabricated to investigate the effect of annealing on the electrical characteristics of the fabricated devices. The parameters such as barrier height, ideality factor and donor concentration were deduced from the current–voltage (I–V) and the capacitance–voltage (C–V) measurements at room temperature. Diodes showed non-ideal behaviour like high value of ideality factor and lower value of barrier height. A barrier height of 1.82?eV was obtained from C–V measurements and it was 1.07?eV when obtained from the I–V measurements with ideality factor 1.71 for as-deposited diodes at room temperature. The diodes, therefore, were annealed in the temperature range from 25°C to 400°C to observe the effect of annealing temperature on these parameters. Schottky barrier height and ideality factors were found to be temperature-dependent. After rapid thermal annealing upto 400°C, a barrier height of 1.59?eV from C–V measurements and the value of 1.40?eV from I–V measurements with ideality factor 1.12 were obtained. Barrier heights deduced from C–V measurements were consistently larger than those obtained from I–V measurements. To come to terms with this discrepancy, we re-examined our results by including the effect of ideality factor in the expression of the barrier height. This inclusion of ideality factor results in reasonably good agreement between the values of barrier height deduced by the above two methods. We believe that these improvements in the electrical parameters result from the improvement in the quality of interfacial layer.     

Improvement of GaAs/AlGaAs quantum well laser diodes by rapid thermal annealing

Post-growth annealing is shown to improve the laser diode quality of GaAs/AlGaAs graded-index separate confinement heterostructure quantum well laser diode structures grown at a nonoptimal substrate temperature lower than 680°C by molecular beam epitaxy. Reduction by a factor of up to three in the threshold current was accompanied by a reduction in the interface trap density. The reduced threshold current is still higher than that of laser diodes grown at the optimal temperatures which are between 680 and 695°C. The improvement in laser diode performance is ascribed to the reduction of interface nonradiative recombination centers.     

快热退火对Co/n-Poly-SiGe肖特基结I-V-T特性的影响

采用射频磁控溅射法在n-Si(100)衬底上沉积Si1-xGex薄膜,俄歇电子谱(AES)测定Si1-xGex薄膜的Ge含量约为17%。对薄膜进行高温磷扩散掺杂,制得n-poly-Si0.83Ge0.17。在n-poly-Si0.83Ge0.17薄膜上溅射一层Co膜,制成Co/n-poly-Si0.83Ge0.17/n-Si肖特基结样品。在300～600℃范围内,对样品做快热退火。对不同退火温度下的样品做I-V-T测试。研究发现,测试温度升高,不同退火温度样品的肖特基势垒高度(SBH)的差别变小,500℃退火的样品,表观SBH最小。总体上,SBH随测试温度的升高而变大,理想因子的变化趋势则与之相反。基于SBH的不均匀分布建模,对实验结果给出了较为合理的解释。     

Thermally induced variation in barrier height and ideality factor of Ni/Au contacts to p-GaN

In this paper, we describe the change in barrier heights (ϕ_B) and ideality factors (n) of Ni/Au contacts to p-GaN determined from current-voltage measurements as a result of (a) rapid thermal annealing between 400–700°C under flowing nitrogen, and (b) testing at temperatures of 20–300°C. The lowest barrier height and ideality factor values were obtained from samples annealed at 500–600°C. These results provide supporting evidence that thermal processing helps to remove contaminants at the contact-GaN interface, thus decreasing effective barrier height and consequently, contact resistance.     

退火温度对Au/Ti/4H-SiC肖特基接触特性的影响

采用电子束蒸发法在4H-SiC表面制备了Ti/Au肖特基电极,研究了退火温度对Au/Ti/4H-SiC肖特基接触电学特性的影响.对比分析了不同退火温度下样品的电流密度-电压(J-V)和电容-电压(C-V)特性曲线,实验结果表明退火温度为500℃时Au/Ti/4H-SiC肖特基势垒高度最大,在.J-V测试和C-V测试中分别达到0.933 eV和1.447 eV,且获得理想因子最小值为1.053,反向泄漏电流密度也实现了最小值1.97×10-8 A/cm2,击穿电压达到最大值660 V.对退火温度为500℃的Au/Ti/4H-SiC样品进行J-V变温测试.测试结果表明,随着测试温度的升高,肖特基势垒高度不断升高而理想因子不断减小,说明肖特基接触界面仍然存在缺陷或者横向不均匀性,高温下的测试进一步证明肖特基接触界面还有很大的改善空间.     

The effect of pulsed laser annealing on the nickel silicide formation

The pulsed laser annealing (PLA) is used to assist nickel silicide transformation for Schottky barrier height reduction and tensile strain enhancement and the effect of different laser power are investigated. In this report, a two-step annealing process which combine the conventional rapid thermal annealing with pulsed laser annealing is proposed to achieve a smooth silicon-rich NiSi_x interfacial layer on (1 0 0) silicon. With optimized laser energy, a 0.2 eV Schottky barrier height (SBH) modulation is observed from Schottky diode electrical characterization. Furthermore, PLA provides sufficient effective temperature during silicidation which also lead to increased tensile stress of silicide film than the two-step RTA silicide is also investigated. The SBH modulation and tensile stress enhancement benefits of PLA silicidation are considered as an alternative to the conventional rapid thermal annealing for ultra-scaled devices performance enhancement.