用于12bit250MS/s流水线ADC的运算放大器设计

设计了一种应用于12 bit 250 MS/s采样频率的流水线模数转换器(ADC)的运算放大器电路.该电路采用全差分两级结构以达到足够的增益和信号摆幅;采用一种改进的频率米勒补偿方法实现次极点的“外推”,减小了第二级支路所需的电流,并达到了更大的单位增益带宽.该电路运用于一种12 bit 250 MS/s流水线ADC的各级余量增益放大器(MDAC),并采用0.18 μm 1P5M 1.8 V CMOS工艺实现.测试结果表明,该ADC电路在全速采样条件下对于20 MHz的输入信号得到的信噪比(SNR)为69.92 dB,无杂散动态范围(SFDR)为81.17 dB,整个ADC电路的功耗为320 mW.     

一种12 bit 200 MS/s 低功耗 SAR-TDC ADC北大核心

为了满足低电压条件下高速高精度采样需求，设计了一种电压-时域两级混合结构流水线模数转换器(ADC)。该流水线ADC的第一级逐次逼近型(SAR) ADC将电压转换为8 bit数字，残差电压变换为时域延时信息后，第二级4.5 bit时间数字转换器(TDC)将延时转换，最终校准输出，实现12 bit精度转换。通过采用多电压供电、改进残差电压转移和放大器结构，以及优化时间判决器，提升了ADC的动态性能和采样速度，降低了采样功耗。该ADC基于40 nm CMOS工艺设计和仿真。采样率为200 MS/s时，功耗为9.5 mW,动态指标SNDR、SFDR分别达到68.4 dB、83.6 dB,优值为22 pJ·conv-1·step-1,能够满足低功耗高速采样的应用需求。     

一种10位250 MS/s电荷域流水线ADC

提出了一种高速、低功耗、小面积的10位 250 MS/s 模数转换器(ADC)。该ADC采用电荷域流水线结构,消除了高增益带宽积的跨导运算放大器,降低了ADC功耗。采用流水线逐级电荷缩减技术,降低了后级电路的电荷范围,减小了芯片面积。测试结果表明,在250 MS/s采样速率、9.9 MHz输入正弦信号的条件下,该ADC的无杂散动态范围(SFDR)为64.4 dB,信噪失真比(SNDR)为57.7 dB,功耗为45 mW。     

一种14位100 MS/s的流水线模数转换器

设计了一种14位100 MS/s的流水线模数转换器(ADC)。采样保持电路与第1级2.5位乘法数模转换器(MDAC1)共享运放,降低了功耗。提出了一种改进的跨导可变双输入开关运放,以满足采样保持和MDAC1对运放的不同要求,并消除记忆效应和级间串扰。ADC后级采用5级1.5位运放共享结构。基于0.18 μm CMOS工艺,ADC核心面积为1.4 mm²。后仿真结果表明,在1.8 V电源电压下,当采样速率为100 MS/s、输入信号频率为46 MHz时,ADC的信噪比(SNR)为82.6 dB,信噪失真比(SNDR)为78.7 dB,无杂散动态范围(SFDR)为84.1 dB,总谐波失真(THD)为-81.0 dB,有效位数(ENOB)达12.78位。ADC整体功耗为116 mW。     

用于视频图像传感器的12 bit 60 MS/s流水线模数转换器

介绍了一种12 bit 60 MS/s流水线模数转换器(ADC),该转换器使用采样保持电路,将连续变化的模拟信号通过一定时间间隔的采样,以实现信号的准确量化,利用增益自举运放提高信号建立的线性度;采用每级1.5 bit精确度的流水线结构实现冗余编码,降低比较器失调电压对精确度的影响,同时提出一种新型的消除静态功耗的预放大比较器结构。该流水线ADC芯片采用华力55 nm 互补金属氧化物(CMOS)工艺进行电路和版图设计。对后仿真结果进行快速傅里叶变换(FFT)分析得到：动态参数无杂散动态范围(SFDR)为86.18 dB,信噪比(SNR)为72.91 dB,信纳比(SNDR)为72.8 dB,有效位数(ENOB)为11.72 bit。     

14位50MS/s100mW0.18μm CMOS流水线ADC

实现了一种14位40MS/s CMOS流水线A/D转换器(ADC)。在1.8V电源电压下,该ADC功耗仅为100mW。基于无采样/保持放大器前端电路和双转换MDAC技术,实现了低功耗设计,其中,无采样/保持放大器前端电路能降低约50%的功耗,双转换MDAC能降低约10%的功耗。该ADC采用0.18μm CMOS工艺制作,芯片尺寸为2.5mm×1.1mm。在40MS/s采样速率、10MHz模拟输入信号下进行测试,电源电压为1.8V,DNL在±0.8LSB以内,INL在±3.5LSB以内,SNR为73.5dB,SINAD为73.3dB,SFDR为89.5dBc,ENOB为11.9位,THD为-90.9dBc。该ADC能够有效降低SOC系统、无线通信系统及数字化雷达的功耗。     

一种10位50MS/s两级逐次逼近流水线混合型A/D转换器

本文在0.18μm CMOS工艺下,实现了一款10位50MS/s两级逐次逼近流水线混合型模数转换器（pipeline SAR ADC）。其由基于逐次逼近的增益模数单元和逐次逼近ADC组成,并采用1位冗余位放宽了子模数转换器的比较误差。通过采用逐次逼近结构,增益减半MDAC技术,动态比较器及动态逐次逼近控制逻辑,降低了模数转换器的功耗和面积。流片测试结果表明,在1.8V电源电压,50MS/s采样速率下,信噪失真比(SFDR)和功耗分别为56.04dB和5mV。     

12位200MS/s交织A/D转换器设计

介绍了一个面向3G/4G LTE通信及雷达等应用的12位200 MS/s的高速低功耗A/D转换器(ADC).采用交织运放共享技术,可节省功耗,同时减小不同通道之间的增益失配、失调失配和带宽失配,提高ADC的性能.为了提高ADC的高频性能并避免时钟采样偏差带来的两路通道失配问题,采用一个工作在200 MS/s采样频率的统一的采样保持电路.芯片采用HJTC0.18 μm 1P6M CMOS的工艺制造,核心电路面积为1.6×4 (mm2),电源电压2.0V.流片测试结果表明,在4.9 MHz的输入频率下,无杂散动态范围(SFDR)为83.1 dB,信号噪声失真比(SNDR)为59.6 dB,模拟核心电流为120mA,FOM1和FOM2值仅为0.08 pJ/step和1.25 pJ/step.     

8位CMOS双通道流水线ADC仿真设计

设计了一种8位1.2V,1GS/s双通道流水线A/D转换器(ADC)。所设计ADC对1.5位增益D/A转换电路(MDAC)中的流水线双通道结构进行改进,其中设置有双通道流水线时分复用运算放大器和双/单通道快闪式ADC,以简化结构并提高速度;在系统前置采样/保持器中加设由单一时间信号驱动的开关线性化控制(SLC)电路,以解决两条通道之间的采样歪扭和时序失调问题。用90nm标准CMOS工艺对所设计的流水线ADC进行仿真试验,结果表明,室温下所设计ADC的信噪比SNR为32.7dB,无杂散动态范围SFDR为42.3dB,它的分辨率、功耗PD和采样速率SR分别为8位、23mW和1GS/s,从而满足了高速、高精度和低功耗的应用需要。     

一种低功耗14位10MS/s流水线A/D转换器

基于0.6μm BiCMOS工艺,设计了一个低功耗14位10MS/s流水线A/D转换器.采用了去除前端采样保持电路、共享相邻级间的运放、逐级递减和设计高性能低功耗运算放大器等一系列低功耗技术来降低ADC的功耗.为了减小前端采样保持电路去除后引入的孔径误差,采用一种简单的RC时间常数匹配方法.仿真结果表明,当采样频率为10MHz,输入信号为102.5kHz,电源电压为5V时,ADC的信噪失真比(SNDR)、无杂散谐波范围(SFDR)、有效位数(ENOB)和功耗分别为80.17dB、87.94dB、13.02位和55mW.     

Performance improvement in tensile-strained In/sub 0.5/Al/sub 0.5/As/In/sub x/Ga/sub 1-x/As/In/sub 0.5/Al/sub 0.5/As metamorphic HEMT

This paper proposes a In/sub 0.5/Al/sub 0.5/As/In/sub x/Ga/sub 1-x/As/In/sub 0.5/Al/sub 0.5/As (x=0.3-0.5-0.3) metamorphic high-electron mobility transistor with tensile-strained channel. The tensile-strained channel structure exhibits significant improvements in dc and RF characteristics, including extrinsic transconductance, current driving capability, thermal stability, unity-gain cutoff frequency, maximum oscillation frequency, output power, power gain, and power added efficiency.     

Morphological and electrical characterization of SixCryCzBv thin films

Si_xCr_yC_zB_v thin films with several compositions have been studied for integration of high precision resistors in 0.8 μm BICMOS technology. These resistors, integrated in the back-end of line, have the advantage to provide high level of integration and attractive electrical behavior in temperature, for analog devices. The film morphology and the structure have been investigated through transmission electron microscopy analysis and have been then related to the electrical properties on the base of the percolation theory. According to this theory, and in agreement with experimental results, negative thermal coefficient of resistance (TCR) has been obtained for samples with low Cr content, corresponding to a crystalline volume fraction below the percolation threshold.Samples with higher Cr content exhibit, instead, a variation of the TCR as a function of film thickness: negative TCR values are obtained for thickness lower than 5 nm, corresponding to a crystalline volume fraction below the percolation threshold; positive TCR are obtained for larger thickness, indicating the establishment of a continuous conductive path between the Cr rich grains. This property seems to be determinant in order to assure the possibility to obtain thin film resistors almost independent on the temperature.     

Comparison between Pt/TiO2/Pt and Pt/TaOX/TaOY/Pt based bipolar resistive switching devices

Nonvolatile memories have emerged in recent years and have become a leading candidate towards replacing dynamic and static random-access memory devices. In this article, the performances of TiO₂ and TaO₂ nonvolatile memristive devices were compared and the factors that make TaO₂ memristive devices better than TiO₂ memristive devices were studied. TaO₂ memristive devices have shown better endurance performances (10⁸ times more switching cycles) and faster switching speed (5 times) than TiO₂ memristive devices. Electroforming of TaO₂ memristive devices requires~4.5 times less energy than TiO₂ memristive devices of a similar size. The retention period of TaO₂ memristive devices is expected to exceed 10 years with sufficient experimental evidence. In addition to comparing device performances, this article also explains the differences in physical device structure, switching mechanism, and resistance switching performances of TiO₂ and TaO₂ memristive devices. This article summarizes the reasons that give TaO₂ memristive devices the advantage over TiO₂ memristive devices, in terms of electroformation, switching speed, and endurance.     

The C-V-f and G/ω-V-f characteristics of Al/SiO2/p-Si (MIS) structures

The frequency dependence of capacitance-voltage (C-V) and conductance-voltage (G/ω-V) characteristics of the Al/SiO₂/p-Si metal-insulator-semiconductor (MIS) structures has been investigated taking into account the effect of the series resistance (R_s) and interface states (N_ss) at room temperature. The C-V and G/ω-V measurements have been carried out in the frequency range of 1 kHz to 1 MHz. The frequency dispersion in capacitance and conductance can be interpreted only in terms of interface states and series resistance. The N_ss can follow the ac signal and yield an excess capacitance especially at low frequencies. In low frequencies, the values of measured C and G/ω decrease in depletion and accumulation regions with increasing frequencies due to a continuous density distribution of interface states. The C-V plots exhibit anomalous peaks due to the N_ss and R_s effect. It has been experimentally determined that the peak positions in the C-V plot shift towards lower voltages and the peak value of the capacitance decreases with increasing frequency. The effect of series resistance on the capacitance is found appreciable at higher frequencies due to the interface state capacitance decreasing with increasing frequency. In addition, the high-frequency capacitance (C_m) and conductance (G_m/ω) values measured under both reverse and forward bias were corrected for the effect of series resistance to obtain the real diode capacitance. Experimental results show that the locations of N_ss and R_s have a significant effect on electrical characteristics of MIS structures.     

Very low-noise Al/sub 0.3/Ga/sub 0.7/As/Ga/sub 0.65/In/sub 0.35/As/GaAs single quantum-well pseudomorphic HEMTs

AlGaAs/GaInAs/GaAs pseudomorphic HEMTs with an InAs mole fraction as high as 35% in the channel has been successfully fabricated. The device exhibits a maximum extrinsic transconductance of 700 mS/mm. At 18 GHz, a minimum noise figure of 0.55 dB with 15.0 dB associated gain was measured. At 60 GHz, a minimum noise figure as low as 1.6 dB with 7.6 dB associated gain was also obtained. This is the best noise performance yet reported for GaAs-based HEMTs.<>     

A 12 /spl times/ 12 In/sub 0.53/Ga/sub 0.47/As-In/sub 0.52/Al/sub 0.48/As avalanche photodiode array

We report a 12 /spl times/ 12 In/sub 0.53/Ga/sub 0.47/As-In/sub 0.52/Al/sub 0.48/As avalanche photodiode (APD) array. The mean breakdown voltage of the APD was 57.9 V and the standard deviation was less than 0.1 V. The mean dark current was /spl sim/2 and /spl sim/300 nA, and the standard deviation was /spl sim/0.19 and /spl sim/60 nA at unity gain (V/sub bias/ = 13.5 V) and at 90% of the breakdown voltage, respectively. External quantum efficiency was above 40% in the wavelength range from 1.0 to 1.6 /spl mu/m. It was /spl sim/57% and /spl sim/45% at 1.3 and 1.55 /spl mu/m, respectively. A bandwidth of 13 GHz was achieved at low gain.     

Al/sub 0.3/Ga/sub 0.7/As/In/sub x/Ga/sub 1-x/As (0/spl les/x/spl les/0.25) doped-channel field-effect transistors (DCFET's)

The properties of both lattice-matched and strained doped-channel field-effect transistors (DCFET's) have been investigated in AlGaAs/In/sub x/Ga/sub 1-x/As (0/spl les/x/spl les/0.25) heterostructures with various indium mole fractions. Through electrical characterization of grown layers in conjunction with the dc and microwave device characteristics, we observed that the introduction of a 150-/spl Aring/ thick strained In/sub 0.15/Ga/sub 0.85/As channel can enhance device performance, compared to the lattice-matched one. However, a degradation of device performance was observed for larger indium mole fractions, up to x=0.25, which is associated with strain relaxation in this highly strained channel. DCFET's also preserved a more reliable performance after biased-stress testings.<>     

Lanthanum diffusion in the TiN/LaOx/HfSiO/SiO2/Si stack

Band edge Complementary Metal Oxide Semiconductor (CMOS) devices are obtained by insertion of a thin LaO_x layer between the high-k (HfSiO) and metal gate (TiN). High temperature post deposition anneal induces Lanthanum diffusion across the HfSiO towards the SiO₂ interfacial layer, as shown by Time of Flight Secondary Ions Mass Spectroscopy (ToF-SIMS) and Atom Probe Tomography (APT). Fourier Transform Infrared Spectroscopy in Attenuated Total Reflexion mode (ATR-FTIR) shows the formation of La-O-Si bonds at the high-k/SiO₂ interface. Soft X-ray Photoelectron Spectroscopy (S-XPS) is performed after partial removal of the TiN gate. Results confirm La diffusion and changes in the La chemical environment.     

Dielectric confinement on exciton binding energy and nonlinear optical properties in a strained Zn1-xinMgxinSe/Zn1-xoutMgxoutSe quantum well

The band offsets for a Zn1-xinMgxin Se/Zn1-xoutMgxout Se quantum well heterostructure are determined using the model solid theory.The heavy hole exciton binding energies are investigated with various M...