An Ultra-Low Power Area Efficient Voltage Controlled Oscillator Based on Tunable Active Inductor for Wireless Applications.

This paper presents a tunable active inductor based ultra-low power, low area voltage-controlled oscillator (VCO) in 90 nm CMOS process. In the designed VCO, the modified topology of the active inductor is employed along with tuning capability. The layoutbased simulation has been performed deeming parasitic resistances and capacitances. The designed VCO yields an oscillation frequency ranging from 1.38 GHz to 3.16 GHz with a tuning range of 78.41%, where the tuning voltage is driven from 0.4 V to −0.2 V. The power dissipation varies from 0.062 mW to 0.177 mW, and the VCO provides a differential output power of 8.34 dBm to 3.94 dBm. The phase noise varies from −71 dBc/Hz to −65.4 dBc/Hz, and the Figure of Merit (FoM) has a value of −143.09 dBc/Hz @ 2.79 GHz frequency. The process corner analysis, temperature swept analysis, and Monte Carlo analysis of the proposed VCO had been carried out for the evaluation of its compatibility for diversified environments. Furthermore, the exclusion of the MOS varactor has condensed total silicon area consumption (10.3 μm × 8.5 μm). Finally, the designed VCO's performance parameters have been compared with mentioned designs where it is demonstrated that the designed VCO outdoes the others in most cases along with outstanding outcomes of low power and low silicon area consumption.     

Poststress RF‐drifts of dual‐band LC VCO in 0.18‐μm CMOS technology

This article studies the RF‐property of a dual‐band voltage‐controlled oscillator (VCO). The designed circuit consists of a dual‐resonance LC resonator and a Colpitts negative resistance cell. The dual‐resonance LC resonator comprises a series‐tuned LC resonator and a parallel resonant resonator. The proposed VCO has been implemented with the TSMC 0.18 μm 1P6M CMOS technology. The VCO can generate differential signals in the frequency range of 3.0–3.37 GHz and 6.95–7.40 GHz with core power consumption of 10.08 and 10.24 mW at the dc drain‐source bias V_DD of 1.4 V, respectively. The die area of the dual‐band VCO is 0.485 × 0.800 mm². The circuit was operated at V_DD = 3 V for 8 h and significant drift in RF parameters was found. © 2013 Wiley Periodicals, Inc. Int J RF and Microwave CAE 24:243–248, 2014.     

Low power quadrature voltage controlled oscillator

In this article, a low voltage low power quadrature voltage controlled oscillator (QVCO) coupled by four P&N transistors is presented. First, a novel negative resistance inductance capacitor (LC) oscillator is described, the N‐metal oxide semiconductor (NMOS) and P‐metal oxide semiconductor (PMOS) transistors are in series with the LC tank in the direct‐current (DC) path, and they generate the required negative resistance to compensate the energy loss of the LC tank and maintain the steady oscillation of the oscillator. Then, based on two identical LC oscillators, four P&N transistors are used as coupling terminals to generate quadrature outputs. The proposed QVCO is designed and simulated with GlobalFoundries' 0.18 μm CMOS RF process. The Cadence IC design tools postlayout simulation results demonstrate that the oscillation frequency of the QVCO can be tuned from 2.0 to 5.6 GHz by adjusting the bias voltage, and the phase noise of the voltage controlled oscillator is ?114 dBc/Hz at 1 MHz offset. Moreover, the proposed QVCO consumes only 2.31 mW from a 1.2 V supply voltage and it occupies a compact area of 0.45 mm² including the bond pads.     

Chip-level integration of RF MEMS on-chip inductors using UV-LIGA technique

This paper presents a chip-level integration of radio-frequency (RF) microelectromechanical systems (MEMS) air-suspended circular spiral on-chip inductors onto MOSIS RF circuit chips of LNA and VCO using a multi-layer UV-LIGA technique including SU-8 UV lithography and copper electroplating. A high frequency simulation package, HFSS, was used to determine the layout of MEMS on-chip inductors with inductance values close to the target inductance values required for the RF circuit chips within the range of 10%. All MEMS on-chip inductors were successfully fabricated using a contrast enhancement method for 50 μm air suspension without any physical deformations. High frequency measurement and modeling of the integrated inductors revealed relatively high quality factors over 10 and self-resonant frequencies more than 15 GHz for a 1.44 nH source inductor and a 3.14 nH drain inductor on low resistivity silicon substrates (0.014 Ω cm). The post-IC integration of RF MEMS on-chip inductors onto RF circuit chips at a chip scale using a multi-layer UV-LIGA technique along with high frequency measurement and modeling demonstrated in this work will open up new avenues with the wider integration feasibility of MEMS on-chip inductors in RF applications for cost-effective prototype applications in small laboratories and businesses.     

A multiband carrier generation architecture for UHF, 2.4 GHz,and 5 GHz ISM applications

Novel multiband carrier generation architecture is proposed that can be applicable for RFID reader, WLAN 802.11a‐b‐g, and ZigBee sensor network, and implemented with 0.18 μm CMOS technology. In the proposed architecture, a quadrature voltage controlled oscillator (QVCO) is implemented by coupling two differential cross‐coupled LC VCOs to generate in‐phase (I) and quadrature (Q) signals operating at one‐thirds of the 5 GHz frequency range. As well, the differential second harmonic signal of the VCO core frequency is generated by mixers, and then converted to I/Q signals via a single‐stage tunable polyphase filter. By single sideband mixing of the I/Q signals of the QVCO and the polyphase filter, a cleaner carrier signal can be generated in the frequency band of 5 GHz. By including extra frequency dividers, the architecture can also be reconfigured to generate UHF band and 2.4 GHz band. The proposed architecture draws about 32 mA including the QVCO core current consumption of 2.8 mA from 1.8 V supply. The measured tuning frequency of the QVCO core ranges from 1.57 to 1.84 GHz. The measured phase noise is ?104.5 dBc/Hz at 1 MHz offset from 4.84 GHz. The chip layout occupies an area of 1.44 × 1.4 mm² on Si substrate, including the DC and RF pads. © 2008 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2009.     

Realization of a VCO for WLAN applications using 0.35 μm‐siGe BICMOS technology

In this article, a 4.5–5.8 GHz, ?G_m LC voltage controlled oscillator (VCO) for IEEE 802.11a standard is presented. The circuit is designed with Austria MicroSystems 0.35 μm SiGe BiCMOS process that includes high‐speed SiGe heterojunction bipolar transistors (HBTs). According to measurement results, phase noise is ?102.3 dBc/Hz at 1 MHz offset from 5 GHz carrier frequency. A linear, 1300 MHz tuning range is obtained utilizing accumulation‐mode varactors. Phase noise is relatively low because of the advantage of differential tuning concept. Output power of the fundamental frequency changes between ?1.6 and 0.9 dBm depending on the tuning voltage. Average second and third harmonic levels are ?25 and ?41 dBm, respectively. The circuit draws 14 mA DC current from 3.3 V supply including buffer circuits leading to a total power dissipation of 46.2 mW. The prototype VCO occupies an area of 0.6 mm² on Si substrate, including DC and RF pads. © 2008 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2008.     

适用于频率综合器的宽带低相噪VCO设计

针对频率综合器在宽调谐范围下相位噪声变差的问题,设计了一款适用于频率综合器的宽调谐范围低相位噪声的压控振荡器;采用180nm BiCMOS工艺,运用可变电容阵列和开关电容阵列实现宽调谐范围;通过加入降噪模块,滤除压控振荡器产生的二次谐波和三次谐波,增大输出振幅,降低相位噪声;并在压控振荡器输出端加入输出缓冲器,降低频率综合器其他器件对压控振荡器的影响;通过Cadence软件对压控振荡器进行仿真,仿真结果表明：调谐电压为0.3~3V,压控振荡器的输出频率范围为2.3~3.5GHz;当压控振荡器的中心频率为3.31GHz时,在偏离中心频率10kHz、100kHz和1MHz处的相位噪声分别为-93.21dBc/Hz,-117.03dBc/Hz,-137.41dBc/Hz,功耗7.66mW;在较宽的频率范围内,取得良好的相位噪声抑制,提高压控振荡器的噪声性能,满足宽带低相噪频率综合器的应用需求。     

Design and simulation of a thermally actuated MEMS switch for microwave circuits

The design, modeling, and optimization of a novel, thermally actuated CMOS‐MEMS switch are presented in this article. This series capacitive MEMS switch solves the substrate loss and down‐state capacitance degradation problems commonly plaguing MEMS switches. The switch uses finger structure for capacitive coupling. The vertical bending characteristic of bimorph cantilever beams under different temperatures is utilized to turn the switch on and off. A set of electrical, mechanical, and thermal models is established, and cross‐domain electro‐thermo‐mechanical simulations are performed to optimize the design parameters of the switch. The fabrication of the switch is completely CMOS‐process compatible. The design is fabricated using the AMI 0.6 μm CMOS process and a maskless reactive‐ion etching process. The measured results show the insertion loss and isolation are 1.67 and 33 dB, respectively, at 5.4 GHz, and 0.36 and 23 dB at 10 GHz. The actuation voltage is 25 V and the power consumption is 480 mW. This switch has a vast number of applications in the RF/microwave field, such as configurable voltage control oscillators, filters, and configurable matching networks. © 2009 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2009.     

Design of a 4.2–5.4 GHz differential LC VCO using 0.35 μm SiGe BiCMOS technology for IEEE 802.11a applications

In this paper, a 4.2–5.4 GHz, ?Gm LC voltage controlled oscillator (VCO) for IEEE 802.11a standard is presented. The circuit is designed with AMS 0.35 μm SiGe BiCMOS process that includes high‐speed SiGe Heterojunction Bipolar Transistors (HBTs). According to post‐layout simulation results, phase noise is ?110.7 dBc/Hz at 1 MHz offset from 5.4 GHz carrier frequency and ?113.4 dBc/Hz from 4.2 GHz carrier frequency. A linear, 1200 MHz tuning range is obtained from the simulations, utilizing accumulation‐mode varactors. Phase noise was also found to be relatively low because of taking advantage of differential tuning concept. Output power of the fundamental frequency changes between 4.8 dBm and 5.5 dBm depending on the tuning voltage. Based on the simulation results, the circuit draws 2 mA without buffers and 14.5 mA from 2.5 V supply including buffer circuits leading to a total power dissipation of 36.25 mW. The circuit layout occupies an area of 0.6 mm² on Si substrate, including DC and RF pads. © 2007 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2007.     

C波段宽带频率源及其测试系统设计

为了设计一个C波段宽带频率源,采用了基于锁相环配合宽带VCO的方法。该方法使用的PLL芯片为HMC702,VCO为HMC586,控制端采用FPGA写寄存器。频率源测试时采用PC串口转SPI协议的方法。实验结果显示,最差相位噪声为-88.2 dBc/Hz@10 kHz,杂散抑制度为-62.7 dBc,从4 GHz到6 GHz的变频时间为20.6μs。     

High-performance inductors using capillary based fluidic self-assembly

In this paper, a batch microfabrication process is presented for creating high aspect ratio, micron-sized helical and toroidal inductors with Q greater than or equal to 50 at multi-GHz frequencies. With a maximum processing temperature of only 220/spl deg/C, the inductors can be fabricated on top of standard CMOS wafers. This process can also be used to create "inductor chiplets", which are polymer-encapsulated inductors with the same form factor as an EIA (Electronics Industries Association) standard 0201 surface mount device. The chiplets can be assembled onto CMOS wafers using a fluidic microassembly technique. This technique allows for multiple electrical interconnects to the inductor chiplets. The 40-/spl mu/m gap between the substrate and assembled inductor increases the Q by a factor of /spl sim/3 compared to as-fabricated inductors. Assembled and as-fabricated inductors have been characterized on similar substrates and have maximum Q values of 50 and 15 with resonant frequencies of 10 GHz and 9 GHz, respectively. Performance of the assembled inductors is nearly comparable to that of inductors as fabricated and tested on quartz substrates.     

用负阻法实现S波段低相噪压控振荡器设计

采用分布式微带电路结构和负阻振荡法设计了频率范围为2．4—2．8GHz的压控振荡器（VCO）,根据ADS软件进行建模并仿真,确定了VCO的电路参数,同时对振荡器的相位噪声和输出功率等关键参数进行了仿真优化。最终通过对实际制作出的VCO测量,验证了该模型的准确性,频段内的相位噪声达到-90dBc,Hz@10KHz,输出功...     

一个低抖动比1GHz环形VCO的设计与实现

通过对Weigandt模型进行噪声分析,采用一种改进的差分延迟单元结构,成功设计了一个稳定输出1 GHz的环形压控振荡器。同时,采用SMIC 0.18μm标准CMOS工艺流片,在输出端增加钳位管和正反馈管使输出电位能够快速转变为给定值,已达到高速振荡频率和较低噪声比的效果。流片后测试结果表明,当控制电压为30μV～800 mV时,输出频率可达740 MHz～1.3 GHz,并与输入电压之间呈现良好的线性性;在中心振荡频率为1 GHz时,噪声电压与信号电压的比满足设计要求。     

A compact dual‐band zeroth‐order resonator antenna loaded with meander line inductor

A novel zeroth‐order resonator (ZOR) meta‐material (MTM) antenna with dual‐band is suggested using compound right/left handed transmission line as MTM. In this article, suggested antenna consists of patch through series gap, two meander line inductors, and two circular stubs. The MTM antenna is compact in size which shows dual‐band properties with first band centered at 2.47 GHz (2.05‐2.89 GHz) and second band is centered at 5.9 GHz (3.70‐8.10 GHz) with impedance bandwidth of (S₁₁ < ? 10 dB) 34.69% and 72.45%, respectively. At ZOR mode (2.35 GHz), the suggested antenna has overall dimension of 0.197λ_o × 0.07λ_o × 0.011λ_o with gain of 1.65 dB for ZOR band and 3.35 dB for first positive order resonator band which covers the applications like Bluetooth (2.4 GHZ), TV/Radio/Data (3.700‐6.425 GHz), WLAN (5‐5.16 GHz), C band frequencies (5.15‐5.35, 5.47‐5.725, or 5.725‐5.875 GHz) and satellite communication (7.25‐7.9 GHz). The radiation patterns of suggested structure are steady during the operating band for which sample antenna has been fabricated and confirmed experimentally. It exhibits novel omnidirectional radiation characteristics in phi = 0° plane with lower cross‐polarization values.     

锁相环中鉴相器结构特点及其与压控振荡器的关键使用技术

以锁相环(PLL)中重要的IC为例,介绍了片内鉴相器不同类型的结构特点,分析了常用鉴相器(PC)的"死区"以及压控振荡器(VCO)与鉴相器之间的相互干扰原因,并从实际出发提出了相应的改进措施。最后,还提出了有关扩展压控振荡器的频率范围和改善其控制电压的关键技术。     

Modeling, optimization and performance of high-Q MEMS solenoid inductors

Modeling, optimization and performance of on-chip solenoid inductors is presented. MATLAB is used to get the π-equivalent circuit model parameters. The effects of the geometrical parameters on the inductance and quality factor (Q-factor) are different. Normally, the performance of the inductors can be improved by increasing the coil turns in a way and increasing the length of the conductor, but both of them will occupy more chip area, which is not good for the minimization of the on-chip system. It is desirable to improve the performance of inductor by increasing the height of the via. Of the three types of fabricated inductors covering the same area, the inductors with the height of via 15, 30 and 45 μm have high performance. The self-resonant frequency is up to 10 GHz. The inductances and Q-factors at peak-Q frequency (about 5.8 GHz) are 1.16, 1.35, 1.78 nH and 21.9, 27, 38, respectively.     

A 5 GHz LC-VCO frequency synthesizer for unlicensed band of WiMAX

This paper presents a low power and low phase noise CMOS integer-N frequency synthesizer based on the charge-pump Phase Locked Loop (PLL) topology. The frequency synthesizer can be used for IEEE 802.16 unlicensed band of WiMAX (World Interoperability for Microwave Access). The operation frequency of the proposed design is ranged from 5.13 to 5.22 GHz. The proposed Voltage-Controlled Oscillator (VCO) achieves low power consumption and low phase noise. The high speed divider is implemented by an optimal extended true single phase clock (E-TSPC) prescaler. It can achieve higher operating frequency and lower power consumption. A new frequency divider is also proposed to eliminate the hardware overhead of the S counter in the conventional programmable divider. The proposed frequency synthesizer consists of a phase-frequency detector (PFD), a charge pump, a low-pass loop filter, a VCO, and a frequency divider. The simulated phase noise of the proposed VCO is −121.6 dBc/Hz at 1 MHz offset from the carrier frequency. The proposed frequency synthesizer consumes 13.1 mW. The chip with an area of 1.048 × 1.076 mm² is fabricated in a TSMC 0.18 μm CMOS 1P6M technology process.     

基于噪声消除技术的超宽带CMOS低噪声放大器设计

为满足3.5 GHz单载波超宽带无线接收机的射频需求,设计了一种工作在3～4 GHz的超宽带低噪声放大器。电路采用差分输入的CMOS共栅级结构,利用MOS管跨导实现宽带输入匹配,利用电容交叉耦合结构和噪声消除技术降低噪声系数,同时提高电压增益。分析了该电路的设计原理和噪声系数,并在基于SMIC 0.18μm CMOS射频工艺进行了设计仿真。仿真结果表明:在3～4GHz频段内,S11和S22均小于-10 dB,S21大于14dB,带内起伏小于0.5dB,噪声系数小于3dB;1.8V电源电压下,静态功耗7.8mW。满足超宽带无线接收机技术指标。     

RF MEMS压控振荡器的研制及相位噪声特性研究

利用RF MEMS可变电容作为频率调节元件,制备了中心频率为2 GHz的MEMS VCO器件.RF MEMS可变电容采用凹型结构,其控制极板与电容极板分离,并采用表面微机械工艺制造,在2 GHz时的Q值最高约为38.462.MEMS VCO的测试结果表明,偏离2.007 GHz的载波频率100kHz处的单边带相位噪声为-107 dBc/Hz,此相位噪声性能优于他们与90年代末国外同频率器件.并与采用GaAs超突变结变容二极管的VCO器件进行了比较,说明由于集成了RF MEMS可变电容,使得在RF MEMS可变电容的机械谐振频率近端时,MEMS VCO的相位噪声特性发生了改变.     

Design of high selectivity tri‐band bandpass filter with wide upper stopband

This article presents a dual‐plane structure high selectivity tri‐band bandpass filter (BPF) which consists of a pair of T‐shaped microstrip feed lines with capacitive source‐load coupling as well as spur lines embedded, and three resonators, i.e., a dual‐mode stub‐loaded stepped impedance resonator and two nested dual‐mode defected ground structure resonators. Using the intrinsic characteristics of the resonators and feed lines, nine transmission zeros near the passband edges and in the stopband can be generated to achieve high selectivity. An experimental tri‐band BPF located at 2.4/5.7 GHz [wireless local area networks (WLAN) application] and 3.5 GHz [worldwide interoperability for microwave access (WiMAX) application] has been simulated and fabricated. Good agreement between the simulated and measured results validates the design approach. © 2012 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2013.