A New Inductor Series-Peaking Technique for Bandwidth Enhancement of CMOS Current-Mode Circuits

This paper introduces a new inductor series-peaking technique for bandwidth enhancement of low-voltage CMOS current-mode circuits. The peaking inductor is in series with the capacitor constituting the dominant pole. It boosts the bandwidth by utilizing the resonance characteristics of LC networks. To reduce the value of the peaking inductor, a new negative current-current feedback mechanism is proposed. The employment of both inductive peaking and current feedback further increases the bandwidth. Both the inductor series-peaking and the current-current feedback do not affect the supply voltage and DC biasing conditions. Theoretical analysis and simulation results show that a significant bandwidth enhancement is achieved.     

A New Differential CMOS Current-Mode Preamplifier for GBps Data Communications

This paper presents a new low-voltage fully differential CMOS current-mode preamplifier for GBps data communications. The number of transistors between the power and ground rails is only two so that the minimum supply voltage is one threshold voltage plus one pinch-off voltage. The preamplifier is a balanced two-stage configuration such that the effect of bias-dependent mismatches is minimized. A new inductive series-peaking technique is introduced to increase the bandwidth by utilizing the resonance characteristics of LC networks. In addition, a new negative differential current feedback technique is proposed to boost the bandwidth and to reduce the value of peaking inductors. The preamplifier has been implemented in TSMC 0.18 μm, 1.8 V, 6-metal mixed-mode CMOS technology and analyzed using Spectre from Cadence Design Systems with BSIM3v3 device models. For an optical front-end with a 0.3 pF photodiode capacitance, simulation results demonstrate that the preamplifier has bandwidth of 3.5 GHz and provides a transimpedance gain of 66 dBΩ. The total chip area is approximately 1 mm² and the DC power consumption is about 85 mW. Bendong Sun received the B.Eng. degree in electrical engineering from Shanghai Jiaotong University, Shanghai, China, in1992, and the MASc degree in electrical and computer engineering from Ryerson University, Toronto, Ontario, Canada, in 2003. He is currently working towards the Ph.D. degree in electrical and computer engineering at University of Waterloo, Waterloo, Ontario, Canada. During 1992 through 1998 he was a Design Engineer at China Electronics Engineering Design Institute, Beijing, China. From 1998 to 2000 he worked for Bently Nevada Corporation, a GE Power Systems business, as a System Engineer. Since 2001, he has been a Research Assistant with the System-on-Chip Laboratory at Ryerson University. His research interests include design of analog and mixed-signal integrated circuits for high-speed data communications. Fei Yuan received the B.Eng. degree in electrical engineering from Shandong University, Jinan, China in 1985, the MASc degree in chemical engineering and PhD degree in electrical engineering from University of Waterloo, Waterloo, Ontario, Canada in 1995 and 1999, respectively. During 1985–1989, he was a Lecturer in the Department of Electrical Engineering, Changzhou Institute of Technology, Jiangsu, China. In 1989 he was a Visiting Professor at Humber College of Applied Arts and Technology, Toronto, Canada. During 1989–1994, he worked for Paton Controls Limited, Sarnia, Ontario, Canada as a Controls Engineer. Since July 1999 he has been with the Department of Electrical and Computer Engineering, Ryerson University, Toronto, Ontario, Canada, where he is currently an Associate Professor and the Associate Chair for Undergraduate Studies and Faculty Affairs. He is the co-author of the book “Computer Methods for Analysis of Mixed-Mode Switching Circuits” (Kluwer Academic Publishers, 2004, with Ajoy Opal). Dr. Yuan received an “Excellence of Teaching" award from Changzhou Institute of Technology in 1988, a post-graduate scholarship from Natural Science and Engineering Research Council (NSERC) of Canada during 1997–1998. He is a senior member of IEEE and a registered professional engineer in the province of Ontario, Canada. Ajoy Opal (S'86-M'88) received the B. Tech degree from Indian Institute of Technology, New Delhi, India in 1981, and the MASc and PhD degrees from University of Waterloo, Waterloo, Ontario, Canada in 1984 and 1987, respectively. During 1989–92 he worked for Bell-Northern Research in the area of analog circuit simulation. He joined the Department of Electrical and Computer Engineering, University of Waterloo in 1992 and currently a Full Professor. Dr. Opal works in the area of simulation of analog and mixed digital-analog circuits, such as, switched capacitor, switched current, oversampled sigma-delta modulators. Other interests include circuit theory and filter design.     

New CMOS Class AB Transmitter for 10 Gb/s Serial Links

This paper presents a new fully differential CMOS class AB transmitter for 10 Gb/s serial links. The transmitter consists of a fully differential multiplexer, a rail-to-rail configured pre-amplification stage, and a push-pull output stage. The multiplexer achieves a high multiplexing speed by using modified pseudo-NMOS logic where pull-up networks are replaced with self-biased active inductors. The rail-to-rail configured pre-amplification stage with active inductors amplifies the signals from the multiplexer. The fully differential output current is generated by a class AB output stage operated in a push-pull mode. High data rates of the transmitter are obtained by ensuring that the transistors in both the pre-amplification and output stages are always in saturation and the voltage swing of all critical nodes is small. The fully differential configuration of the transmitter effectively suppresses common-mode disturbances, particularly those coupled from the power and ground rails, the electro-magnetic interference exerted from channels to neighboring devices is also minimized. The transmitter minimizes switching noise by drawing a constant current from the supply voltage. The transmitter has been implemented in TSMC 0.18 μm 1.8 V 6-metal CMOS technology and analyzed using Spectre from Cadence Design Systems with BSIM3.3 device models. Simulation results demonstrate that the transmitter provides a 5 mA peak-to-peak differential output current with 100 ps eye-width and >5 mA eye-height at 10 Gb/s. The transmitter consumes 18 mW with a total transistor area of 100 μm² approximately. Jean Jiang received the B.Eng. degree in Electrical Engineering from Wuhan University of Technology, Wuhan, China in 1995, and the M.A.Sc. degree in Electrical and Computer Engineering from Ryerson University, Toronto, Ontario, Canada in 2004. From 1999 to 2001, she worked for Ericsson Global IT Services where she was a technical staff to maintain computer networks. From 2002 to 2004, she was a research assistant and a M.A.Sc. student with the Microsystem Research Laboratory in the Department of Electrical and Computer Engineering at Ryerson University. She is now with Intel Corp., CA. as an IC design engineer. Her research interests are in analog CMOS circuit design for high-speed data communications. Jean Jiang was awarded the Ontario Graduate Scholarship in 2003–2005 for academic excellence. Fei Yuan received the B.Eng. degree in electrical engineering from Shandong University, Jinan, China in 1985, the M.A.Sc. degree in chemical engineering and Ph.D. degree in electrical engineering from University of Waterloo, Waterloo, Ontario, Canada in 1995 and 1999, respectively. During 1985–1989, he was a Lecturer in the Department of Electrical Engineering, Changzhou Institute of Technology, Jiangsu, China. In 1989 he was a Visiting Professor at Humber College of Applied Arts and Technology, Toronto, Ontario, Canada, and Lambton College of Applied Arts and Technology, Sarnia, Ontario, Canada. He was with Paton Controls Limited, Sarnia, Ontario, Canada as a Controls Engineer during 1989–1994. Since 1999 he has been with the Department of Electrical and Computer Engineering, Ryerson University, Toronto, Ontario, Canada, where he is currently an Associate Professor and the Associate Chair for Undergraduate Studies and Faculty Affairs. He is the co-author of the book Computer Methods for Analysis of Mixed-Mode Switching Circuits (Springer-Verlag, 2004, with Ajoy Opal). Dr. Yuan received the Ryerson Research Chair award from Ryerson University in Jan. 2005, the Research Excellence Award from the Faculty of Engineering and Applied Science of Ryerson University in 2004, the post-graduate scholarship from Natural Science and Engineering Research Council of Canada during 1997–1998, and the Teaching Excellence Award from Changzhou Institute of Technology in 1988. Dr. Yuan is a senior member of IEEE and a registered professional engineer in the province of Ontario, Canada.     

A 1.5 V Current-Mode CMOS RMS-to-DC Converter

A very low voltage, current-mode CMOS RMS-to-DC converter is presented. It is fully designed using MOS Translinear techniques. More specifically, its main building blocks are a squarer/divider and a geometric-mean cell which are obtained by using simple second-order MOS Translinear loops in a folded configuration, leading to a very regular and compact implementation. A novel biasing technique is employed for such loops, allowing them to operate at supply voltages as low as 1.5 V. Experimental results for a prototype IC demonstrating the correct operation of the circuit are included.     

A new CMOS class AB serial link transmitter with a low supply voltage sensitivity

This paper presents a new class AB transmitter with a low supply voltage/ground bouncing sensitivity for 10 Gb/s serial links. The low sensitivity of the output current to supply voltage fluctuation and ground bouncing is achieved by operating the system in a rail-to-rail swing mode. High data rates are obtained by multiplexing at low-impedance nodes and inductive shunt peaking with active inductors. The fully differential configuration and bipolar signaling of the transmitter minimize the effect of both common-mode disturbances and electro-magnetic interferences exerted from channels to neighboring devices. The class AB operation of the transmitter minimizes its static power consumption. The proposed transmitter is implemented in a 1.2 V 0.13μm CMOS technology and analyzed using Spectre from Cadence Design Systems with BSIM3v3 device models. Both pre and post-layout simulation results demonstrate that the transmitter conveys a sufficiently large differential output current that is insensitive to supply voltage fluctuation and ground bouncing at 10 Gb/s. Fei Yuan received the B.Eng. degree in electrical engineering from Shandong University, Jinan, China in 1985, the M.A.Sc. degree in chemical engineering, and Ph.D. degree in electrical engineering from University of Waterloo, Waterloo, Ontario, Canada in 1995 and 1999, respectively. During 1985–1989, he was a Lecturer in the Department of Electrical Engineering, Changzhou Institute of Technology, Jiangsu, China. In 1989 he was a Visiting Professor at Humber College of Applied Arts and Technology, Toronto, Ontario, Canada, and Lambton College of Applied Arts and Technology, Sarnia, Ontario, Canada. He was with Paton Controls Limited, Sarnia, Ontario, Canada as a Controls Engineer during 1989–1994. Since 1999 he has been with the Department of Electrical and Computer Engineering, Ryerson University, Toronto, Ontario, Canada, where he is currently an Associate Professor and the Associate Chair for Undergraduate Studies and Faculty Affairs. He is the co-author of the book Computer Methods for Analysis of Mixed-Mode Switching Circuits (Springer-Verlag, 2004, with Ajoy Opal). Dr. Yuan received the Ryerson Research Chair award from Ryerson University in Jan. 2005, the Research Excellence Award from the Faculty of Engineering and Applied Science of Ryerson University in 2004, the post-graduate scholarship from Natural Science and Engineering Research Council of Canada during 1997–1998, and the Teaching Excellence Award from Changzhou Institute of Technology in 1988. Dr. Yuan is a senior member of IEEE and a registered professional engineer in the province of Ontario, Canada. Minghai Li received the B.Eng. (96) and M.A.Sc (06) degrees from North University of China and Ryerson University, Toronto, Ontario, Canada, respectively, both in Electrical and Computer Engineering. During 1996–2001, he was with Motorola Semiconductor (China) as a MCU product engineer. He was involved with MCU new product design, simulation, and test program development. He was a research assistant and a M.A.Sc student with the Microsystems Research Laboratory in the Department of Electrical and Computer Engineering at Ryerson University. He is now with Micron Technology Inc., Boise, Idaho, USA as a design engineer. His research interest is in the design of CMOS mixed-signal circuits for high-speed data transmission, including multiplexer, driver, pre-emphasis, and VCOs.     

CMOS Design of a Current-Mode Multiplier/Divider Circuit with Applications to Fuzzy Controllers

Multiplier and divider circuits are usually required in the fields of analog signal processing and parallel-computing neural or fuzzy systems. In particular, this paper focuses on the hardware implementation of fuzzy controllers, where the divider circuit is usually the bottleneck. Multiplier/divider circuits can be implemented with a combination of A/D-D/A converters. An efficient design based on current-mode data converters is presented herein. Continuous-time algorithmic converters are chosen to reduce the control circuitry and to obtain a modular design based on a cascade of bit cells. Several circuit structures to implement these cells are presented and discussed. The one that is selected enables a better trade-off speed/power than others previously reported in the literature while maintaining a low area occupation. The resulting multiplier/divider circuit offers a low voltage operation, provides the division result in both analog and digital formats, and it is suitable for applications of low or middle resolution (up to 9 bits) like applications to fuzzy controllers. The analysis is illustrated with Hspice simulations and experimental results from a CMOS multiplier/divider prototype with 5-bit resolution. Experimental results from a CMOS current-mode fuzzy controller chip that contains the proposed design are also included.     

Design Strategies for Class A CMOS CCIIS

In this paper, solutions for class A CCIIs are discussed and design arrangements are suggested to achieve improved performance in terms of gain accuracy, impedance level, offset and linearity. The noise performance is also evaluated and compared for the various solutions. Finally, a novel CCII is proposed which is based on an innovative arrangement of the biasing. The circuit provides a THD 15 dB lower than previous solutions and has a linearity feature which has low sensitive to the mismatch of the parameters and V _T .     

An 8 Bit Current-Mode CMOS A/D Converter with Three Level Folding Amplifiers

An 8 bit current-mode folding and interpolation analog to digital converter (ADC) with three-level folding amplifiers is proposed in this paper. A current-mode three-level folding amplifier is employed not only to reduce the number of reference current sources, but also to decrease a power dissipation within the ADC. The designed ADC fabricated by a 0.8 m n-well CMOS double metal/single poly process occupies the chip area of 2.2 × 1.6. The experimental result shows the power dissipation of 33.6 mW with a power supply of 5 V.     

A modified Park-Kim voltage-controlled ring oscillator for multi-Gbps serial links

This paper proposes a new multi-stage CMOS voltage-controlled ring VCO called modified Park-Kim ring VCO for multi-Gbps serial links. An in-depth comparative study of pros and cons of Park-Kim VCO and the modified Park-Kim VCO with both single and dual delay paths is given. We show that the modified Park-Kim VCO offers an improved oscillation frequency, large output voltage swing, comparable frequency tuning range and phase noise as compared with Park-Kim VCO proposed in [1, 2]. We further show that although the modified Park-Kim VCO with single delay path and that with dual delay path offer comparable oscillation frequencies when the number of stages of the VCOs is high, the former provides a large frequency tuning range and reduced circuit complexity. To verify performance improvement, both Park-Kim VCOs and the modified Park-Kim VCOs are implemented in TSMC’s-0.18 μm, 1.8 V CMOS technology and analyzed using SpectreRF from Cadence Design Systems with BSIM3.3 device models. Simulation results are presented.     

A sub 1 V high PSRR CMOS bandgap voltage reference

A Bandgap circuit capable of generating a reference voltage of less than 1 V with high PSRR and low temperature sensitivity is proposed. High PSRR achieved by means of an improved current mode regulator which isolates the bandgap voltage from the variations and the noise of the power supply. A vigorous analytical approach is presented to provide a universal design guideline. The analysis unveils the sensitivity of the circuit characteristic to device parameters. The proposed circuit is fabricated in a CMOS technology and operates down to a supply voltage of 1.2 V. The circuit yields 20 ppm/°C of temperature coefficient in typical case and 50 ppm/°C of temperature coefficient in worst case over temperature range −40 to 140°C, 60 ppm/V of supply voltage dependence and 60 dB PSRR at 1 MHz without trimming or extra circuits for the curvature compensation. The entire circuit occupies 0.027 mm² of die area and consumes from a 1.2 V supply voltage at room temperature. Twenty chips are tested to show the robustness of the topology and the measurement results are compared with Monte Carlo simulation and analysis.     

A Wired-AND Current-Mode Logic Circuit Technique in CMOS for Low-Voltage, High-Speed and Mixed-Signal VLSIC

A wired-AND current-mode logic (WCML) circuit techniquein CMOS technology for low-voltage and high-speed VLSI circuitsis proposed, and a WCML cell library is developed using standard0.8 micron CMOS process. The proposed WCML technique appliesthe analog circuit design methodologies to the digital circuitdesign. The input and output logic signals are represented bycurrent quantities. The supply current of the logic circuitis adjustable for the required logic speed and the switchingnoise level. The noise is reduced on the power supply lines andin the substrate by the current-steering technique and by thesmooth swing of the reduced node potentials. Precise analogcircuits and fast digital circuits can be integrated on the samesilicon substrate by using the low noise property of the WCML.It is shown by the simulations that at low supply voltages, theWCML is faster and generates less switching noise when comparedto the static-CMOS logic. At high speeds, the power dissipationof the WCML is less than that of the static-CMOS logic.     

A 3 V Wideband CMOS Switched-Current A/D-Converter Suitable for Time-Interleaved Operation

The simulated and measured performance of an experimental 10-b wideband CMOS A/D converter design is presented. Fully-differential first-generation switched-current circuits with common-mode feedforward were used to implement a 1.5-b/stage pipelined architecture in order to evaluate the switched-current technique for digital radio applications. With f _in = 1.83, the measured spurious-free dynamic range (SFDR) is 60.3 dB and the signal-to-noise-and-distortion ratio (SNDR) = 46.5dB at 3 MS/s. Although this 3 V design was fabricated in a standard digital 5 V, 0.8 m CMOS process, a high bandwidth was achieved. Since the ADC maintains an SNDR 40 dB for input frequencies of more than 20 MHz, it has the highest input bandwidth reported for any CMOS switched-current A/D-converter implementation. Its sample rate can be increased by parallel, time-interleaved, operation. Measurement results are compared with the measured performance of other wideband switched-current A/D converters and found to be competitive also with respect to area and power efficiency.     

A tunable highly linear CMOS transconductor with 80 dB of SFDR

This paper presents a new tunable CMOS differential transconductor with an SFDR ranging from 80 to 94 dB. It is based on a core of two voltage buffers with local feedback loops to achieve low-output impedance. The two buffers drive an integrated polysilicon resistor, which is the actual transconductance element. The current generated at the resistor is delivered directly to the output using source coupled pairs. This avoids distortion generated by conventional architectures using current copying cells. The voltage buffers are based on the compact flipped voltage follower (FVF) cell. The proposed transconductor relies on the gain of local feedback loops instead of harmonic cancellation. This leads to a simpler design and less mismatch sensitivity. The proposed transconductor bandwidth is closer to that of the typical open-loop design than to one with global feedback, since the local feedback loop is much faster than a global one. It can be tuned down 20% of its maximum g_m which is enough to compensate for process variations. The proposed circuit was fabricated in a 0.5 μm CMOS technology and powered by a 5 V single supply. It was measured with 2 Vpp input signals up to 10 MHz. The maximum g_m value is 660 μA/V. The transconductor consumes 30 mW and occupies roughly a die area of 0.17 mm². Experimental results are presented to validate the proposed circuit.     

A Voltage-Translinear Based CMOS Signal Component Separator Chip for Linear LINC Transmitters

The LINC transmitter is an architecture that provides linear amplification using nonlinear but power efficient amplifiers. One crucial signal processing function of LINC is the signal component separator (SCS) which forms two constant-amplitude phase-modulated signals from the source signal. This paper presents an analog SCS chip implemented in a 0.35 m CMOS process using a novel design based on the so-called voltage-translinear circuit principle. An experimental LINC transmitter was built with the SCS chip, nonlinear amplifiers and a power combiner. Test results showed that all output spurious levels some -55 dBc and -48 dBc could be obtained with a North American Digital Cellular (NADC) signal and an IS-95 signal, respectively. This implies a high degree of linearity.     

A high precision temperature control system for CMOS integrated wide range resistive gas sensors

In this work we present an integrated interface for wide range resistive gas sensors able to heat the sensor resistance through a constant power heater block at 0°C–350°C operating temperatures. The proposed temperature control system is formed by a sensor heater (which fixes the sensor temperature at about 200°C), a R/f (or R/T) converter, which converts the resistive value into a period (or frequency), and can be able to reveal about 6 decades variation (from 10 KΩ up to 10 GΩ), and a digital subsystem that control the whole systems loop. This interface allows high sensibility and precision and performs good stability in temperature and power supply drift and low power characteristics so it can be used also in portable applications. Test measurements, performed on the fabricated chip, have shown an excellent agreement between theoretical expectations and simulation results. Giuseppe Ferri is an associate professor in Electronics at the Department of Electrical Engineering of L’ Aquila University, Ital. In 1993 he has been a visiting researcher at SGS-Thomson Milano, working in bipolar low-voltage op-amp design. In 1994-95 he has been visiting researcher at KU Leuven working in low-voltage CMOS design in the group of Prof. Sansen. His research activity is actually centred on the analog design of integrated circuits for portable applications (e.g., sensors and biomedicals) and circuit theory. He is co-author of a book entitled “Low Voltage, Low Power CMOS Current Conveyors”, Kluwer ed. (2003) and four text-books in Italian on Analogue Microelectronics (2005, 2006). Moreover, he is author and co-author of 74 papers on international and Italian journals and 123 talks at national and international conferences. Vincenzo Stornelli was born in Avezzano (AQ), Italy, on May 31, 1980. He received the Electronics Engineering degree (cum laude) in July 2004. In October 2004 he joined the Department of Electronic Engineering, University of L’Aquila, where he is actually involved with problems concerning project and design of integrated circuits for RF and sensor applications, CAD modelling, characterization, and design analysis of active microwave components, circuits, and subsystems. He regularly teaches courses of the European Computer patent and has regular collaborations with national corporations such as Thales Italia     

一种新型的晶体管级改进Booth编码单元电路

文章提出了一种新的高速低功耗晶体管级改革Booth编码单元电路。该电路组合了CMOS逻辑电路和传递管逻辑电路，采用高速低耗XOR和XNOR电路，仅用了30个晶体管就实现了改进Booth编码。在0.35μm的工艺条件下，HSPICE的仿真结果表明，电源电压3.3V和频率100MHz条件下，该改进Booth编码电路的延迟为0.34ns，平均功耗为0.13mW。     

一种用于大面积CMOS FPA的相关双采样保持电路

提出了一种基于动态源随器的、用于CMOS焦平面阵列的新结构相关双采样保持电路,并与现有的相关双采样保持电路作了详细的比较。理论分析和模拟结果表明,这种新结构的相关双采样保持电路具有结构简单、功耗小、驱动信号源少,以及能在芯片内实现双采样等优点。     

A New Low Voltage CMOS Transconductor for VHF Filtering Applications

In this paper, a new differential input CMOS transconductor circuit for VHF filtering application is introduced. The new circuit has a very high frequency bandwidth, large linear differential mode input range and good common mode signal rejection capability. Using 0.35 m CMOS technology with 3 V power supply, the transconductor has a ±0.9 V linear differential input range with a –54 dB total harmonic distortion (THD) and more than 1 GHz – 3 dB bandwidth. The large signal DC analysis and small signal ac analysis derived by compact equations are in line with SpectreS simulation. A 3rd order elliptic low pass g _m-C filter with a cutoff frequency of 150 MHz is demonstrated as an application of the new transconductor.     

A single-channel 8-bit 660 MS/s asynchronous SAR ADC with pre-settling procedure in 65 nm CMOS

A single-channel 8-bit low-power high-speed SAR ADC with a novel pre-settling procedure is presented in this paper. The proposed procedure relaxes the settling time significantly and improves the speed of the ADC. Moreover, the asynchronous technique avoids the high frequency internal clocks and further increases the speed of the SAR ADC. Based on SMIC 65 nm 1.2-V CMOS technology, the simulation results demonstrate that DNL and INL are −0.4/0.4 LSBs and −0.9/0.8 LSBs, respectively. At 660 MS/s sampling rate, the ADC consumes 7.6 mW from a 1.2 V supply. The proposed SAR ADC?s SNDR and SFDR are 49.5 dB and 64.2 dB, respectively.     

一种用于CMOS图像传感器的新结构光电器件

提出了一种用于CMOS图像传感器的新结构光电探测器件--双极光栅场效应晶体管.通过在器件中引入pn结,有效地增加了光生电荷的读出速率,因而与传统光栅晶体管相比,双极光栅晶体管具有工作速度快、响应灵敏度高、读出电路简单等优点.