Highly reliable, high-C DRAM storage capacitors with CVD TA2O5 films on rugged polysilicon

The authors report on a highly reliable stacked storage capacitor with ultrahigh capacitance using rapid-thermal-annealed low-pressure chemical vapor deposited (LPCVD) Ta₂O₅ films (~100 Å) deposited on NH₃-nitrided rugged poly-Si electrodes. Capacitances as high as 20.4 fF/μ² (corresponding to the thinnest t_ox.eff (16.9 Å) ever reported using LPCVD-Ta₂O₅ and poly-Si technologies) have been achieved with excellent leakage current and time-dependent dielectric breakdown (TDDB) characteristics. Extensive electrical characterization over a wide temperature range (~25-300°C) shows that Ta₂O ₅ films on rugged poly-Si electrodes have a better temperature stability in dielectric leakage and breakdown compared to the films on smooth poly-Si electrodes     

Effect of bottom electrode materials on the electrical andreliability characteristics of (Ba, Sr)TiO3 capacitors

The dielectric constant and the leakage current density of (Ba, Sr)TiO₃ (BST) thin films deposited on various bottom electrode materials (Pt, Ir, IrO₂/Ir, Ru, RuO₂/Ru) before and after annealing in O₂ ambient were investigated. The improvement of crystallinity of BST films deposited on various bottom electrodes was observed after the postannealing process. The dielectric constant and leakage current of the films mere also strongly dependent on the postannealing conditions. BST thin film deposited on Ir bottom electrode at 500°C, after 700°C annealing in O₂ for 20 min, has the dielectric constant of 593, a loss tangent of 0.019 at 100 kHz, a leakage current density of 1.9×10 ^-8 A/cm² at an electric field of 200 kV/cm with a delay time of 30 s, and a charge storage density of 53 fC/μm² at an applied field of 100 kV/cm. The BST films deposited on Ir with post-annealing can obtain better dielectric properties than on other bottom electrodes in our experiments. And Ru electrode is unstable because the interdiffusion of Ru and Ti occurs at the interface between the BST and Ru after postannealing. The ten year lifetime of time-dependent dielectric breakdown (TDDB) studies indicate that BST on Pt, Ir, IrO₂/Ir, Ru, and RuO₂/Ru have long lifetimes over ten gears on operation at the voltage bias of 2 V     

Novel capacitor process using diffusion barrier rounded by Si3N4 spacer for high density FRAM device

A novel capacitor process was successfully implemented in 4 Mb FRAM device by developing a barrier layer rounded by Si₃N₄ spacer (BRS) scheme. Using this process, it is possible to eliminate an undesired barrier etching damage, which is a major role in degrading ferroelectric properties. The novel capacitor process was generated by etching an Ir barrier layer and rounding the barrier by a Si₃N₄ spacer before preparing Pb(Zr _1-xTi_x)O₃ (PZT) films. It was observed that uniform sol-gel derived PZT films were prepared on the patterned Ir substrate by using Si₃N₄ spacer, which provides a smooth edge of the patterned cell. The contact resistance between bottom electrode and polysilicon plug after full integration was monitored below 700 Ω per contact with contact size 0.6×0.6 (μm²). Compared to the ferroelectric capacitor damaged by barrier etching, the novel Pb(Zr_1-xTi_x)O₃ (PZT) capacitor exhibited a well-saturated Q-V curve. The fully processed novel capacitor having 1.2×1.2 (μm²) effective area displayed remnant polarization of 14 (μC/cm²) at an operating voltage of 3.0 V. The BRS ferroelectric capacitor showed a reliable retention property until 100 h at 125°C. Same state retention (Qss) was stable with time up to 100 h while opposite state retention (Qos) showed a log-linear decay rate at 125°C thermal stress     

Spread-vertical-capacitor cell (SVC) for high-density dRAM's

An advanced three-dimensionally (3-D) stacked-capacitor cell, the spread-vertical-capacitor cell (SVC), was developed. SVC realized a storage capacitance (C_s) of 30 fF with a cell area of 1.8 μm², a capacitor height of 0.37 μm, and an equivalent SiO₂ film thickness of 7 nm for oxide-nitride-oxide (ONO). By extrapolating these results to 256-Mb DRAMs, a C_s of 24 fF is obtained with a cell area of 0.5 μm², a capacitor height of 0.4 μm, and an equivalent SiO₂ thickness of 5 nm, and these values satisfy the specifications for 256-Mb DRAMs. The low capacitor height of SVC makes possible a fabrication process using ArF excimer laser lithography     

原子层沉积方法制备低温多层Al2O3/TiO2复合封装薄膜的研究

原子层沉积(ALD)方法可以制备出高质量薄膜,被认为是可应用于柔性有机电致发光器件(OLED)最有发展前景的薄膜封装技术之一。本文采用原子层沉积(ALD)技术,在低温(80℃)下,研究了Al₂O₃及TiO₂薄膜的生长规律,通过钙膜水汽透过率(WVTR)、薄膜接触角测试等手段,研究了不同堆叠结构的多层Al₂O₃/TiO₂复合封装薄膜的水汽阻隔特性,其中5 nm/5 nm×8 dyads(重复堆叠次数)的Al₂O₃/TiO₂叠层结构薄膜的WVTR达到2.1×10^-5 g/m²/day。采用优化后的Al₂O₃/TiO₂叠层结构薄膜对OLED器件进行封装,实验发现封装后的OLED器件在高温高湿条件下展现了较好的寿命特性。     

Poly-Si/poly-SiCx heterojunction thin-film transistors

We have proposed heterojunction thin-film transistors having a stacked structure of poly-crystal silicon-carbon (SiC_x) and Si thin films, both of which are prepared by an excimer-laser crystallization method. A Si/SiC_x interface after intense excimer-laser irradiation for crystallization, was as abrupt as that of the as-deposited and amorphous structure. The device had a relatively high mobility of about 4 cm²/Vs and a sufficiently low leakage current of an order of 10^-14 A/μm even under intense light illumination conditions     

Low contact resistance metallization for gigabit scale DRAM's usingfully-dry cleaning by Ar/H2 ECR plasma

A fully-dry cleaning technique with Ar/H₂ Electron Cyclotron Resonance (ECR) plasma was developed as a low contact resistance metallization technology for gigabit scale DRAM contacts. By combining with ECR TiN/Ti-CVD, extremely low contact resistances of 296 Ω and 350 Ω for 0.3-μm contact diameter with aspect ratio of 7 were realized on n⁺ and p⁺ diffusion layers, respectively. No leakage current was observed. By using this technology, a DRAM ULSI, which was planarized by Chemical Mechanical Polishing (CMP) and had deep contact holes with aspect ratio of 6, was successfully demonstrated     

Two-step annealing technique for leakage current reduction inchemical-vapor-deposited Ta2O5 film

A capacitor technology developed to obtain extremely thin Ta₂ O₅ dielectric film with an effective SiO₂ film thickness down to 3 nm (equivalent to 11 fF/μm²) for a 1.5-V, low-power, high-density, 64-Mb DRAM is discussed. The Ta₂ O₅ has low leakage current, low defect density, and excellent step coverage. The key process is two-step annealing after the deposition of the film by thermal chemical vapor deposition (CVD). The first step involves ozone (O₃) annealing with ultraviolet light irradiation, which reduces the leakage current. The second step is dry oxygen (O₂) annealing, which decreases the defect density. A more significant reduction in the leakage current is attained by the combination of the two annealing steps     

High-density MIM capacitors using Al2O3 andAlTiOx dielectrics

We have investigated the electrical characteristics of Al₂ O₃ and AlTiO_x MIM capacitors from the IF (100 KHz) to RF (20 GHz) frequency range. Record high capacitance density of 0.5 and 1.0 μF/cm² are obtained for Al₂ O₃ and AlTiO_x MIM capacitors, respectively, and the fabrication process is compatible to existing VLSI backend integration. However, the AlTiO_x MIM capacitor has very large capacitance reduction at increasing frequencies. In contrast, good device integrity has been obtained for the Al₂O₃ MIM capacitor as evidenced from the small frequency dependence, low leakage current, good reliability, small temperature coefficient, and low loss tangent     

Impact of time dependent dielectric breakdown and stress-inducedleakage current on the reliability of high dielectric constant(Ba,Sr)TiO3 thin-film capacitors for Gbit-scale DRAMs

Time dependent dielectric breakdown (TDDB) and stress-induced leakage current (SILC) are investigated for the reliability of (Ba,Sr)TiO₃ (BST) thin films. Both time to breakdown (T_BD) versus electric field (E) and T_BD versus 1/E plots show universal straight lines, independent of the film thickness, and predict lifetimes longer than 10 y at +1 V for 50 nm BST films with an SiO₂ equivalent thickness of 0.70 nm. SILC is observed at +1 V after electrical stress of BST films; nevertheless, 10 y reliable operation for Gbit-scale DRAMs is predicted in spite of charge loss by SILC. Lower (Ba+Sr)/Ti ratio is found to be strongly beneficial for low leakage, low SILC, long TBD, and therefore greater long-term reliability. This suggests a worthwhile tradeoff against the dielectric constant, which peaks at a (Ba+Sr)/Ti ratio of 1.05     

Submicrometer self-aligned AlGaAs/GaAs heterojunction bipolartransistor process suitable for digital applications

A self-aligned process is developed to obtain submicrometer high-performance AlGaAs/GaAs heterojunction bipolar transistors (HBTs) which can maintain a high current gain for emitter sizes on the order of 1 μm². The major features of the process are incorporation of an AlGaAs surface passivation structure around the entire emitter-base junction periphery to reduce surface recombination and reliable removal of base metal (Ti/W) deposits from the sidewall by electron cyclotron resonance (ECR) plasma deposition of oxide and ECR plasma etching by NF₃. A DC current gain of more than 30 can be obtained for HBTs with an emitter-base junction area of 0.5×2 μm² at submilliampere collector currents. The maximum f_T and f_max obtained from a 0.5×2 μm² emitter HBT are 46 and 42 GHz, respectively at I_C=1.5 and more than 20 GHz even at I_C=0.1 mA     

Excellent low-pressure-oxidized Si3N4 filmson roughened poly-Si for high-density DRAMs

High-reliability and good-performance stacked storage capacitors with high capacitance value of 17.8 fF/μm² has been realized using low-pressure-oxidized thin nitride films deposited on roughened poly-Si electrodes. These novel electrodes are fabricated by H ₃PO₄-etching and are RCA-cleaned. The leakage current density at +2.5 and -2.5 V are 0.07×10^-9 and -2.4×10^-8 A/cm², respectively, fulfilling the requirements of 256 Mb DRAM's. Weibull plots of time-dependent-dielectric-breakdown (TDDB) characteristics under constant current stress and constant voltage stress also show tight distribution and good electrical properties. Hence, this easy and simple technique is promising for future high-density DRAM's applications     

Small-scaled InGaP/GaAs HBTs with WSi/Ti base electrode and buriedSiO2

This paper describes the fabrication and characteristics of small-scaled InGaP/GaAs HBTs with high-speed as well as low-current operation. To reduce both the emitter size S_E and the base-collector capacitance C_BC simultaneously, the HBTs are fabricated by using WSi/Ti as the base electrode and by burying SiO₂ in the extrinsic base-collector region under the base electrode. WSi/Ti simplifies and facilitates processing to fabricate a small base electrode, and makes it possible to reduce the width of the base contact to less than 0.4 μm without the large increase in the base resistance. The DC current gain of 20 is obtained for an HBT with S _E of 0.3×1.6 μm² due to the suppression of emitter size effect by using InGaP as the emitter material. An HBT with SE of 0.6×4.6 μm² exhibited f_T of 138 GHz and f_max of 275 GHz at I_C of 4 mA; and an HBT with SE of 0.3×1.6 μm² exhibited f_T of 96 GHz and f_max of 197 GHz at I_C of 1 mA. These results indicate the great potential of these HBTs for high-speed and low-power circuit applications     

Oxidized Ta2O5/Si3N4dielectric films on poly-crystalline Si for dRAMs

A dielectric film technology characterized by a novel multilayer structure formed by oxidation of Ta₂O₅/Si₃ N₄ films on polysilicon has been developed to realize high-density dRAMs. The dry oxidation of the Ta₂O₅/Si₃N₄ layers was performed at temperatures higher than 900°C. This film has a capacitance per unit area from 5.5 to 6.0 fF/ μm², which is equivalent to that of a 6.0- to 6.5-nm-thick SiO₂. The leakage current at an effective electric field of 5 MV/cm is less than 10^-9 A/cm². Under such an electric field, the extrapolated time to failure for 50% cumulative failure can be as high as 1000 years     

The effects of NH3 plasma passivation on polysiliconthin-film transistors

The NH₃ plasma passivation has been performed for the first time on the polycrystalline silicon (poly-Si) thin-film transistors (TFT's). It is found that the TFT's after the NH₃ plasma passivation achieve better device performances, including the off-current below 0.1 pA/μm and the on/off current ratio higher than 10⁸, and also better hot-carrier reliability as well as thermal stability than the H₂-plasma devices. These improvements were attributed to not only the hydrogen passivation of the grain-boundary dangling bonds, but also the nitrogen pile-up at SiO₂/poly-Si interface and the strong Si-N bond formation to terminate the dangling bonds at the grain boundaries of the polysilicon films     

Half-VCC sheath-plate capacitor DRAM cell withself-aligned buried plate wiring

A trench-capacitor DRAM cell called a half-V_CC sheath-plate capacitor (HSPC) cell has been developed using 0.6-μm-process technology. It is applicable to DRAMs with capacities of 16 Mb and over. The HSPC cell achieves a storage capacitance of 51 fF in a cell area of 4.2 μm² and excellent immunity (critical charge Q_c<35 fC) against alpha-particle injection. These advantages are achieved using a half-V_CC sheath-plate structure, a 5.5-nm SiO₂-equivalent Si ₃N₄-SiO₂ composite film, and three self-alignment technologies involving buried plate wiring, a sidewall contact and a pad for the bit-line contact. The device performance is evaluated using an experimental 2-kb array     

Emission cross sections and spectroscopy of Ho3+ laserchannels in KGd(WO4)2 single crystal

The spectroscopic properties of Ho³⁺ laser channels in KGd(WO₄)₂ crystals have been investigated using optical absorption, photoluminescence, and lifetime measurements. The radiative lifetimes of Ho³⁺ have been calculated through a Judd-Ofelt (JO) formalism using 300-K optical absorption results. The JO parameters obtained were Ω₂=15.35×10^-20 cm², Ω ₄=3.79×10^-20 cm², Ω₆ =1.69×10^-20 cm². The 7-300-K lifetimes obtained in diluted (8·10¹⁸ cm^-3) KGW:0.1% Ho samples are: τ(⁵F₃)≈0.9 μs, τ( ⁵S₂)=19-3.6 μs, and τ(⁵F₅ )≈1.1 μs. For Ho concentrations below 1.5×10²⁰ cm^-3, multiphonon emission is the main source of non radiative losses, and the temperature independent multiphonon probability in KGW is found to follow the energy gap law τ_ph ^-1(0)=βexp(-αΔE), where β=1.4×10^-7 s^-1, and α=1.4×10³ cm. Above this holmium concentration, energy transfer between Ho impurities also contributes to the losses. The spectral distributions of the Ho³⁺ emission cross section σ_EM for several laser channels are calculated in σ- and π-polarized configurations. The peak a σ_EM values achieved for transitions to the ⁵I₈ level are ≈2×10^-20 cm² in the σ-polarized configuration, and three main lasing peaks at 2.02, 2.05, and 2.07 μm are envisaged inside the ⁵I₇→⁵I₈ channel     

The performances of (InAs)1/(GaAs)2short-period superlattice strained single-quantum-well laser on GaAssubstrate

We fabricated an (InAs)₁/(GaAs)₂ short-period superlattice (SPS) strained quantum-well laser at 1.07 μm by MOVPE. The SPS active layer has 10 periods of (InAs)₁/(_GaAs)₂ and an average mismatch of over 2.2%. In highly strained conditions the device showed a lasing wavelength of 1.07 μm, a threshold of 130 A/cm², and a characteristic temperature T₀ of 175 K. We measured the gain characteristic by the Hakki and Paoli method at LED conditions and obtained a high differential gain of 2.0×10^-15 cm² at the threshold current     

Optoelectronic properties of Zn0.52Se0.48/Si Schottky diodes

Zn_0.52Se_0.48/Si Schottky diodes are fabricated by depositing zinc selenide (Zn_0.52Se_0.48) thin films onto Si(1 0 0) substrates by vacuum evaporation technique. Rutherford backscattering spectrometry (RBS) analysis shows that the deposited films are nearly stoichiometric in nature. X-ray diffractogram of the films reveals the preferential orientation of the films along (1 1 1) direction. Structural parameters such as crystallite size (D), dislocation density (δ), strain (ε), and the lattice parameter are calculated as 29.13 nm, 1.187 × 10⁻¹⁵ lin/m², 1.354 × 10⁻³ lin⁻² m⁻⁴ and 5.676 × 10⁻¹⁰ m respectively. From the I–V measurements on the Zn_0.52Se_0.48/p-Si Schottky diodes, ideality and diode rectification factors are evaluated, as 1.749 (305 K) and 1.04 × 10⁴ (305 K) respectively. The built-in potential, effective carrier concentration (N_A) and barrier height were also evaluated from C–V measurement, which are found to be 1.02 V, 5.907 × 10¹⁵ cm⁻³ and 1.359 eV respectively.     

Fabrication and performance of selective HSG storage cells for 256Mb and 1 Gb DRAM applications

Fabrication of rapid thermal nitrided HSG transformed crown capacitor storage cells incorporating an ultrathin low pressure chemical vapor deposition (LPCVD) Ta₂O₅ and Si₃N ₄/SiO₂(NO) dielectric is proposed. 256 Mb array with HSG crown cells of 0.3 μm diameter×0.6 μm height and 49 A T_eff showed an area enhancement factor of 1.7 (relative to untransformed crown cell). C_min/C_max ratio of >0.95, and capacitance of 16.7 fF/cell is obtained. A measured leakage current density of 0.7 nA/cm² at 1.2 V is reported. Metal-oxide-semiconductor capacitor (MOSCAP) devices with HSG electrodes for 1 Gb application are characterized using capacitance-voltage (C-V) and current-voltage (I-V) analyses. Detailed HSG grain characterization results are presented with correlation to the electrical behavior of the devices. Devices are formed using LPCVD Ta₂O₅ and/or Si₃N₄ dielectric. HSG films formed from 4×10²⁰ atoms/cc phosphorus doped amorphous silicon show depletion in C-V behavior. It is shown that phosphine doping of HSG film is required to avoid depletion. Process selectivity of the UHV/CVD HSG transformation mechanism applied to thermal oxide and nitride field dielectrics is fully explored. Selectivity limits for different types of dielectric are also presented. Effect of critical parameters such as a-Si dopant concentration, HSG incubation time, anneal conditions, and a-Si layer thickness on HSG transformation are discussed for 1 Gb crown cells