OFDM系统中低复杂度联合译码和信道估计方法研究

本文针对OFDM(Orthogonal Frequency Division Multiplexing)系统提出了一种低复杂度联合译码和信道估计算法的接收机。接收机首先通过导频对信道进行估计，然后使用Turbo码译码输出判决信息对信道参数进行稳健的估计。仿真结果表明，即使系统误码率大于10^-2，经过3次迭代估计，系统性能提高仍有0．5-1dB；在高信噪比下，可显著地降低系统的误码底限。本文同时还给出了译码迭代次数对系统性能的影响。     

FPGA implementation of low complexity LDPC iterative decoder

Low-density parity-check (LDPC) codes, proposed by Gallager, emerged as a class of codes which can yield very good performance on the additive white Gaussian noise channel as well as on the binary symmetric channel. LDPC codes have gained lots of importance due to their capacity achieving property and excellent performance in the noisy channel. Belief propagation (BP) algorithm and its approximations, most notably min-sum, are popular iterative decoding algorithms used for LDPC and turbo codes. The trade-off between the hardware complexity and the decoding throughput is a critical factor in the implementation of the practical decoder. This article presents introduction to LDPC codes and its various decoding algorithms followed by realisation of LDPC decoder by using simplified message passing algorithm and partially parallel decoder architecture. Simplified message passing algorithm has been proposed for trade-off between low decoding complexity and decoder performance. It greatly reduces the routing and check node complexity of the decoder. Partially parallel decoder architecture possesses high speed and reduced complexity. The improved design of the decoder possesses a maximum symbol throughput of 92.95 Mbps and a maximum of 18 decoding iterations. The article presents implementation of 9216 bits, rate-1/2, (3, 6) LDPC decoder on Xilinx XC3D3400A device from Spartan-3A DSP family.     

Turbo decoder

We propose an adaptive channel SNR estimation algorithm required for the iterative MAP decoding of turbo decoders. The proposed algorithm uses the extrinsic values generated within the iterative MAP decoder to update the channel SNR estimate toward its optimum value per each decoder iteration or per each turbo code frame     

Iterative (turbo) soft interference cancellation and decoding forcoded CDMA

The presence of both multiple-access interference (MAI) and intersymbol interference (ISI) constitutes a major impediment to reliable communications in multipath code-division multiple-access (CDMA) channels. In this paper, an iterative receiver structure is proposed for decoding multiuser information data in a convolutionally coded asynchronous multipath DS-CDMA system. The receiver performs two successive soft-output decisions, achieved by a soft-input soft-output (SISO) multiuser detector and a bank of single-user SISO channel decoders, through an iterative process. At each iteration, extrinsic information is extracted from detection and decoding stages and is then used as a priori information in the next iteration, just as in turbo decoding. Given the multipath CDMA channel model, a direct implementation of a sliding-window SISO multiuser detector has a prohibitive computational complexity. A low-complexity SISO multiuser detector is developed based on a novel nonlinear interference suppression technique, which makes use of both soft interference cancellation and instantaneous linear minimum mean-square error filtering. The properties of such a nonlinear interference suppressor are examined, and an efficient recursive implementation is derived. Simulation results demonstrate that the proposed low complexity iterative receiver structure for interference suppression and decoding offers significant performance gain over the traditional noniterative receiver structure. Moreover, at high signal-to-noise ratio, the detrimental effects of MAI and ISI in the channel can almost be completely overcome by iterative processing, and single-user performance can be approached     

Design and Architecture of Low‐Latency High‐Speed Turbo Decoders

In this paper, we propose and present implementation results of a high‐speed turbo decoding algorithm. The latency caused by (de)interleaving and iterative decoding in a conventional maximum a posteriori turbo decoder can be dramatically reduced with the proposed design. The source of the latency reduction is from the combination of the radix‐4, center to top, parallel decoding, and early‐stop algorithms. This reduced latency enables the use of the turbo decoder as a forward error correction scheme in real‐time wireless communication services. The proposed scheme results in a slight degradation in bit error rate performance for large block sizes because the effective interleaver size in a radix‐4 implementation is reduced to half, relative to the conventional method. To prove the latency reduction, we implemented the proposed scheme on a field‐programmable gate array and compared its decoding speed with that of a conventional decoder. The results show an improvement of at least five fold for a single iteration of turbo decoding.     

Near-optimum decoding of product codes: block turbo codes

This paper describes an iterative decoding algorithm for any product code built using linear block codes. It is based on soft-input/soft-output decoders for decoding the component codes so that near-optimum performance is obtained at each iteration. This soft-input/soft-output decoder is a Chase decoder which delivers soft outputs instead of binary decisions. The soft output of the decoder is an estimation of the log-likelihood ratio (LLR) of the binary decisions given by the Chase decoder. The theoretical justifications of this algorithm are developed and the method used for computing the soft output is fully described. The iterative decoding of product codes is also known as the block turbo code (BTC) because the concept is quite similar to turbo codes based on iterative decoding of concatenated recursive convolutional codes. The performance of different Bose-Chaudhuri-Hocquenghem (BCH)-BTCs are given for the Gaussian and the Rayleigh channel. Performance on the Gaussian channel indicates that data transmission at 0.8 dB of Shannon's limit or more than 98% (R/C>0.98) of channel capacity can be achieved with high-code-rate BTC using only four iterations. For the Rayleigh channel, the slope of the bit-error rate (BER) curve is as steep as for the Gaussian channel without using channel state information     

Reduced-Complexity Turbo Equalization for Turbo Coded MIMO/OFDM Systems

1IntroductionTowards wireless systems Beyondthe3G(B3G),it isa great challenge for the physical layer to support high-speed transmissioninthe mobile environment to providecomfortable Internet access.Multiple Input MultipleOutput(MI MO)technique is effectiv…     

Turbo decodulation: iterative combined demodulation and source-channel decoding

We propose the combination of iterative demodulation and iterative source-channel decoding as a multiple turbo process. The receiver structures of bit-interleaved coded modulation with iterative decoding (BICM-ID), iterative source-channel decoding (ISCD), and iterative source coded modulation (ISCM) are merged to one novel turbo system, in which in two iterative loops reliability information is exchanged between the three single components, demodulator, channel decoder and (softbit) source decoder. Simulations show quality improvements compared to the different previously known systems, which use iterative processing only for two components of the receiver.     

Hadamard-based soft decoding for vector quantization over noisychannels

We present an estimator-based, or soft, vector quantizer decoder for communication over a noisy channel. The decoder is optimal according to the mean-square error criterion, and Hadamard-based in the sense that a Hadamard transform representation of the vector quantizer is utilized in the implementation of the decoder. An efficient algorithm for optimal decoding is derived. We furthermore investigate suboptimal versions of the decoder, providing good performance at lower complexity. The issue of joint encoder-decoder design is considered both for optimal and suboptimal decoding. Results regarding the channel distortion and the structure of a channel robust code are also provided. Through numerical simulations, soft decoding is demonstrated to outperform hard decoding in several aspects     

Iterative channel estimation for turbo equalization of time-varying frequency-selective channels

We investigate turbo equalization, or iterative equalization and decoding, as a receiver technology for systems where data is protected by an error-correcting code, shuffled by an interleaver, and mapped onto a signal constellation for transmission over a frequency-selective channel with unknown time-varying channel impulse response. The focus is the concept of soft iterative channel estimation, which is to improve the channel estimate over the iterations by using soft information fed back from the decoder from the previous iteration to generate "extended training sequences" between the actual transmitted training sequences.     

Pilot embedding for joint channel estimation and data detection in MIMO communication systems

A novel pilot-aided joint channel estimation and data detection method for MIMO communication systems is proposed. Unlike, conventional methods where pilots are time-multiplexed with data symbols, a pilot-embedding method where low-level pilots are transmitted concurrently with the data is used to obtain an initial estimate of the channel such that a turbo decoding process can be started. The soft information obtained from the turbo decoder is subsequently used to improve channel estimates.     

Systematic analysis of the decoding delay in multiview video

We present a framework for the analysis of the decoding delay in multiview video coding (MVC). We show that in real-time applications, an accurate estimation of the decoding delay is essential to achieve a minimum communication latency. As opposed to single-view codecs, the complexity of the multiview prediction structure and the parallel decoding of several views requires a systematic analysis of this decoding delay, which we solve using graph theory and a model of the decoder hardware architecture. Our framework assumes a decoder implementation in general purpose multi-core processors with multi-threading capabilities. For this hardware model, we show that frame processing times depend on the computational load of the decoder and we provide an iterative algorithm to compute jointly frame processing times and decoding delay. Finally, we show that decoding delay analysis can be applied to design decoders with the objective of minimizing the communication latency of the MVC system.     

On iterative decoding in some existing systems

Iterative decoding is used to achieve backward compatible performance improvement in several existing systems. Concatenated coding and iterative decoding are first set up using composite mappings, so that various applications in digital communication and recording can be described in a concise and uniform manner. An ambiguity zone detection (AZD) based iterative decoder, operating on generalized erasures, is described as an alternative for concatenated systems where turbo decoding cannot be performed. The described iterative decoding techniques are then applied to selected wireless communication and digital recording systems. Simulation results and utilization of decoding gains are discussed     

Iterative multiuser detection for turbo-coded FHMA communications

An iterative receiver structure Is proposed for turbo-coded frequency-hop multiple access (FHMA) systems. In FHMA systems, the adjacent channel interference (ACI) is the major contributor of multiple access interference (MAI) if orthogonal hopping patterns are used. The ACI is a function of the tone spacings of the adjacent subchannels and the rolloff factor of the pulse-shaping filter. The calculation of the ACI for a square-root raised-cosine pulse-shaping filter in an FHMA system is presented in this paper. In addition, a low complexity iterative multiuser detector is developed to mitigate the degradation caused by ACI in the FHMA systems. The iterative receiver structure is based on a modified turbo decoding algorithm which makes use of the a posteriori log-likelihood ratio (LLR) information of the systematic bits to obtain the a posteriori information of the turbo-encoded parity bits. Iterations of the receiver/decoder are used as the mechanism to estimate and mitigate the MAI in the FHMA system. The properties of both soft and hard interference suppressors based on the modified turbo decoding algorithm are examined and an efficient recursive implementation is derived. Compared to maximum-likelihood multiuser detection, the proposed system is more practical and its complexity is only a linear function of the number of users. Simulation results show that the proposed iterative receiver structure offers significant performance gain in bandwidth efficiency and the required signal-to-noise ratio (SNR) for a target bit-error rate (BER) over the noniterative receiver structure. Moreover, the single user performance can be achieved when imperfect power control exists     

Improved Soft Iterative Channel Estimation for Turbo Equalization of Time Varying Frequency Selective Channels

In this paper, we present computationally efficient iterative channel estimation algorithms for Turbo equalizer-based communication receiver. Least Mean Square (LMS) and Recursive least Square (RLS) algorithms have been widely used for updating of various filters used in communication systems. However, LMS algorithm, though very simple, suffers from a relatively slow and data dependent convergence behaviour; while RLS algorithm, with its fast convergence rate, finds little application in practical systems due to its computational complexity. Variants of LMS algorithm, Variable Step Size Normalized LMS (VSSNLMS) and Multiple Variable Step Size Normalized LMS algorithms, are employed through simulation for updating of channel estimates for turbo equalization in this paper. Results based on the combination of turbo equalizer with convolutional code as well as with turbo codes alongside with iterative channel estimation algorithms are presented. The simulation results for different normalized fade rates show how the proposed channel estimation based-algorithms outperformed the LMS algorithm and performed closely to the well known Recursive least square (RLS)-based channel estimation algorithm.     

A low-complexity iterative multiuser receiver for turbo-codedDS-CDMA systems

Optimal joint multiuser detection and decoding for direct-sequence code-division multiple-access (DS-CDMA) systems with forward error correction normally requires prohibitively high computational complexity. A suboptimal solution with low complexity is therefore appealing for use in practical applications. We propose a low-complexity iterative multiuser receiver for turbo-coded DS-CDMA systems. The proposed approach consists of a modified decorrelating decision-feedback detector (MDDFD) and K single-user turbo decoders, where K is the number of users in the DS-CDMA system. The MDDFD is derived on the basis of maximizing a likelihood probability and has a feature that it can use the reliability information from the turbo decoders' output. In addition, the MDDFD can deliver interference-cancelled soft outputs to the turbo decoders where the calculation of transition metrics is modified appropriately. Both performance analysis and computer simulation results have indicated that the reliability information from the turbo decoders' output can enhance the multiuser detection capability of the MDDFD. Computer simulations have also shown that the proposed iterative multiuser receiver outperforms the conventional DDFD-based multiuser receiver in terms of the bit-error probability     

A contribution to the reduction of the dynamic power dissipation in the turbo decoder

In the field of mobile communication systems, the energy issue of a turbo decoder becomes an equivalent constraint as throughput and performance. This paper presents a contribution to the reduction of the power consumption in the turbo decoder. The main idea is based on re-encoding technique combined with dummy insertion during the iterative decoding process. This technique, named “toward zero path” (TZP) helps in reducing the state transition activity of the Max-Log-MAP algorithm by trying to maintain the survivor path on the ‘zero path’ of the trellis. The design of a turbo decoder based on the TZP technique, associated with different power reduction technique (saturation of state metrics, stoping criterium) is described. The resulting turbo decoder was implemented onto a Xilinx VirtexII-Pro field-programmable gate array (FPGA) in a digital communication experimental setup. Performance and accurate power dissipation measurements have been done thanks to dynamic partial reconfiguration of the FPGA device. The experimental results have shown the interest of the different contributions for the design of turbo decoders.     

新的降低复杂度的Turbo均衡

Turbo均衡是一种通过反复均衡和信道译码来提高接收性能的迭代接收机算法。通常的Turbo均衡算法采用均衡与软输出译码的迭代运算，由于均衡和译码的重复计算，使得复杂度大大提高。文中提出了2种降低复杂度的Turbo均衡器：第一种采用软判决维特比译码，第二种采用软输入硬输出的维特比译码。通过仿真表明，这2种算法在几乎没有损失接收性能的情况下，大大降低了计算复杂度，并且第二种的性能要好于第一种。     

Bandwidth-efficient turbo trellis-coded modulation using puncturedcomponent codes

We present a bandwidth-efficient channel coding scheme that has an overall structure similar to binary turbo codes, but employs trellis-coded modulation (TCM) codes (including multidimensional codes) as component codes. The combination of turbo codes with powerful bandwidth-efficient component codes leads to a straightforward encoder structure, and allows iterative decoding in analogy to the binary turbo decoder. However, certain special conditions may need to be met at the encoder, and the iterative decoder needs to be adapted to the decoding of the component TCM codes. The scheme has been investigated for 8-PSK, 16-QAM, and 64-QAM modulation schemes with varying overall bandwidth efficiencies. A simple code choice based on the minimal distance of the punctured component code has also been performed. The interset distances of the partitioning tree can be used to fix the number of coded and uncoded bits. We derive the symbol-by-symbol MAP component decoder operating in the log domain, and apply methods of reducing decoder complexity. Simulation results are presented and compare the scheme with traditional TCM as well as turbo codes with Gray mapping. The results show that the novel scheme is very powerful, yet of modest complexity since simple component codes are used     

High-throughput Block Turbo Decoding: From Full-parallel Architecture to FPGA Prototyping

Ultra high-speed block turbo decoder architectures meet the demand for even higher data rates and open up new opportunities for the next generations of communication systems such as fiber optic transmissions. This paper presents the implementation, onto an FPGA device of an ultra high throughput block turbo code decoder. An innovative architecture of a block turbo decoder which enables the memory blocks between all half-iterations to be removed is presented. A complexity analysis of the elementary decoder leads to a low complexity decoder architecture for a negligible performance degradation. The resulting turbo decoder is implemented on a Xilinx Virtex II-Pro FPGA in a communication experimental setup which also includes an innovative parallel product encoder. The implemented block turbo decoder processes input data at 600 Mb/s. The component code is an extended Bose, Ray-Chaudhuri, Hocquenghem (eBCH(16,11)) code. Some solutions to reach even higher data rates are finally presented.