Effects of ion implantation on deep-submicrometer, drain-engineeredMOSFET technologies

The effects of ion implantation on the reliability of thin-oxide (7-nm) MOS structures using drain engineering, e.g. lightly doped-drain (LDD), Inverse-T, large-angle-tilt-implanted drain (LATID), are examined. High-dose, conventional source/drain implants with no spacer present are seen to degrade oxide integrity severely by increasing the gate-to-diffusion leakage along the gate perimeter. The oxide degradation results in a reduction of the oxide breakdown strength rather than an increase in the perimeter shorting defect density. Gate oxide integrity is improved if oxide spacer technologies are used prior to source/drain implantation. To be fully effective these spacers must be thick enough to stop ion penetration at the edge of the polysilicon gate. Oxide spacers grown by reoxidation to ion-implant-induced gate-oxide degradation than oxide spacers formed by CVD oxide. The bird's beak which forms during the reoxidation step is thought to improve gate reliability by thickening the gate oxide at the gate-feature edge. No yield loss was observed for the low doses (<10 ¹⁴ As/cm²) used for LDD implants. Inverse-T- and GOLD-type devices exhibit the same edge degradation as conventional devices but are further affected by the implant which penetrates the thin T-bar     

Disposable polysilicon LDD spacer technology

An advanced 0.5-μm CMOS disposable lightly doped drain (LDD) spacer technology has been developed. This 0.5-μm CMOS technology features surface-channel LDD NMOS and PMOS devices, n⁺/p⁺ poly gates, 125-A-thick gate oxide, and Ti-salicided source/drain/gate regions. Using only two masking steps, the NMOS and PMOS LDD spacers are defined separately to provide deep arsenic n⁺ regions for lower salicided junction leakage, while simultaneously providing shallow phosphorus n^- and boron p^- regions for improved device short-channel effects. Additionally, the process allows independent adjustment of the LDD and salicide spacers to optimize the LDD design while avoiding salicide bridging of source/drain to gate regions. The results indicate extrapolated DC hot-carrier lifetimes in excess of 10 years for a 0.3-μm electrical channel-length NMOS device operated at a power-supply voltage of 3.3 V     

High-voltage-tolerant I/O buffers with low-voltage CMOS process

This paper presents high-voltage-tolerant I/O buffer designs for a 1.9-V external cache interface and a 3.3-V system interface using 1.9-V MOS transistors in a 0.21-μm process with 40-Å gate-oxide thickness. Various circuit techniques are used for 1.9- and 3.3-V I/O buffers to ensure that the voltage across the gate oxide of every MOS element is below specified limits of 2.2 V for transient (short duty cycle) and 1.9 V for steady state. Only one PMOS pullup driver transistor between the bond pad and the power supply, and one NMOS pulldown driver transistor between the bond pad and ground, are used for the 1.9-V I/O buffer design, while cascoded MOS transistors between the bond pad and power supply or ground terminals are used for the 3.3-V I/O buffer design. The primary design goal is to ensure the reliability of MOS elements by avoiding excessive gate oxide stress due to high electric fields. However, due to differences in requirements for speed, power-supply voltage, and tristate leakage current, completely different circuit techniques have been used for the two designs. Both of the designs have been successfully implemented in a 400-MHz UltraSPARC microprocessor     

A self-aligned elevated source/drain MOSFET

An advanced elevated source/drain CMOS process which features self-aligned lightly-doped drain (LDD) and channel implantation is described. Unlike conventional elevated source/drain structures which employ separate polysilicon deposition steps to define the source/drain and gate electrodes, this new structure provides self-alignment of the LDD regions with the heavily doped channel regions to avoid dopant compensation effects. This process employs a single selective silicon deposition step to define both the epitaxial source/drain and polycrystalline gate regions. A single sidewall spacer is used for both LDD and salicide definition. Unlike conventional elevated source/drain CMOS processes, the final MOSFET structure provides self-alignment of the LDD regions with the heavily doped channel regions. Salicidation is performed after selective silicon deposition to provide low sheet resistances for the source/drain and gate regions. Small-geometry NMOS and PMOS devices have been fabricated which display excellent short channel behavior     

双掺杂多晶Si栅MOSFET的截止频率研究

在前期对双掺杂多晶Si栅(DDPG)LDMOSFET的电场、阈值电压、电容等特性所作分析的基础上,仍然采用双掺杂多晶Si栅结构,以低掺杂漏/源MOS(LDDMOS)为基础,重点研究了DDPG-LDDMOSFET的截止频率特性.通过MEDICI软件,模拟了栅长、栅氧化层厚度、源漏区结深、衬底掺杂浓度以及温度等关键参数对器件截止频率的影响,并与相同条件下P型单掺杂多晶Si栅(p-SDPG)MOSFET的频率特性进行了比较.仿真结果发现,在栅长90 nm、栅氧厚度2 nm,栅极P,n掺杂浓度均为5×1019cm-3条件下,截止频率由78.74 GHz提高到106.92 GHz,幅度高达35.8%.此结构很好地改善了MOSFET的频率性能,得出的结论对于结构的设计制作和性能优化具有一定的指导作用,在射频领域有很好的应用前景.     

Junction leakage current degradation under high temperature reverse-bias stress induced by band-defect-band tunnelling in power VDMOS

A deep analysis of the intrinsic junction and surface currents in power vertically diffused MOS devices with sub-micrometer channel length and thin gate oxide has been carried on after a typical reliability high temperature reverse bias (HTRB) stress. A reference set of gated diodes has also been examined in order to better understand the onset and evolution of post-stress leakage degradation. A comparison among complete MOSs, single body diodes and enriched diodes allows to highlight the role played by the point defectivity both at gate interface and in the bulk silicon close to the junction surface. We found that the typical interface defects involved in the leakage degradation are shallow traps and can be de-populated simply by a thermally activated mechanism. More specifically, the main degradation mechanism relies to band-defect-band tunneling localized at the surface drain/body junction where an intrinsic n-i-p region evolves due to a bird’s beak lateral profile of the body diffusion. We have demonstrated that the most important contribution to the activation of the precursor defect sites is given by the transverse electrical field that develops just below the SiO₂/Si interface within the n-i-p region during the stress.     

Part I: Mixed-Signal Performance of Various High-Voltage Drain-Extended MOS Devices

In this paper, the optimization issues of various drain-extended devices are discussed for input/output applications. The mixed-signal performance, impact of process variations, and gate oxide reliability of these devices are compared. Lightly doped drain MOS (LDDMOS) was found to have a moderate performance advantage as compared to shallow trench isolation (STI) and non-STI drain-extended MOS (DeMOS) devices. Non-STI DeMOS devices have improved circuit performance but suffer from the worst gate oxide reliability. Incorporating an STI region underneath the gate–drain overlap improves the gate oxide reliability, although it degrades the mixed-signal characteristics of the device. The single-halo nature of DeMOS devices has been shown to be effective in suppressing the short-channel effects.      

Fundamental modification of gate silicon dioxide layer as a result of lateral gettering of electrically active centres

The method of the lateral gettering of the ionised donor centres from the gate oxide layer is presented. This method is based on the capture of the excess hydrogen from the gate oxide peripheral regions by the point defects in the lateral oxide layer. The additional generation of the point defects in the lateral oxide layer in the process of Ar⁺ ion bombardment was found to intensify the lateral gettering processes. The most effective passivation of the electrically active centres in the gate oxide layer was found to occur in the structures with a high perimeter/area ratio, particular to the MOS device of the VLSIC.     

The Effect of Electroactive Defects in the Gate Oxide on the Threshold Voltage of a Submicron MOS Transistor

A new mechanism underlying the effect of the gate oxide geometry on the threshold voltage and other electrical properties of an MOS transistor (MOST) is proposed. This mechanism includes a relationship between the ionized center concentration in the gate oxide and its length. The dependence of the charge on these centers on the gate oxide configuration is associated with hydrogen redistribution between the gate and side oxide layers, as well as with the superposition of the ionized center distributions in the oxide layer along its horizontal and vertical boundaries in the peripheral drain and source contact windows. The revealed strong dependence of the charge density of the ionized centers in the oxide layer on the gate configuration (up to charge polarity reversal) specifies the strong dependence of the threshold voltage on the configuration of the gate and side oxide layers.     

The degradation mechanisms in high voltage pLEDMOS transistor with thick gate oxide

The hot-carrier degradation behavior in a high voltage p-type lateral extended drain MOS (pLEDMOS) with thick gate oxide is studied in detail for different stress voltages. The different degradation mechanisms are demonstrated: the interface trap formation in the channel region and injection and trapping of hot electrons in the accumulation and field oxide overlapped drift regions of the pLEDMOS, depending strongly on the applied gate and drain voltage. It will be shown that the injection mechanism gives rise to rather moderate changes of the specific on-resistance (Ron) but tiny changes of the saturation drain current (Idsat) and the threshold voltage (Vth). CP experiments and detailed TCAD simulations are used to support the experimental findings. In this way, the abnormal degradation of the electrical parameters of the pLEDMOS is explained. A novel structure is proposed that the field oxide of the pLEDMOS transistor is used as its gate oxide in order to minish the hot-carrier degradation.     

Gate-oxide breakdown accelerated by large drain current inn-channel MOSFET's

A study of the time-dependent dielectric breakdown (TDDB) of thin gate oxides in small n-channel MOSFETs operated beyond punchthrough is discussed. Catastrophic gate-oxide breakdown is accelerated when holes generated by the large drain current are injected into the gate oxide. More specifically, the gate-oxide breakdown in a MOSFET (gate length=1.0 μm, gate width-15 μm) occurs in ~100 s at an applied gate oxide field of ~5.2 MV/cm during the high drain current stress, while it occurs in ~100 s at an applied gate oxide field of ~10.7 MV/cm during a conventional time-dependent dielectric breakdown (TDDB) test. The results indicate that the gate oxide lifetime is much shorter in MOSFETs when there is hot-hole injection than that expected using the conventional TDDB method     

Electrical characteristics of a DSA MOS transistor with a fine structure

Fabrication technologies and electrical characteristics of a diffusion self-aligned MOS transistor (DSA MOST) or a double-diffused MOS transistor (DMOST) are discussed in comparison with a conventional short-channel MOS transistor as a fundamental device for a VLSI. The symmetrical DSA MOS LSI with enhancement depletion configurations requires six photolithographic steps and the number of the steps is the same as that of an NMOS LSI with small physical dimensions. The only difference is the step orders of the enhancement channel doping in these devices. The lowering effects of the threshold voltage and the source drain breakdown voltage are smaller in the DSA MOST than in the conventional MOS transistor. The drain current IDof the symmetrical DSA MOS transistor is, respectively, 1.13 (in the nonsaturation region) and 1.33 (in the saturation region) times larger than that of the conventional short-channel NMOS transistor at the effective gate voltage of 3.0 V. The improvement of the short-channel effect, the current voltage characteristics, and the power-delay product are obtained by the scaling of the DSA MOS transistor.     

Radiation damage of thermally oxidized MOS capacitors

The influence of preparation parameters and the effect of X-rays (150 keV, 10⁴rad (Si)) on oxide charge Qoxand interface state density Nssin thermally oxidized MOS varactors under different biasing conditions during irradiation has been investigated. The interface state density was determined by the ac conductance method before and after irradiation. The oxide charge has been evaluated with regard to the charge Qssof the interface states. Qsshas beeu discussed with the aid of simple models concerning the energetic distribution and recharge character of the interface states. The results indicate a similar dependence between flatband voltage, interface state density, and normalized oxide charge density as a function of gate bias during irradiation. Furthermore, the so-called "oxidation triangle" of oxide charge before irradiation exists for interface states as well. Calculations on the basis of the Schottky barrier model of the irradiated MOS structure show that the radiation-induced charge exists at both interfaces in the oxide layer. Radiation tolerance of the MOS capacitors as a function of technological parameters is discussed.     

Oxide current in MOS transistors operated under charge pumping conditions

The present paper describes an alternative approach for isolating the oxide current from the gate current (GC) and its use for characterizing the bulk oxide in MOS transistors. The method is based on measurements of the gate as well as the substrate currents of MOS transistors pulsed by a train of square wave pulses under charge pumping conditions.The measurements are done on various experimental devices and different gate and drain/source voltage biasing. The GC has been measured and was found to be of typical behavior when it is plotted with respect to the gate voltage. Moreover, the gate and substrate currents are found to be of complementary shapes when plotted with respect to gate voltage. This behavior is made useful in studying and characterizing the oxide and the interface of MOS transistors.     

A JMOS transistor fabricated with 100-Å low-pressure nitrided-oxide gate dielectric

A Junction MOS (JMOS) transistor is proposed to offer increased performance over conventionally scaled NMOS devices as the gate dielectric thickness is reduced. The design, fabrication, and characterization of the JMOS device with a 100-Å gate dielectric is presented. Conventionally scaled NMOS and JMOS devices with gate lengths down to 1 µm are compared. The JMOS devices show a 25- percent increase in channel electron mobility and a 15-percent increase in drain current for equivalent gate drives with minimal adverse short-channel effects.     

The Formation of Shallow Low-Resistance Source-Drain Regions for VLSI CMOS Technologies

As a result of MOS device scaling, very shallow source-drain structures are needed to minimize short-channel effects in 1-/spl mu/m transistors. This can be readily achieved with highly doped arsenic regions for NMOS devices but is more difficult using boron for PMOS devices. In addition, shallow junctions suffer from inherently high sheet resistances due to dopant solid solubility limitations. This paper proposes an improved CMOS source-drain technology to overcome both these problems. The technique employs amorphizing silicon implants prior to dopant implantation to eliminate ion channeling and platinum silicidation to substantially reduce sheet resistance. Counterdoping of the p/sup +/ regions by high-concentration arsenic implantation is used to enable both NMOS and PMOS devices to be manufactured with only one photolithographic masking operation. Using this technique, n/sup +/ and p/sup +/ junction depths are 0.22 /spl mu/ and of 8 /spl Omega/sq. sheet resistance. By creating oxide sidewalls on gate conductors, polysilicon can be silicided simultaneously with diffusions. Results of extensive materials analysis are discussed in detail. The technique has been incorporated into a VLSI CMOS process schedule at our laboratories.     

Sub-quarter-micrometer CMOS on ultrathin (400 Å) SOI

MOS transistors with effective channel lengths down to 0.2 μm have been fabricated in fully depleted, ultrathin (400 Å) silicon-on-insulator (SOI) films. These devices do not exhibit punchthrough, even for the smallest channel lengths, and have performance characteristics comparable to deep-submicrometer bulk transistors. The NMOS devices have a p⁺-polysilicon gate, and the PMOS devices have an n⁺-polysilicon gate, giving threshold voltages close to 1 V with very light channel doping. Because the series resistance associated with the source and drain regions can be very high in such thin SOI films, a titanium salicide process was used using a 0.25 μm oxide spacer. With this process, the sheet resistance of the silicided SOI layer is approximately 5 Ω/□. However, the devices still exhibit significant series resistance, which is likely due to contact resistance between the silicide and silicon source/drain regions     

Refractory metal silicon device technology

Films 2000–5000 Å thick of Mo or W deposited over thin films of thermally grown SiO₂ are shown to be effective high temperature diffusion masks against both phosphorous and boron. These metal films may be precisely patterned and their diffusion masking properties can be used to define the source and drain regions of MOSFETs. In this manner, self-registered MOSFETs can be fabricated with a portion of the diffusion masking metal film acting as the gate electrode. Using P or B doped deposited glasses as diffusion sources, n or p channel enhancement mode MOSFETs were made by diffusion through the exposed thin SiO₂ film into p and n type Si to form source and drain junctions. Contact was subsequently made by etching holes through the oxide layers to the source and drain regions and to the refractory metal gate electrode buried within the oxide layers. These devices exhibit channel mobilities between 200 and 300 cm²/V-sec at gate voltages about 10 V above threshold. The stability of MOS structures processed in a similar manner has been measured. After being stressed at ±6 × 10⁵ V/cm and 250°C for 15 hr, these devices exhibited shifts in their C---V characteristics less than 200 mV.     

Characteristics of buried-channel pMOS devices with shallowcounter-doped layers fabricated using channel preamorphization

Channel preamorphization, which is a technique used for shallow boron counter doping of pMOSFETs to suppress short-channel effects, improves gate oxide quality in MOS capacitors with the field-edge structure. This indicates that the source of gate oxide quality degradation is located near the field oxide edge, and is eliminated in channel preamorphization process by the gettering effects of defects induced near the original amorphous/crystalline interface. The leakage current of junction diodes, on the other hand, is increased by channel preamorphization. The leakage current increases because the defects near the original amorphous/crystalline interface act as generation centers in the depletion layers. This problem will be overcome by increasing the preamorphization depth. Hot carrier immunity of pMOSFETs is improved by channel preamorphization, especially in short-channel devices     

高压pLEDMOS器件在不同应力条件下导通电阻的衰退及改进方法

实验测试结果揭示高压pLEDMOS器件在不同的应力条件下,导通电阻的衰退结果不同,半导体器件专业软件MEDICI模拟结果表明Si/SiO2表面的陷阱产生以及热电子的注入和俘获导致了高压pLEDMOS器件在不同的应力条件下产生不同的导通电阻衰退.文中同时提出了一种改进方法:用场氧代替厚栅氧作为高压pLEDMoS器件的栅氧,MEDICI模拟结果显示该方法可以明显降低/减缓高压pLEDMOS导通电阻的衰退.