基于开关电流技术的连续小波变换的实现方法

开关电流技术是一种新的模拟抽样数据处理技术。开关电流电路具有一般电路不具有的优点，与标准数字CMOS工艺兼容。连续小波变换是分析非平稳信号的有力工具，在信号处理上有广泛的应用。本文提出用开关电流技术实现连续小波变换的方法，并用Matlab仿真证明了其理论可行性。     

二维离散小波变换的VLSI实现

小波变换图像编码获得了比传统DCT变换编码更好的图像质量和更高的压缩比,然而,实时二维小波变换需要大量运算,因此,专用小波变换芯片的设计已成为小波图像编码中的关键技术,文章提出了一种高速的二维小波变换的VLSI结构。根据模块化的设计思想,设计出一组二维小波变换的基本模块。通过将这些模块按变换要求适当组装,完成了多级二维小波变换,编写了相应的VerilogHDL模型,并进行了仿真和逻辑综合。     

离散小波变换的VLSI实现

离散小波变换已广泛应用于信号处理中。然而,实时小波变换需要大量运算,因此,专用小波变换芯片的设计已成为信号处理中的关键技术。文章提出了一种小波变换递归金字塔算法的VLSI结构,采用一组输入延迟单元和一个控制单元,用一组并行滤波器完成了小波变换。编写了相应的Verilog HDL模块,并进行了仿真和逻辑综合。     

离散小波变换的VLSI设计

在本文中，我们提出了一种离散小波变换（DWT）及其逆变换（IDWT）的VLSI结构，这一结构利用DWT／IDWT的结构和数值特性大大降低了系统的实现规模，同时由于采用了并行流水线和平衡数据通道等技术，可以获得每个时钟两个数据的处理速度和五个时钟节拍的流水线时延．基于硬件描述语言VHDL的模拟和综合结果表明，采用1．5μmCMOS工艺时，电路的规模为5058单元面积，在最坏情况下，最高时钟频率约可达55MHz，数据处理速度达到110Mpoints／s．     

一维离散小波/小波包变换的VLSI结构

小波/小波包变换作为强有力的信号处理手段,正在越来越多的领域中得到了应用,因而其硬件实现也日益受到重视.本文针对小波/小波包变换在语音编码中的应用,给出了一维离散小波/小波包变换的VLSI结构.和现有的一些实现方案不同,该结构可用于不同支集长度小波、不同长度数据段、不同变换阶数,具有较大的通用性和可编程性,可作为多种处理系统的片上变换单元,亦可单片实现     

整数5/3小波变换的VLSI结构设计

在JPEG 2000中,无损图像压缩是采用整数5/3小波变换实现的.JPEG 2000也给出了5/3小波基于提升方法的算法.对提升方法的整数5/3小波变换算法进行了研究,针对二维的变换提出一种VLSI结构.该结构由4个模块构成,模块之间并行运行,模块内部采用流水线技术.对多级变换,级间的运算还可交叉,体现了提升方法的优势,较大地提高了硬件效率.其主要优点是消耗资源少且运算速度高,同时也适用于其他整数小波变换.     

一维离散小波变换的VLSI设计

文章提出了一种离散小波变换的VLSI结构。这种结构由四部分构成：输入延迟单元、寄存器单元、滤波器单元和控制单元。该结构采用了递归金字塔算法(RPA)取代传统的PA算法。只用一组滤波器即可完成所有级别的小波运算。同时，结合Short-Length FIR技术，以减少乘法和加法的运算次数。在寄存器单元的设计上，采用了Lifetime Analysis技术，结合Forward-Backward Register Allocation(FBRA)方法，使寄存器的数目降至最低。     

小波图像编码的VLSI实现

设计了一种模块化的二维离散小波变换(2-D DWT)的VLSI结构.该结构可以实时完成小波变换,且很容易扩展.针对零树编码硬件实现方面的不足,利用一种简单的顺序扫描方式和两个标志阵列,设计了一种适合硬件实现的快速零树编码算法(FZIC)和FZIC硬件实现的VLSI结构,编写了2-D DWT和FZIC硬件结构的Veri log HDL模型,并进行了仿真和逻辑综合.结合2-D DWT和FZIC,实现了小波图像编码系统 ,并用ALTERA CPLD成功进行了验证.     

小波图像编码的VLSI实现

设计了一种模块化的二维离散小波变换(2-D DWT)的VLSI结构.该结构可以实时完成小波变换,且很容易扩展.针对零树编码硬件实现方面的不足,利用一种简单的顺序扫描方式和两个标志阵列,设计了一种适合硬件实现的快速零树编码算法(FZIC)和FZIC硬件实现的VLSI结构,编写了2-D DWT和FZIC硬件结构的Veri log HDL模型,并进行了仿真和逻辑综合.结合2-D DWT和FZIC,实现了小波图像编码系统 ,并用ALTERA CPLD成功进行了验证.     

二维9／7小波变换VLSI设计

为了提高JPEG2000图像压缩速度,提出一种基于提升算法的二维离散9／7小波变换（DWT）Mesh结构的VLSI设计方案,利用这种Mesh结构的VLSI能够实现并行处理一个图像的所有像素点。这种并行处理的Mesh结构可提高小渡变换电路速度,以及图像压缩的速度。     

基于对数域的连续小波变换处理电路

提出了一种新型的连续小波变换处理电路.电路中采用复解调技术实现小波变换,对变换系数进行了模数转换,可以与数字处理芯片接口,实现了信号的实时处理.电路完全采用对数域电流模式实现.对电路的主要模块进行了分析,仿真结果显示电路能在低电压低功率时得到宽动态范围的运用.     

Low-power Analog VLSI Implementation of Wavelet Transform

For applications requiring low-power, low-voltage and real-time, a novel analog VLSI implementation of continuous Marr wavelet transform based on CMOS log-domain integrator is proposed.Mart wavelet is approximated by a parameterized class of function and with Levenbery-Marquardt nonlinear least square method,the optimum parameters of this function are obtained.The circuits of implementating Mart wavelet transform are composed of analog filter whose impulse response is the required wavelet.The filter design is based on IFLF structure with CMOS log-domain integrators as the main building blocks.SPICE simulations indicate an excellent approximations of ideal wavelet.     

连续小波变换开关电流电路的实现

提出了一种用开关电流电路实现连续小波变换的方法,将连续小波变换转化为用带通滤波器组对信号进行处理,并用开关电流电路实现该带通滤波器组.文章采用基于第二代开关电流技术的带通滤波器组实现了8通道的Marr小波.仿真结果表明该滤波器组具有恒Q值,且每个带通滤波器的中心频率与理论值大致相符,从而证实了该方法的可行性.     

VLSI Architecture for Forward Discrete Wavelet Transform Based on B-spline Factorization

Based on B-spline factorization, a new category of architectures for Discrete Wavelet Transform (DWT) is proposed in this paper. The B-spline factorization mainly consists of the B-spline part and the distributed part. The former is proposed to be constructed by use of the direct implementation or Pascal implementation. And the latter is the part introducing multipliers and can be implemented with the Type-I or Type-II polyphase decomposition. Since the degree of the distributed part is usually designed as small as possible, the proposed architectures could use fewer multipliers than previous arts, but more adders would be required. However, many adders can be implemented with smaller area and lower speed because only few adders are on the critical path. Three case studies, including the JPEG2000 default (9, 7) filter, the (6, 10) filter, and the (10, 18) filter, are given to demonstrate the efficiency of the proposed architectures.Chao-Tsung Huang was born in Kaohsiung, Taiwan, R.O.C., in 1979. He received the B.S. degree from the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C., in 2001. He currently is working toward the Ph.D. degree at the Graduate Institute of Electronics Engineering, National Taiwan University. His major research interests include VLSI design and implementation for signal processing systems.Po-Chih Tseng was born in Tao-Yuan, Taiwan in 1977. He received the B.S. degree in Electrical and Control Engineering from National Chiao Tung University in 1999 and the M.S. degree in Electrical Engineering from National Taiwan University in 2001. He currently is pursuing the Ph.D. degree at the Graduate Institute of Electronics Engineering, Department of Electrical Engineering, National Taiwan University. His research interests include VLSI design and implementation for signal processing systems, energy-efficient reconfigurable computing for multimedia systems, and power-aware image and video coding systems.Liang-Gee Chen received the B.S., M.S., and Ph.D. degrees in electrical engineering from National Cheng Kung University, Tainan, Taiwan, R.O.C., in 1979, 1981, and 1986, respectively.In 1988, he joined the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C. During 1993–1994, he was a Visiting Consultant in the DSP Research Department, AT&T Bell Labs, Murray Hill, NJ. In 1997, he was a Visiting Scholar of the Department of Electrical Engineering, University of Washington, Seattle. Currently, he is Professor at National Taiwan University, Taipei, Taiwan, R.O.C. His current research interests are DSP architecture design, video processor design, and video coding systems.Dr. Chen has served as an Associate Editor of IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY since 1996, as Associate Editor of the IEEE TRANSACTIONS ON VLSI SYSTEMS since 1999, and as Associate Editor of IEEE TRANSACTIONS CIRCUITS AND SYSTEMS II since 2000. He has been the Associate Editor of the Journal of Circuits, Systems, and Signal Processing since 1999, and a Guest Editor for the Journal of Video Signal Processing Systems. He is also the Associate Editor of the PROCEEDINGS OF THE IEEE. He was the General Chairman of the 7th VLSI Design/CAD Symposium in 1995 and of the 1999 IEEE Workshop on Signal Processing Systems: Design and Implementation. He is the Past-Chair of Taipei Chapter of IEEE Circuits and Systems (CAS) Society, and is a member of the IEEE CAS Technical Committee of VLSI Systems and Applications, the Technical Committee of Visual Signal Processing and Communications, and the IEEE Signal Processing Technical Committee of Design and Implementation of SP Systems. He is the Chair-Elect of the IEEE CAS Technical Committee on Multimedia Systems and Applications, During 2001-2002, he served as a Distinguished Lecturer of the IEEE CAS Society. He received the Best Paper Award from the R.O.C. Computer Society in 1990 and 1994. Annually from 1991 to 1999, he received Long-Term (Acer) Paper Awards. In 1992, he received the Best Paper Award of the 1992 Asia-Pacific Conference on circuits and systems in the VLSI design track. In 1993, he received the Annual Paper Award of the Chinese Engineer Society. In 1996 and 2000, he received the Outstanding Research Award from the National Science Council, and in 2000, the Dragon Excellence Award from Acer. He is a member of Phi Tan Phi.     

二维离散小波变换的FPGA实现

依据传统的Mallat算法,提出了一种基于FPGA实现的高速二维小波变换的方法.该方法采用模块化设计,通过将这些模块按变换要求适当级联,可轻松实现多级二维离散小波分解.用Verilog HDL实现了相关模块,并进行了仿真和逻辑综合.     

一种适合JPEG2000的离散小波变换VLSI统一结构

提出了一种基于提升算法(1ifting)的离散小波变换(DWT)统一结构。它无需额外的边界延拓过程，经配置后可适用于JPEG2000中的无损或有损小波变换。通过将边界延拓过程内嵌于离散小波变换中，可以降低功耗，减少所需内存。为了达到更高的处理速度和硬件利用率，采用了流水线和折叠结构。这种高效紧凑的离散小波变换结构适用于JPEG2000编码器和各种实时图像／视频应用系统．     

基于开关电流技术的时域连续小波变换实现

首次提出基于开关电流技术的时域法连续小波变换实现。该方法利用幅度调制技术产生小波链实现小波变换,为小波变换的快速实现提供了新的途径。基于双线性变换采用开关电流积分器综合实现低通滤波器,解决了时域法小波变换实用电路集成化的关键问题。对开关电流低通滤波器用ASIZ进行仿真,结果证实其性能完全满足实用要求。