A new flipped voltage follower with enhanced bandwidth and low output impedance

The paper proposes a flipped voltage follower (FVF) cell with wider bandwidth and lower output impedance as compared to the conventional FVF. These improvements are obtained by adding a resistance in the feedback path of conventional FVF. A current mirror is implemented by using proposed FVF cell to verify the performance improvement. The circuits are designed in TSMC 0.18-µm CMOS technology with 1.5 V supply voltage. The simulation results show that bandwidth extension ratio (BWER) of newly developed FVF is 1.4 without peaking and 1.7 with peaking. The BWERs of the passive-compensated current mirror implemented by using proposed FVF cell are 1.28 without peaking and 1.58 with peaking in the frequency response.     

High frequency flipped voltage follower with improved performance and its application

In this paper a wideband flipped voltage follower (FVF) with low output impedance at high frequency has been proposed. Inductive-peaking-based bandwidth extension technique is employed in the FVF cell. The small signal high-frequency analysis of both conventional and proposed FVF has been done. It is shown in analytical derivation of the proposed FVF that by adding an inductive element in the feedback path, the bandwidth is enhanced. Simulation results show that bandwidth extension ratio (BWER) of proposed FVF is about 2.00, without extra dc power dissipation. A wideband low voltage current mirror has been developed by using proposed FVF in place of conventional FVF and by doing so, BWER of 2.98 has been achieved. The performances of circuits are verified in TSMC 0.18 μm CMOS, BSIM3 and Level 49 technology with 1.5 V power supply and by using Spectre simulator of Cadence.     

A very low output resistance and wide-swing class-AB level-shifted folded flipped voltage follower cell

The paper presents a class-AB flipped voltage follower (FVF) cell. In contrast to previous works in the literature, FVF cell, level shifter and folded FVF cell are merged in the proposed FVF cell to offer class-AB operation along with wide input/output voltage swing and low output resistance. In the proposed FVF cell, the level shifter increases the input/output voltage swing while the folding transistor provides an alternate path for sourcing current, which results in low output resistance. The proposed FVF cell offers wide input/output voltage swing of 0.80 V/0.67 V, high gain of 0.84, wide bandwidth of 54 MHz for the worst case load capacitance of 50 pF and low output resistance of 10 Ω. The proposed FVF cell is simulated using Cadence Virtuoso Analog Design Environment in 180 nm CMOS technology. The physical layout has been designed using Cadence Virtuoso Layout XL editor and post-layout simulation results are presented to demonstrate the performance of the proposed FVF cell. The corner analysis has also been performed to show the robustness of the proposed FVF cell.     

Low supply voltage high-performance CMOS current mirror with low input and output voltage requirements

This paper presents a scheme for the efficient implementation of a low supply voltage continuous-time high-performance CMOS current mirror with low input and output voltage requirements. This circuit combines a shunt input feedback and a regulated cascode output stage to achieve low input resistance and very high output resistance. It can be used as a high-precision current mirror in analog and mixed signal circuits with a power supply close to a transistor's threshold voltage. The proposed current mirror has been simulated and a bandwidth of 40 MHz has been obtained. An experimental chip prototype has been sent for fabrication and has been experimentally verified, obtaining 0.15-V input-output voltage requirements, 100-/spl Omega/ input resistance, and more than 200-M/spl Omega/ (G/spl Omega/ ideally) output resistance with a 1.2-V supply in a standard CMOS technology.     

Low power high output impedance high bandwidth QFGMOS current mirror

Current mirror is a basic block of any mixed-signal circuit for example in an analog-to-digital converter. Its precise performance is the key requirement for analog circuits where offset is a measure issue. The key parameter which defines the performance of current mirror is its input/output impedance, input swing, and bandwidth. In this paper, a low power design of current mirror using quasi-floating gate MOS transistor is presented. The proposed current mirror boosts its output impedance in range of giga-ohm through use of regulated cascode structure followed by super-cascode. Another improvement is done in reduced input compliance voltage limits with the help of level shifter. The proposed current mirror operates well for input current range 0–700 $\mathrm{\mu }A$ with an input and output impedance of 160 $\Omega$ and 8.55 $\mathrm{G}\Omega$ respectively and high bandwidth of 4.05 $\mathrm{GHz}$. The total power consumption of the proposed current mirror is about 0.84 mW. The low power consumption with enhanced output impedance and bandwidth suits proposed current mirror for various high-speed analog designs. Performance of the presented current mirror circuit is verified using HSpice simulations on 0.18 $\mathrm{\mu }m$ mixed-mode twill-well technology at a supply voltage of ±0.5 V.     

Low Voltage High Output Impedance Bulk-Driven Quasi-Floating Gate Self-Biased High-Swing Cascode Current Mirror

A low voltage self-biased high-swing cascode current mirror using bulk-driven quasi-floating gate MOSFET is proposed in this paper. The proposed current mirror bandwidth and especially the output impedance show a significant improvement compared to prior arts. The current mirror presented is designed using bulk-driven and bulk-driven quasi-floating gate N-channel MOS transistors, which helped it to operate at very low supply voltage of \({\pm }0.2\,\hbox {V}\). To achieve high output resistance, the current mirror uses regulated cascode stage followed by super cascode architecture. The small-signal analysis carried out proves the improvement achieved by proposed current mirror. The current mirror circuit operates well for input current ranging from 0 to \(250\,{\upmu }\mathrm{A}\) with good linearity and shows the bandwidth of 285 MHz. The input and output resistances are found as \(240\,\Omega \) and \(19.5\,\hbox {G}\Omega \), respectively. Further, the THD analysis and Monte Carlo simulations carried prove the robustness of proposed current mirror. The complete analysis is done using HSpice on UMC \(0.18\,\upmu \mathrm{m}\) technology.     

Quasi-floating gate MOSFET based low voltage current mirror

This paper demonstrates the use of quasi-floating gate MOSFET (QFGMOS) in the design of a low voltage current mirror and highlights its advantages over the floating gate MOSFET (FGMOS). The use of resistive compensation has been shown to enhance the bandwidth of QFGMOS current mirror. The proposed current mirror based on QFGMOS has a current range up to 500 μA with offset of 2.2 nA, input resistance of 235 Ω, output resistance of 117 kΩ, current transfer ratio of 0.98, dissipates 0.83 mW power and exhibits bandwidth of 656 MHz which increases to 1.52 GHz with resistive compensation. The theoretical and simulation results are in good agreement. The workability of the circuits has been verified using PSpice simulation for 0.13 μm technology with a supply voltage of ±0.5 V.     

A new low voltage level-shifted FVF current mirror with enhanced bandwidth and output resistance

This paper proposes a new high-performance level-shifted flipped voltage follower (LSFVF) based low-voltage current mirror (CM). The proposed CM utilises the low-supply voltage and low-input resistance characteristics of a flipped voltage follower (FVF) CM. In the proposed CM, level-shifting configuration is used to obtain a wide operating current range and resistive compensation technique is employed to increase the operating bandwidth. The peaking in frequency response is reduced by using an additional large MOSFET. Moreover, a very high output resistance (in GΩ range) along with low-current transfer error is achieved through super-cascode configuration for a wide current range (0–440 µA). Small signal analysis is carried out to show the improvements achieved at each step. The proposed CM is simulated by Mentor Graphics Eldospice in TSMC 0.18 µm CMOS, BSIM3 and Level 53 technology. In the proposed CM, a bandwidth of 6.1799 GHz, 1% settling time of 0.719 ns, input and output resistances of 21.43 Ω and 1.14 GΩ, respectively, are obtained with a single supply voltage of 1 V. The layout of the proposed CM has been designed and post-layout simulation results have been shown. The post-layout simulation results for Monte Carlo and temperature analysis have also been included to show the reliability of the CM against the variations in process parameters and temperature changes.     

A bulk-driven quasi-floating gate FVF current mirror for low voltage,low power applications

This paper introduces a new low-voltage, low-power FVF current mirror circuit. The bulk-driven (BD) technique is employed to achieve extended input voltage swing and low supply voltage. Besides, the quasi-floating gate (QFG) is used to achieve high frequency performance. The merging of (BD) and (QFG) appear as a good and attractive solution to improve the circuit performance with reduced supply voltage. Benefiting from the interesting properties of (BD-QFG) MOSFET (MOST) technique, the proposed FVF current mirror circuit exhibits superior performance compared to other previously reported works. The workability of the proposed circuit has been verified through ELDO simulator based on a 0.18 μm USMC process. It achieves an enhanced bandwidth (2.7 GHz), low power consumption (79.33 μW), a low input impedance (130 Ω), and high output impedance (9.5 G Ω) from a low supply voltage (0.8 V). Monte Carlo simulation is also carried out, which proves the robust performance of the proposed circuit against mismatches. An application of the proposed current mirror is presented in the form of the current comparator to ensure the workability of the proposed BD-QFG current mirror.     

MOS cascode-mirror biasing circuit operating at any current levelwith minimal output saturation voltage

A cascode biasing circuit is proposed which fixes the source voltage of the cascode transistor equal to the saturation voltage of the mirror transistor. The mirror can operate at any current level from weak to strong inversion. The design is based on ratios, and is technology-independent. Since the circuit ensures the smallest possible output saturation voltage, it has potential applications in all fields of low-voltage micropower design     

Class-AB Flipped Voltage Follower Cell with High Current Driving Capability and Low Output Resistance for High Frequency Applications

In this paper, a class-AB flipped voltage follower cell with high current driving capability is proposed. The proposed flipped voltage follower (FVF) cell offers increased current sourcing capability and large input/output voltage swing due to the use of bulk-driven and level shifter techniques, respectively. Further, it uses an additional NMOS transistor connected between output and ground terminals to increase the current sinking capability and to reduce the output resistance. The stability analysis has been performed by using Routh–Hurwitz stability criteria which confirms that the proposed FVF cell is stable. The proposed FVF cell also offers a high symmetrical slew rate. The proposed FVF cell has been simulated in Cadence virtuoso analog design environment using BSIM3v3 180 nm CMOS technology and simulation results are presented to validate the effectiveness of the proposed circuit.

     

A very high performance self-biased cascode current mirror for CMOS technology

This paper presents a novel high performance self-biased cascode current mirror (CM) for CMOS technology. The proposed circuit shows a resistance compensated high bandwidth CM operating at low voltages. This circuit uses super cascode configuration to obtain high output impedance required for high performance of CM. Active implementation of passive resistances of the proposed circuit is shown. The simulations of proposed CM are carried out by Mentor Graphics Eldospice based on TSMC 0.18 μm CMOS technology, for input current range of 0–500 μA. A bandwidth of 2.26 GHz, input and output resistances of 679 Ω and 482 MΩ respectively, are obtained with a single supply voltage of ?1 V.     

Evaluation of gate oxide breakdown effect on cascode class E power amplifier performance

A CMOS cascode class E power amplifier has been designed at 5.2 GHz. Its RF performances such as output and power-added efficiency have been examined in ADS simulation. The layout parasitic is accounted for in the post-layout simulation. Time-dependent drain-source voltage waveforms indicate that the drain of cascode transistor is subject to much higher voltage stress than that of main transistor. Analytical equation of output power including impact of gate-oxide breakdown is developed and compared with RF simulation results. Good agreement between the model predictions and ADS simulation is obtained. The gate-drain breakdown of the cascode transistor decreases the output power and power-added efficiency of the power amplifier significantly when the breakdown resistance is below 1 kΩ.     

Comparative study of sub-volt differential difference current conveyors

Enhancing the performances of analog circuits with sub-volt supplies becomes a great challenge for circuit designers. Techniques such as bulk-driven (BD) and quasi-floating gate (QFG) count among the suitable ones for ultra-low voltage (ULV) operation capability with extended input voltage range and simple CMOS circuitry. However, in comparison to the conventional gate-driven (GD) MOS transistor (MOST), these techniques suffer from several disadvantages such as low transconductance value and bandwidth that limit their applicability for some applications. Therefore, the idea of merging the BD and QFG techniques to eliminate their drawbacks appears as efficacious solution. This new merging is named bulk-driven quasi-floating gate (BD-QFG)^* technique and in order to demonstrate its advantages in compassion to BD and QFG ones, this paper presents a comparison study of three ULV differential difference current conveyor (DDCC) blocks based on BD, QFG and BD-QFG techniques. The significant increment of the transconductance and the bandwidth values of the BD-QFG are clearly observed. The proposed CMOS structures of the DDCCs work at ±300 mV supply voltage and 18.5 µW power consumption. The simulation results using 0.18 µm CMOS n-Well process from TSMC show the features of the proposed circuits.     

A feedforward technique with frequency-dependent current mirrorsfor a low-voltage wideband amplifier

A feedforward technique using frequency-dependent current mirrors for a low-voltage wideband amplifier is presented. In the conventional single-stage wideband amplifiers, the folded cascode structure is used. However, the common-gate transistor requires an additional V_{DS sat} and reduces the available output voltage range. In this study the cascode structure is avoided; instead, a frequency-dependent current mirror, whose input impedance becomes higher for a higher frequency, is used to form the feedforward path from the input of the current mirror with a feedforward capacitor. This technique is effective to improve a 100 MHz-1 GHz frequency characteristic of the amplifier. The amplifier has been fabricated using the standard 0.8 μm CMOS process. The phase margin is improved from 46-66° without sacrificing the unity gain frequency of 133 MHz compared with the amplifier without this technique. The amplifier operates at 2.5 V power supply voltage and consumes 12 mW     

A Current Mirror for Low Voltage, High Performance Analog Circuits

A current mirror for low voltage analog and mixed mode circuits is proposed. The current mirror has high input and output voltage swing capability and can operate at ±1.0 V supply. P-Spice simulations confirm the input current range of 1 A to 500 A with 2.5 GHz bandwidth for the proposed current mirror. Adaptive biasing increases the input voltage swing capability and decreases the undesired offset current. Resistive and capacitive compensation are used to increase its bandwidth.     

Novel low-voltage ultra-low-power DVCC based on floating-gate folded cascode OTA

In this paper a novel low-voltage ultra-low-power differential voltage current conveyor (DVCC) based on folded cascode operational transconductance amplifier OTA with only one differential pairs floating-gate MOS transistor (FG-MOST) is presented. The main features of the proposed conveyor are: design simplicity; rail-to-rail input voltage swing capability at a low supply voltage of ±0.5 V; and ultra-low-power consumption of mere 10 μW. Thanks to these features, the proposed circuit could be successfully employed in a wide range of low-voltage ultra-low-power analog signal processing applications. Implementation of new multifunction frequency filter based on the proposed FG-DVCC is presented in this paper to take the advantages of the properties of the proposed circuit. PSpice simulation results using 0.18 μm CMOS technology are included as well to validate the functionality of the proposed circuit.     

A model for the breakdown characteristics of p-channel MOS transistor protection devices

Gate controlled diodes, MOS transistors with grounded gate, source and substrate and gate controlled pnn + structures are compared when used as a protective input device on p-channel MOS integrated circuits. For this purpose two pulse techniques are developed which allow an accurate determination of the dynamic resistance by minimizing the walk-out of the breakdown voltage during the measurement. While the breakdown voltage does not differ much for the different types of devices, the dynamic resistance however is found to be considerably lower for the MOS transistor than for both other devices. For these low values the series resistance of the drain and source diffusion is shown to constitute already an important contribution. The lower dynamic resistance of MOST's can be ascribed to parasitic bipolar transistor operation during breakdown. The identification of this mechanism leads to a simple model for the MOS transistor in breakdown which has been experimentally verified and confirmed. Guidelines for the definition of the source diffusion for an optimal protective functioning can be obtained from this model.     

Body effect up- and down-conversion mixer circuits for low-voltage ultra-wideband operation

This article presents fully differential up- and down-conversion mixer circuits manufactured in a triple well 45 nm CMOS process for low-voltage Ultra-Wideband transmitter and receiver applications. The proposed circuits both employ the transistor bulk terminal for signal injection. While the down-conversion mixer uses the bulk for switching via threshold voltage modulation, the up-conversion mixer applies the baseband signal to the bulk, thereby implicitly incorporating the back-gate controlled current source of the MOS transistor. Both circuits offer resistive on-chip termination and DC coupled output buffering for measurement purposes. The down-conversion mixer features an input-referred compression point of −13.2 dBm and a maximum conversion gain of 9.4 dB at 2.5 GHz with the 3-dB corner frequency being beyond 10 GHz. The implemented up-conversion mixer offers a maximum conversion gain of −8.8 dB at 5.8 GHz together with an output-referred compression point of −9.7 dBm. The operational bandwidth ranges from 4.5 to 6.7 GHz. Both circuits operate at a low supply voltage of 1.1 V.     

Novel multiple-selected and multiple-valued memory design using negative differential resistance circuits suitable for standard SiGe-based BiCMOS process

A novel multiple-selected and multiple-valued memory (MSMVM) design using the negative differential resistance (NDR) circuits is demonstrated. The NDR circuits are made of Si-based metal-oxide-semiconductor field-effect-transistor (MOS) and SiGe-based heterojunction bipolar transistor (HBT). During suitably designing the parameters and connecting three MOS–HBT–NDR circuits, we can obtain the three-peak current–voltage (I–V) curves with different peak currents in the combined I–V characteristics. For the traditional resonant-tunneling-diode (RTD) memory circuit, one can only obtain four-valued memory states using a constant current source to bias the three-peak NDR circuit. However in this paper, we utilize two switch-controlled current sources to bias the three-peak NDR circuit at different current levels. By controlling the switches on and off alternatively, we can obtain the four-valued, three-valued, two-valued, and one-valued memory levels under the four different conditions. Our design is based on the standard 0.35 μm SiGe BiCMOS process.