Series resistance effects in semiconductor CV profiling

The effects of series resistance on semiconductor doping profiles obtained by conventional CV analysis are discussed, and it is shown that this resistance can cause extremely large errors in the profiles. It is demonstrated that the existence of such errors can be inferred from suitable RF phase angle measurements obtained during the CV profiling process, and that this information can be used to correct distorted profiles. A theoretical analysis and several computer simulations are presented in order to illustrate the nature of the problem and the methods by which accurate profiles can be obtained. All of the behavior predicted by computer simulations is verified by experimental examples.     

Source/drain metallization effects on the specific contact resistance of indium tin zinc oxide thin film transistors

We report on the specific contact resistance of interfaces between thin amorphous semiconductor Indium Tin Zinc Oxide (ITZO) channel layers and different source/drain (S/D) electrodes (Al, ITO, and Ni) in amorphous oxide thin film transistors (TFTs) at different channel lengths using a transmission line model. All the contacts showed linear current–voltage characteristics. The effects of different channel lengths (200–800 μm, step 200 μm) and the contact resistance on the performance of TFT devices are discussed in this work. The Al/ITZO TFT samples with the channel length of 200 μm showed metallic behavior with a linear drain current-gate voltage (I_D–V_G) curve due to the formation of a conducting channel layer. The specific contact resistance (ρ_C) at the source or drain contact decreases as the gate voltage is increased from 0 to 10 V. The devices fabricated with Ni S/D electrodes show the best TFT characteristics such as highest field effect mobility (16.09 cm²/V·s), ON/OFF current ratio (3.27×10⁶), lowest sub-threshold slope (0.10 V/dec) and specific contact resistance (8.62 Ω·cm² at V_G=0 V). This is found that the interfacial reaction between Al and a-ITZO semiconducting layer lead to the negative shift of threshold voltage. There is a trend that the specific contact resistance decreases with increasing the work function of S/D electrode. This result can be partially ascribed to better band alignment in the Ni/ITZO interface due to the work function of Ni (5.04–5.35 eV) and ITZO (5.00–6.10 eV) being somewhat similar.     

Mechanical processes in chemical-mechanical planarization: Plasticity effects in oxide thin films

The role of plastic behavior of normally brittle oxide films in controlling materials removal mechanisms in chemical-mechanical planarization (CMP) is discussed. Particular attention is given to how material removal mechanisms are sensitive to fundamental changes in surface materials properties. It is suggested that the synergism between chemical and mechanical effects in CMP can be framed in the context of an environmentally sensitive fracture process. The concept of “fracture” in the case of CMP, however it is argued, occurs at the nanometric or ultimately at the atomistic scale. This type of paradigm for chemical-mechanical planarization is developed through an analysis of the different types of materials behavior associated with surface changes where environment and mechanical effects are coupled.     

GaAs-MOS capacitor with native oxide film anodized in nonaqueous electrolyte

Anodic oxidation of GaAs in a new nonaqueous electrolyte and MOS characteristics are described. The anodic oxide film with specific resistivity of $\text{10}{}^{14}\text{–10}{}^{15}\text{Ω}\text{cm}$ and breakdown field strength of 2 × 10⁶ V/cm was grown at a rate of 22 Å/V for a current density of 0.5 mA/cm² in the electrolyte of a saturated ethylene glycol solution of potassium dichromate. A linear relationship between the oxide thickness and the forming voltage was maintained in spite of nonlinearity between the forming voltage and the anodization time. After a shorter time annealing for about 30 min than in an aqueous electrolyte, the new MOS capacitor shows improved interface properties with a small hysteresis and has a noticeable feature of sensitivity to light, and no hysteresis in the C-V curve was observed under light illumination of higher photon energy than about 1 eV.     

Geometric effects on the gate-controlled capacitor

The effect of p-n junction geometry on the capacitance-voltage (C-V) and conductance-voltage (G-V) characteristics of a gate-controlled Capacitor (GCC) is discussed. Three p-n junction geometries were studied; one was a circular structure and the remaining two were cross structures. It is concluded that the effective transit distances are decreased as the geometries of the junction become more complex.     

氮化硅薄膜MIM电容器的制备与性能研究

在被釉氧化铝陶瓷基片上,采用真空电阻蒸发法和等离子体增强化学气相沉积法制备了Au/NiCr电极薄膜及氮化硅(SiNx)介质薄膜,并对薄膜进行光刻图形化,制成了Au/NiCr/SiNx/Au/NiCr结构的MIM电容器。研究了所制电容器的介电性能、介温性能和I-V特性等电学性能。结果表明:所得MIM电容器具有很低的介电损耗(1MHz时tanδ为0.00192)及很高的电压稳定性;在–55～+150℃的范围内其1MHz时的电容温度系数为258×10–6/℃;另外,其I-V特性曲线显示出较好的对称性,漏电流密度较低,可承受较高的电压。     

Ceramic capacitor insulation resistance failures accelerated by low voltage

Ceramic capacitors failed insulation resistance at less than 1/10 th their rated voltage despite the fact that they had been subjected to "voltage conditioning" at twice the rated voltage for 100 h. Many failures recovered as the voltage was increased. Using special sectioning procedures, the failures were isolated to single ceramic plates; however, extensive analysis did not initially determine the cause of failure. Finally, the ceramic was ground from all four sides and an unexpected discovery was made: the plates could be peeled apart intact. This allowed dissection of the capacitor structure, completely exposing the shorted plates. Using the absorbed-current mode of the SEM, it was determined that the only leakage was through very small voids in the ceramic. Peeling the plates apart also provided the ability to see delaminations and other defects in three dimensions and to examine the electrodes and plate surfaces in minute detail. Based on this and related experiences, it is concluded that ceramic capacitors that fail at low voltage and recover or partially recover as the voltage is increased are fairly prevalent. Screening results indicate the need for special screening for ceramic capacitors intended for low-voltage applications.     

Realisation of grounded capacitor with operational amplifiers and resistance

A simple circuit is given for the simulation of a high-quality grounded capacitor. It uses only two operational amplifiers and one resistance. Experimental results are included.     

A study on electrochemical effects in external capacitor packages

Exposing semiconductor devices with external capacitors to harsh environmental conditions may lead to electrical failures with the formation of conductive paths. This paper presents examples of the analysis of modules with the purpose to understand the respective failure modes. Appropriate sample preparation, sensitive analytical methods like micro-X-ray fluorescence spectroscopy (μXRF), ToF-SIMS, SEM/EDX, X-ray-microscopy as well as micro computed X-ray-tomography (μCT) have been applied to identify the root causes of the electrical failures.As a main conclusion of these investigations, we found that electrolytes can easily penetrate thermoplastic overmold materials which are typically used by module manufacturers. This can lead to either reversible electrical failures which can be eliminated by drying or irreversible electrical failures because of material migration. The effective failure mode depends on mechanical and climate conditions inside the module which could not be simulated up to now under laboratory but only under application conditions.     

The investigation of DARC etch back in DRAM capacitor oxide mask opening

Opening the silicon oxide mask of a capacitor in dynamic random access memory is a critical process on a capacitive coupled plasma (CCP) etch tool.Three steps,dielectric anti-reflective coating (DARC) etch back,silicon oxide etch and strip,are contained.To acquire good performance,such as low leakage current and high capacitance,for further fabricating capacitors,we should firstly optimize DARC etch back.We developed some experiments,focusing on etch time and chemistry,to evalu-ate the profile of a silicon oxide mask,DARC remain and critical dimension.The result shows that etch back time should be con-trolled in the range from 50 to 60 s,based on the current equipment and condition.It will make B/T ratio higher than 70％ mean-while resolve the DARC remain issue.We also found that CH2F2 flow should be ～15 sccm to avoid reversed CD trend and keep in-line CD.     

Phototransients in anodic tantalum oxide thin films

Phototransients under radiation of 274 nm have been studied in anodic tantalum oxide thin films. The area under the phototransient curves, the relaxation time end the decay time are found U> decrease with the applied field. For short times ΔI αexp ( ? t/r) with τ decreasing with field, while for longer times thore is a departure from exponential behaviour. These photo transients may be due to the drift of photoexcited electrons under the action of an applied field end their subsequent retrapping.     

Compound barriers in thin oxide film diodes

High-frequency reverse bias measurements are made on sandwiched evaporated oxide films of tungsten and molybdenum. The linearity of the capacitance-voltage pilot gives an indication of Schottky-type barrier. The intercept and the n values obtained from the plot are used to calculate the thickness of the space charge region. It is concluded that a compound barrier exists at the interface.     

Monitoring plasma-process induced damage in thin oxide

Plasma etching and resist ashing processes cause current to flow through the thin oxide and the resultant plasma-induced damage can be simulated and modeled as damage produced by constant current electrical stress. The oxide charging current produced by plasma processing increases with the `antenna' size of the device structure. Oxide charge measurement such as CV or threshold voltage is a more sensitive technique for characterizing plasma-processing induced damage than oxide breakdown. The oxide charging current is collected only through the aluminum surfaces not covered by the photoresist during plasma processes. Although forming gas anneal can passivate the traps generated during plasma etching, subsequent Fowler-Nordheim stressing causes more traps to be generated in these devices than in devices that have not been through plasma etching. Using the measured charging current, the breakdown voltage distribution of oxides after plasma processes can be predicted accurately. Oxide shorts density of a single large test capacitor is found to be higher than that in a multiple of separated small capacitors having the same total oxide area. This would lead to overly pessimistic oxide defect data unless care is taken     

An evaluation of three simple scalable MIM capacitor models

This paper presents an evaluation of three different scalable metal-insulator-metal capacitor models for use in monolithic-microwave integrated-circuit design. The models, including one previously unpublished, are based on transmission-line theory and are easily scalable using only physical dimensions and constants. Comparisons to measured data for several device sizes, up to 45/spl deg/ in electrical length, show that the three models exhibit similar performance, with a mean deviation between models and S/sub 11/ measurements that is less than 3%.     

The effects of thermal nitridation conditions on the reliability of thin nitrided oxide films

MIS capacitors on n-type silicon substrate with thin oxide films thermally nitrided in NH3gas ambient at different temperatures and for different times have been fabricated. The effects of nitridation temperature and time on the properties of the thin nitrided oxide films have been examined and analyzed by using a constant current stress. It is found that the oxide films nitrided at 900°C exhibit much improved total charge to breakdown and interface trap generation if proper nitridation time is used. The superior characteristics of the fabricated nitrided oxide films using the proposed optimum conditions are suitable for existing CMOS/VLSI applications.     

Effect of the nitrous oxide plasma treatment on the MIM capacitor

We report the demonstration of near zero voltage coefficient of capacitance (VCC) by exposing the silicon nitride dielectric of the metal-insulator-metal capacitor (MIM) to nitrous oxide (N₂O) plasma. Oxidization in the N₂O plasma enhanced the hard breakdown field, whereby an excess of 9 MV/cm was achieved. In addition, low-temperature coefficient of capacitance (TCC) of < 20 ppm/K and high dielectric constant ⩾ 6.5 were preserved     

Low frequency noise in thin gate oxide MOSFETs

Low frequency, 1/f, noise of the drain current, I_D, fluctuations was measured on a series of Si MOSFETs with the gate oxide thickness, t_ox, varied from 25 to 40 Å by steps of 5 Å. The salient point of this work is a demonstration that, at sufficiently low I_D intensities, a mean low noise level in the MOSFETs is reduced as the gate oxide becomes thinner. This is explained assuming that the noise originates from the electron capture/release on Si/SiO₂ interface/border traps. The flat band voltage fluctuations, observable as noise, are linked then to the oxide charge fluctuations by a factor, that is inversely proportional to the gate capacitance, C_ox, and thus proportional to t_ox. At higher I_D, the results are more complicated, as the access resistance noise is also involved. We provide an interpretation of the ensemble of the data and show that the noise analysis can furnish quantitative estimates of several device characteristics. Device degradation and its consequences for the low frequency noise at higher current levels are also discussed.     

Electrical conduction in anodic tungsten oxide thin films

Thin films of tungsten oxide were prepared by anodic oxidation of 99.999% pure tungsten foils using an aqueous solution containing 0.4 M KNO₃ and 0.04 M HNO₃ as the electrolyte. Different films show different colours. The current-voltage characteristics are of the log I- V^1/2 type. These characteristics can be interpreted in terms of the Poole—Frenkel type of conduction mechanism. The colours may be duo to the incorporation of H⁺ ions and the formation of HxWO₃ during the anodizing process.     

The effect of native oxide on thin gate oxide integrity

We have studied the effect of native oxide on thin gate oxide integrity. Much improved leakage current of gate oxide can be obtained by in situ desorbing the native oxide using HF-vapor treated and H₂ baked processes. Furthermore, an extremely sharp interface between oxide and Si is obtained, and good oxide reliability is achieved even under a high current density stress of 11 A/cm² and a large charge injection of 7.9×10⁴ C/cm². The presence of native oxide will increase the interface roughness, gate oxide leakage current and stress-induced hole traps