Fast and accurate quasi-three-dimensional capacitance determinationof multilayer VLSI interconnects

A new fast and accurate capacitance determination methodology for intricate multilayer VLSI interconnects is presented. Since a multilayer interconnect structure is too complicated to be directly tractable, it is simplified by investigating charge distributions within the system. The quasi-three-dimensional (3-D) capacitances of the structure are then determined by combining a set of solid-ground-based two-dimensional (2-D) capacitances and shielding effects that can be independently calculated from the simplified structure. The shielding effects due to the neighboring lines of a line can be analytically determined from the given layout dimensions. The solid-ground-based 2-D capacitances can also be quickly computed from the simplified structure. Thus, the proposed capacitance determination methodology is much more cost-efficient than conventional 3-D-based methods. It is shown that the calculated quasi-3-D capacitances have excellent agreement with 3-D field-solver-based results within 5% error     

Interconnect capacitance characterization using charge-injection-induced error-free (CIEF) charge-based capacitance measurement (CBCM)

In this work, we describe a novel operation of charge-injection-induced error-free charge-based capacitance measurement (CIEF CBCM) method. This method has the simplest test structure among various CBCM methods by using only one N/PMOS pair. CIEF CBCM has the advantage of being free from charge-injection-induced errors and of efficient layout area usage. It is very suitable for industrial applications for large amounts of accurate capacitance characterizations with a limited layout area. Besides, CIEF CBCM is also implemented for investigating the impact of floating dummy metal fills on interconnect capacitance directly from silicon data.     

Crosstalk-based capacitance measurements: theory and applications

Geometry scaling increases the relative effect of coupling capacitances on performance, power, and noise so that they need to be carefully taken into account during process development, characterization, and monitoring. In the last decade, charge-based capacitance measurements (CBCMs) have been widely used to estimate on-chip wiring and coupling capacitances because of their accuracy and simplicity. We provide a thorough theoretical and experimental study of CBCMs applied to the selective extraction of cross-coupling capacitances. We take a historical perspective starting from the original CBCM approach proposed by Chen in 1996, and we present a new technique for crosstalk-based capacitance measurements (CTCMs). CTCMs improve the accuracy and usability of CBCMs while reducing the complexity of the test structures. We present the theory of CTCM, we provide experimental results demonstrating its improved accuracy, and we discuss its application to a wide range of process monitoring and testing tasks. Experimental results are used throughout the paper to support the discussion.     

A novel simple CBCM method free from charge injection-induced errors

In this letter, we propose a charge injection-induced error-free charge-based capacitance measurement method (CIEF CBCM). This novel method uses only one n/pMOS pair to characterize the small interconnect capacitance. It has the simplest test structure among various CBCM methods. More importantly, the CIEF CBCM method is free from the errors induced by charge injection. Besides, only one additional pad is needed for one additional capacitor under the test by this method, and it is the most efficient method for process characterization and monitoring.     

A multilevel parasitic interconnect capacitance modeling andextraction for reliable VLSI on-chip clock delay evaluation

This paper describes fringing and coupling interconnect capacitance models which include the nonlinear second-order effects of field interactions among multilevel parasitic interconnects for accurate circuit simulations. They are fitted well with numerical solutions by using a Poisson equation solver. A reliable parasitic distributed resistance-inductance-capacitance (RLC) extraction method is identified by using the solver with the bounded local three-dimensional (3-D) numerical analysis to reduce excessive central processing unit (CPU) time compared to full 3-D numerical simulation. We investigate the impact of input slew variations on the traversal clock delay within the slow ramp region of the driver gate as well as in the extracted parasitic interconnect networks. Input slew is found to be a dominant factor affecting clock delay sensitivity. In addition, we use indirect on-chip electron beam probing to confirm that the simulated clock delays are in reasonable agreement with the measured delays     

An on-chip, interconnect capacitance characterization method withsub-femto-farad resolution

A simple, accurate method of measuring interconnect capacitances is presented. The test structure has excellent resolution, needs only DC measurements, and is compact enough for scribe-line implementation. These qualities make it suitable for measurement-based, interconnect capacitance characterization in a comparable fashion to current characterization efforts for MOSFET devices. The entire characterization scheme is demonstrated for a production 0.5 μm, three-level metal technology. The method not only provides an accurate assessment of actual capacitance variation but provides valuable feedback on the variability of physical parameters such as interlevel dielectric (ILD) thickness and drawn width reductions for process control as well     

Measurement and characterization of multilayered interconnectcapacitance for deep-submicron VLSI technology

This paper presents the measurement and characterization of multilayered interconnect capacitances for a 0.35-μm CMOS logic technology, which become a critical circuit limitation to high performance VLSI design. To measure multilayered capacitances of nonstacked, stacked, and orthogonally crossing interconnect lines, new test structures and measurement methods are presented. The measured interconnect capacitances were employed to evaluate and calibrate TCAD tools for the simulation of high-speed interconnect technologies. This study shows that the calibration method considerably improves the accuracy of simulation results compared with measured results     

Multilevel metal capacitance models for CAD design synthesissystems

An empirical model for multilevel interconnect capacitance is presented. This is the first model that allows designers to compute capacitances of arbitrary complex metal geometries. Such flexibility is achieved by a novel strategy of constructing complex geometries from simple primitive cells. Agreement with accurate simulations and measurements is within 8% over an extensive range of dimensions     

SET logic driving capability and its enhancement in 3-D integrated SET–CMOS circuit

The driving capability of a single-electron transistor (SET) circuit is sensitive to the load and interconnects. We discuss about improving the performance of a SET logic in hybrid SET–CMOS circuit by parameter variation and circuit architecture along with its simulation results. With an intention of studying the SET logic drivability in a SET-only circuit, we examined a circuit composed of 2¹³ SET inverters with its interconnect effect in a 3-D CMOS IC. The schematic of the simulation is based on fabrication model of this large circuit along with interlayer and coupling capacitances of its metallization. The simulation results for delay, bandwidth and power validate the efficiency of a SET circuit.     

Domain decomposition approach for capacitance computation ofnonorthogonal interconnect structures

In this paper we apply the domain decomposition approach in conjunction with the finite difference (FD) method to compute efficiently the capacitance matrixes of crossovers and via type of interconnect structures, formed by traces that are nonorthogonal in general. In the past we have applied the FD method, in conjunction with the perfectly matched layer (PML) and the impedance boundary condition for FD mesh truncation, to compute the capacitances of orthogonal interconnect configurations. In this work we extend the above approach to apply to more general geometries, e.g., vias and crossovers with arbitrary angles. The paper presents some representative numerical results and examines the convergence and efficiency issues of the proposed algorithm     

Feature-scale Process Simulation and accurate capacitance extraction for the backend of a 100-nm aluminum/TEOS Process

One of the challenges that technology computer-aided design must meet currently is the analysis of the performance of groups of components, interconnects, and, generally speaking, large parts of the IC. This enables predictions that the simulation of single components cannot achieve. In this paper, we focus on the simulation of backend processes, interconnect capacitances, and time delays. The simulation flows start from the blank wafer surface and result in device information for the circuit designer usable from within SPICE. In order to join topography and backend simulations, deposition, etching, and chemical mechanical planarization processes in the various metal lines are used to build up the backend stack, starting from the flat wafer surface. Depending on metal combination, line-to-line space, and line width, thousands of simulations are required whose results are stored in a database. Finally, we present simulation results for the backend of a 100-nm process, where the influence of void formation between metal lines profoundly impacts the performance of the whole interconnect stack, consisting of aluminum metal lines, and titanium nitride local interconnects. Scanning electron microscope images of test structures are compared to topography simulations, and very good agreement is found. Moreover, charge-based capacitance measurements were carried out to validate the capacitance extraction, and it was found that the error is smaller than four percent. These simulations assist the consistent fabrication of voids, which is economically advantageous compared to low-/spl kappa/ materials, which suffer from integration problems.     

An efficient solver for the three-dimensional capacitance of theinterconnects in high speed digital circuit by the multiresolutionmethod of moments

The computation of the equivalent capacitances for three-dimensional (3-D) interconnects features large memory usage and long computing time. In this paper, a matrix sparsification approach based on multiresolution representation is applied with the method of moments (MoM) to calculate 3-D capacitances of interconnects in a layered media. Instead of direct expansion of the charge distribution by the orthogonal wavelet basis functions, the large full matrix resulting from discretization of the integral equations is taken as a discrete image and sparsified by two-dimensional (2-D) multiresolution representations. The inverse of the obtained sparse matrix is efficiently implemented by Schultz's iterative approach. Several numerical examples are given and the results obtained show that the proposed method significantly sparsifies the matrix equation and the capacitance parameters computed by the matrix equation with high sparsity agree well with the results of other reports and those computed by an established capacitance extractor FASTCAP     

Analysis of the gate-source/drain capacitance behavior of a narrow-channel FD SOI NMOS device considering the 3-D fringing capacitances using 3-D simulation

This paper reports an analysis of the gate-source/drain capacitance behavior of a narrow-channel fully depleted (FD) silicon-on-insulator (SOI) NMOS device considering the three-dimensional (3-D) fringing capacitances. Based on the 3-D simulation results, when the width of the FD SOI NMOS device is scaled down to 0.05 /spl mu/m, the inner-sidewall-oxide fringing capacitance (C/sub FIS/), due to the fringing electric field at the edge of the mesa-isolated structure of the FD SOI NMOS device biased at V/sub G/=0.3 V and V/sub D/=1 V, is the second largest contributor to the gate-source capacitance (C/sub GS/). Thus, when using nanometer CMOS devices with a channel width smaller than 0.1 /spl mu/m, C/sub FIS/ cannot be overlooked for modeling gate-source/drain capacitance (C/sub GS//C/sub GD/).     

Planar Microspring—A Novel Compliant Chip-to-Package Interconnect for Wafer-Level Packaging

In this paper, a novel compliant chip-to-package interconnect, planar microspring, is presented in terms of design consideration, wafer-level fabrication process and mechanical characterization. Several spring designs have been evaluated, and results indicate that a $J$-shaped spring design produces a combination of high 3-D compliances and acceptable electrical parasitics. Further, numerical analyses on the $J$ -shaped microspring interconnect examined the dependence of mechanical and electrical performance upon geometry parameters. A wafer-level fabrication flow combining complementary metal oxide semiconductor (CMOS) back-end-of-line (BEOL) process and 3-D surface micromachining technique has been successfully implemented to create planar microspring interconnect prototypes with a fine pitch (100 $mu{rm m}$ ). The mechanical robustness of the prototype interconnects have been evaluated by nanoindentation. Finally, high-frequency electrical simulation suggested that the interconnect application can be extended up to $sim$35 GHz without significant power loss.      

A capacitance model for GaAs MESFETs

A capacitance model for a GaAs MESFET suitable for implementation in the circuit analysis program SPICE is presented. The model consists of nonlinear capacitances that are a function of two voltages. Such a model gives rise to ordinary nonlinear capacitances and transcapacitances. The placement of these elements in the Y matrix is shown. The empirical equations for the gate charge of a GaAs MESFET given provide an accurate SPICE model for the gate charge and capacitances of a MESFET. A comparison of measured capacitance values with the modeled values gives close enough agreement for circuit simulation purposes     

Tradeoff between interconnect capacitance and RC delay variationsinduced by process fluctuations

This paper describes the influence of the process fluctuations such as the critical dimension (CD) variation upon the interconnect capacitance C and RC delay. It is found that there is a tradeoff between C and RC delay variations because of the fringing capacitance. An interconnect design guideline to reduce C and/or RC delay variations is proposed. Also, C and RC delay variations for Cu interconnect are discussed     

A New Capacitance-to-Frequency Converter for On-Chip Capacitance Measurement and Calibration in CMOS Technology

In this paper, a new capacitance-to-frequency converter using a charge-based capacitance measurement (CBCM) circuit is proposed for on-chip capacitance measurement and calibration. As compared to conventional capacitor measurement circuits, the proposed technique is able to represent the capacitance in term of the frequency so that the variations can be easily handled in measurement or calibration circuits. Due to its simplicity, the proposed technique is able to achieve high accuracy and flexibility with small silicon area. Designed using standard 180 nm CMOS technology, the core circuit occupies less than 50 μm × 50 μm while consuming less than 60 μW at an input frequency of 10 MHz. Post-layout simulation shows that the circuit exhibits less than 3 % measurement errors for fF to pF capacitances while the functionality has been significantly improved.     

Three-Dimensional System-in-Package Using Stacked Silicon Platform Technology

In this paper, a novel method of fabricating three–dimensional (3-D) system-in-package (SiP) using a silicon carrier that can integrate known good dice with an integrated cooling solution is presented. The backbone of this stacked module is the fabrication of a silicon carrier with through-hole conductive interconnects. The design, process, and assembly to fabricate silicon through-hole interconnect using a wet silicon etching method is discussed in this paper. The process optimization to fabricate silicon carriers with solder through-hole interconnect within the design tolerance has been achieved. The design and modeling methodology to optimize the package in terms of electrical aspects of the stacked module is carried out to achieve less interconnect parasitics. An integrated cooling solution for 3-D stacked modules using single-phase and two-phase cooling solutions is also demonstrated for high-power applications. Known good thin flip-chip devices with daisy chain are fabricated and attached to the silicon carrier by flip-chip processes making it a known good carrier after electrical testing. Individual known good carriers are vertically integrated to form 3-D SiP.     

A set of analytic formulas for capacitance of VLSI interconnects oftrapezium shape

In VLSI timing analysis, a quick and accurate extraction of interconnect line to line and line to ground capacitance is very important. This paper presents a set of analytic formulas for the capacitance of one, two, and three trapezium interconnect lines over a ground plane which show better than 7% agreement with the capacitance values from the numerical simulation     

Stochastic interconnect modeling, power trends, and performancecharacterization of 3-D circuits

Three-dimensional (3-D) technology promises higher integration density and lower interconnection complexity and delay. At present, however, not much work on circuit applications has been done due to lack of insight into 3-D circuit architecture and performance. One of the purposes of realizing 3-D integration is to reduce the interconnect complexity and delay of two dimensions (2-D), which are widely considered as the barriers to continued performance gains in future technology generations. Thus, understanding the interconnect and its related issues, such as the impact on circuit performance, is key to 3-D circuit applications. In this paper, we present a stochastic 3-D interconnect model and study the impact of 3-D integration on circuit performance and power consumption. To model 3-D interconnect, we divide 3-D wires into two parts (horizontal wires and vertical wires) and derive their stochastic distributions. Based on those distributions, we estimate the delay distribution. We show that 3-D structures effectively reduce the number of long delay nets, significantly reduce the number of repeaters, and dramatically improve circuit performance. With 3-D integration, circuits can be clocked at frequencies much higher (double or even triple) than 2-D