Multivalued dynamic circuits

A new family of multivalued logic circuits is presented. These circuits exhibit some appealing features: they are the first MV dynamic operators reported in the literature, they implement the Vranesic-Smith-Lee algebra (which is specially suited for arithmetic operations), and their performance has been found to be similar to binary counterparts by simulation.     

Analysis of dynamic characteristics of process of designing analogue circuits

The process of designing analogue circuits is formulated as a controlled dynamic system. For analysis of such system’s properties it is suggested to use the concept of Lyapunov’s function for a dynamic system. Various forms of Lyapunov’s function are suggested. Analyzing the behavior of Lyapunov’s function and its first derivative allowed to determine significant correlation between this function’s properties and processor time used to design the circuit. Numerical results prove the possibility of forecasting the behavior of various designing strategies and processor time based on the properties of Lyapunov’s function for the process of designing the circuit.     

Timing verification of dynamic circuits

A complete set of rules is presented for timing verification of domino-style dynamic circuits. These rules include identification of dynamic nodes, generation of accurate timing constraints based on the operating environment of the gate and verification as an enhanced part of a complete timing verification process. This methodology has been implemented in a new static timing verifier and used to verify microprocessor circuits     

Design and synthesis of dynamic circuits

Dynamic circuits are widely used in today's high-performance microprocessors for obtaining timing goals that are not possible using static CMOS circuits. Currently, no commercial tools are able to synthesize dynamic circuits and therefore their design is either completely done by hand or aided by proprietary in-house design tools. This paper describes methodologies and tools for the design and synthesis of dynamic circuits, including general monotonic circuits, which consist of alternating low-skew and high-skew logic gates that may both contain functionality. Synthesis results show standard domino, dynamic-static domino, monotonic static CMOS, zipper CMOS, and footless domino and clock-delayed domino circuits to have average speed improvements of 1.57, 1.66, 1.67, 1.47, 1.71, and 1.60 times over static CMOS, respectively.     

Noise in digital dynamic CMOS circuits

Dynamic logic is an attractive circuit technique giving reduced area and increased speed for CMOS circuits. Static logic has a major advantage: its superior noise margins. To be able to choose between a static and a dynamic implementation of a design, we need to know the requirements for dynamic logic. Here we try to identify possible errors, estimate the limits and discuss some possible solutions when considering noise in dynamic circuits     

Current testing in dynamic CMOS circuits

Current testing of dynamic CMOS integrated circuits with single phase clock is investigated. The analysis is performed on a single phase stage dynamic module in the presence of internal bridging defects of low resistance. These defects produce intermediate voltage levels which cause difficulties to the logic testing methods based on voltage level comparison. It is shown that current testing may be an effective complement to the usual logic methods. Theoretical bounds on the coverage of single internal bridges obtainable by current testing are given.     

Neural-based dynamic modeling of nonlinear microwave circuits

A neural network formulation for modeling nonlinear microwave circuits is achieved in the most desirable format, i.e., continuous time-domain dynamic system format. The proposed dynamic neural network (DNN) model can be developed directly from input-output data without having to rely on internal details of the circuit. An algorithm is developed to train the model with time or frequency domain information. Efficient representations of the model are proposed for convenient incorporation of the DNN into high-level circuit simulation. Compared to existing neural-based methods, the DNN retains or enhances the neural modeling speed and accuracy capabilities, and provides additional flexibility in handling diverse needs of nonlinear microwave simulation, e.g., time- and frequency-domain applications, single-tone and multitone simulations. Examples of dynamic modeling of amplifiers, mixer, and their use in system simulation are presented.     

Realistic scalability of noise in dynamic circuits

The usage of noise-sensitive dynamic circuits has become commonplace due to speed and area requirements, making the noise issue even more prominent. This paper focuses on the trends of coupling and its effects on dynamic circuits. It presents closed form analytical solutions for noise, as well as noise tolerance metrics for dynamic circuits. These solutions are within 5% of dynamic simulations. It is shown that not all scaling trends are negative for noise, and that the scaling down of supply voltage and increasing frequency, help improve certain aspects of the noise immunity of dynamic circuits. Most of the works treated the noise immunity and the noise content separately. This paper introduces an analysis of noise scalability by looking at the noise immunity and the noise content simultaneously.     

Static and dynamic noise margins of logic circuits

Explaining four basic types of noise, and by showing the various methods, together with boundary conditions, which can be used to find the worst case noise margins. A flip-flop setup is advised which can be used for measurements and computer simulations, both for static and dynamic noise margins. Also configurations with fan-in and fan-out larger than 1 can be handled with this flip-flop method. In general, it is found that the dynamic noise margins increase for shorter noise pulses; a first-order explanation of this phenomenon is given. Also, energy noise margins are considered. The theoretical considerations are completed with computer simulations and measurements of the static and dynamic noise margins of integrated Schottky logic (ISL), as an example.     

MOS capacitor pull-up circuits for high-speed dynamic logic

The use of an MOS capacitor as an integrated load element in dynamic inverters is reviewed and a particular approach (direct cascading) to its application is demonstrated. Experimental n-channel capacitor pull-up shift registers are demonstrated to operate with multiphase clocks at frequencies up to 34.5 MHz, which is about twice the limit of conventional MOS dynamic circuits fabricated with the same Si-gate process. A substrate bias is used to eliminate minority carrier injection which was previously reported to limit the high frequency performance. Possible applications of this circuit are discussed.     

Temperature-dependent dynamic triggering characteristics of SCR-type ESD protection circuits

Experimental analysis of the dynamic characteristics of various silicon-controlled rectifier (SCR)-type ESD protection circuits at various temperatures has been carried out. These circuits include MOSFET-trigger SCR (MTSCR), diode-chain-trigger SCR (DCTSCR), low-voltage zener diode trigger SCR (ZDSCR), low-voltage trigger SCR (LVTSCR) and gate-coupled low-voltage trigger SCR (GCSCR) circuits. The static trigger voltage increases with temperature if the SCR uses the breakdown trigger mechanism, otherwise it decreases with temperature. The peak pad voltages for the MTSCR and DCTSCR subjected to a pulse-like ESD stress decrease with increasing temperature, while those of GCSCR and LVTSCR are relatively insensitive to temperature.     

Feedback supported isolation structure for blocking of minority leakage carriers in power integrated circuits

A combination of two conventional junction isolation structures is used to produce a device, which significantly improves the blocking of minority carriers injected into the substrate of a power IC due to switching of an inductive load. Simulation results show that the connection scheme employed greatly enhances the efficiency of the structures. A substrate current reduction of up to four orders of magnitude compared to conventional junction isolation structures is achieved. The significance of doping profiles in the p-sinker region is evaluated.     

Low-voltage dynamic biasing technique for CMOS class ABcurrent-mode circuits

A novel dynamic biasing technique that can be used for the design of CMOS class AB current-mode circuits is presented. The approach takes advantage of the switched capacitor (SC) technique and enables extremely low voltage operations. An application of the proposed technique to the design of a basic input stage is given and simulations showing good agreement with the expected results are provided     

Ultralow-power GaAs MESFET MSI circuits using two-phase dynamic FETlogic

Two-phase dynamic FET logic (TDFL) gates are used in GaAs MESFET MSI circuits to implement very low power 4-b ripple carry adders and a variable modulus (2 to 31) prescaler. Operation of the adders is demonstrated at 500 MHz with an associated power dissipation of less than 1.0 mW and at 750 MHz with P_d=1.7 mW. The prescaler, which contains 166 TDFL gates and 79 static gates, is shown to operate up to 850 MHz with an associated power dissipation of 9.2 mW from its 1.0-V supply. The operation of the adders and prescalers demonstrates the use of three- and four-input TDFL gates and a completely dynamic TDFL XNOR gate. The TDFL gates in these circuits dissipate only from 14 to 20 nW/MHz     

A stuck fault model for dynamic CMOS combinational circuits

This paper utilizes the logic transistor function (LTF), that was devised to model the static CMOS combinational circuits at the transistor and logic level, to model the dynamic CMOS combinational circuits. The LTF is a Boolean representation of the circuit output in terms of its input variables and its transistor topology. The LTF is automatically generated using the path algebra technique. The faulty behavior of the circuit can be obtained from the fault-free LTF using a systematic procedure. The model assumes the following logic values (0, 1, I, M), where I, and M imply an indeterminate logical value, and a memory element, respectively. The model is found to be efficient in describing a cluster of dynamic CMOS circuits at both the fault-free and faulty modes of operation. Both single and multiple transistor stuck faults are precisely described using this model. The classical stuck-at and non classical stuck open and short faults are analyzed. A systematic procedure to produce the fault-free and faulty LTFs for different implementations of the dynamic CMOS combinational circuits is presented.     

Analysis of imperfectly defined circuits

The use of nodal analysis, coupled with a Volterra-integral formulation for nonlinear circuits, often enables a solution to be found to analysis problems that, because they contain elements that cannot be modelled, and for which only numerical data are available, are intractable by other known techniques.     

绝热无比型动态触发器和同步时序电路综合

该文从电路三要素理论出发研究低功耗电路，定量描述绝热无比型动态记忆电路。绝热无比型动态触发器利用电容接收和保存信息，避免目前绝热电路中电容上的信息得而复失的现象，其中绝热D和T'触发器只用6管，带‘与或非’输入的绝热D触发器只用9管。在上述理论基础上该文提出绝热无比型动态同步时序电路综合方法，用此法设计出绝热5421BCD码十进制计数器，仅用32管，总功耗小于一个PAL－2N四位二进制计数器的功耗，计算机模拟验证该文方法正确。     

High performance low power CMOS dynamic logic for arithmetic circuits

This paper presents the design of high performance and low power arithmetic circuits using a new CMOS dynamic logic family, and analyzes its sensitivity against technology parameters for practical applications. The proposed dynamic logic family allows for a partial evaluation in a computational block before its input signals are valid, and quickly performs a final evaluation as soon as the inputs arrive. The proposed dynamic logic family is well suited to arithmetic circuits where the critical path is made of a large cascade of inverting gates. Furthermore, circuits based on the proposed concept perform better in high fanout and high switching frequencies due to both lower delay and dynamic power consumption. Experimental results, for practical circuits, demonstrate that low power feature of the propose dynamic logic provides for smaller propagation time delay (3.5 times), lower energy consumption (55%), and similar combined delay, power consumption and active area product (only 8% higher), while exhibiting lower sensitivity to power supply, temperature, capacitive load and process variations than the dynamic domino CMOS technologies.     

基于动态逻辑的MPRM电路低功耗优化设计

n个输入变量的逻辑函数有3n种不同的MPRM(Mixed-Polarity Reed-Muller)表达式,其对应电路的功耗和面积不尽相同。本文通过对CMOS电路功耗和动态逻辑MPRM电路低功耗分解方法的分析,建立MPRM电路功耗和面积估计模型,而后提出一种基于动态逻辑的MPRM电路快速低功耗分解算法。在此基础上,针对中小规模和大规模MPRM电路,结合列表转换技术,分别将穷尽搜索算法和遗传算法应用于基于动态逻辑的MPRM电路低功耗优化设计中。通过对MCNC和ISCAS基准电路测试表明:与Boolean电路和FPRM(Fixed-Polarity Reed-Muller)电路相比,中小规模MPRM电路的功耗平均节省80.65%和50.98%,大规模MRPM电路的功耗平均节省69.17%和46.61%。     

Complementary dynamic m.o.s. logic circuits

Allowing both p and n channel groups of transistors to be blocked between transitions of c.m.o.s. gates leads to complementary dynamic m.o.s. circuits which, in many cases, are significantly less complex than their static counterparts. The value of the concept and a method of synthesis are demonstrated with a practical example. Systematic application to frequency dividers yields very simple new structures.