A 5.8-ns 256-Kb BiCMOS TTL SRAM with T-Shaped bit line architecture

Presents a new bit line architecture named T-shaped bit line architecture (TSBA), which is suitable for high speed, high density, and/or large bit-wide configuration SRAMs. TSBA, utilizing orthogonal complimentary bit lines in parallel with the word lines, is the solution to bit line pitch constraint for direct bipolar column sensing. This TSBA is applied to a 256-Kb SRAM with a typical access time of 5.8 ns. To achieve access times below 6 ns, this SRAM employs a bipolar Darlington column sense amplifier, a hierarchical column decoding scheme, a data bus shielding layout combined with TSBA, and a 0.8-μm BiCMOS technology     

一种面向可容错应用的低功耗SRAM架构

提出了一种面向可容错应用的低功耗SRAM架构。通过对输入数据进行预编码,提出的SRAM架构实现了以较小的精度损失降低SRAM电路功耗。设计了一种单端的8管SRAM单元。该8管单元采用读缓冲结构,提升了读稳定性。采用打破反馈环技术,提升了写能力。以该8管单元作为存储单元的近似SRAM电路能够在超低压下稳定工作。在40 nm CMOS工艺下对电路进行仿真。结果表明,该8管单元具有良好的稳定性和极低的功耗。因此,以该8管单元作为存储单元的近似SRAM电路具有非常低的功耗。在0.5 V电源电压和相同工作频率下,该近似SRAM电路的功耗比采用传统6管单元的SRAM电路功耗降低了59.86%。     

A low-power SRAM using hierarchical bit line and local sense amplifiers

This paper proposes a low power SRAM using hierarchical bit line and local sense amplifiers (HBLSA-SRAM). It reduces both capacitance and write swing voltage of bit lines by using the hierarchical bit line composed of a bit line and sub-bit lines with local sense amplifiers. The HBLSA-SRAM reduces the write power consumption in bit lines without noise margin degradation by applying a low swing signal to the high capacitive bit line and by applying a full swing signal to the low capacitive sub-bit line. The HBLSA-SRAM reduces the swing voltage of bit lines to V/sub DD//10 for both read and write. It saves 34% of the write power compared to the conventional SRAM. An SRAM chip with 8 K/spl times/32 bits is fabricated in a 0.25-/spl mu/m CMOS process. It consumes 26 mW read power and 28 mW write power at 200 MHz with 2.5 V.     

A 0.7 V Single-Supply SRAM With 0.495 $mu$m$^{2}$ Cell in 65 nm Technology Utilizing Self-Write-Back Sense Amplifier and Cascaded Bit Line Scheme

We proposed a novel SRAM architecture with a high-density cell in low-supply-voltage operation. A self-write-back sense amplifier realizes cell failure rate improvement by more than two orders of magnitude at 0.6 V. A cascaded bit line scheme saves additional process cost for hierarchical bit line layer. A test chip with 256 kb SRAM utilizing 0.495 $mu$ m$^{2}$ cell in 65 nm CMOS technology demonstrated 0.7 V single-supply operation.      

Hybrid crossbar architecture for a memristor based cache

This paper describes a new memristor crossbar architecture that is proposed for use in a high density cache design. This design has less than 10% of the write energy consumption than a simple memristor crossbar. Also, it has up to 3 times the bit density of an STT-MRAM system and up to 11 times the bit density of an SRAM architecture. The proposed architecture is analyzed using a detailed SPICE analysis that accounts for the resistance of the wires in the memristor structure. Additionally, the memristor model used in this work has been matched to specific device characterization data to provide accurate results in terms of energy, area, and timing. The proposed memory system was analyzed by modeling two different devices that vary in resistance range and switching time. This system does not require that the memristor devices have inherent diode effects which limit alternate current paths. Therefore this system is capable of utilizing a much broader class of devices.An architectural analysis has also been completed that shows how the memory system may perform as a cache memory. A hybrid cache structure was used to alleviate the long write latencies of memristor devices. This approach consisted of the tag array being made of SRAM cells while the data array was made of the memristor circuit proposed. This hybrid scheme allows multiple reads and writes to concurrently access different sub-arrays within a cache. The performance of these novel memristor based caches was compared to SRAM and STT-MRAM based caches through detailed simulations. The results show that the memristor caches are denser and allow better performance along with lower system power when compared to the STT-MRAM and SRAM caches.     

Characterization of a Novel Nine-Transistor SRAM Cell

Data stability of SRAM cells has become an important issue with the scaling of CMOS technology. Memory banks are also important sources of leakage since the majority of transistors are utilized for on-chip caches in today's high performance microprocessors. A new nine-transistor (9T) SRAM cell is proposed in this paper for simultaneously reducing leakage power and enhancing data stability. The proposed 9T SRAM cell completely isolates the data from the bit lines during a read operation. The read static-noise-margin of the proposed circuit is thereby enhanced by 2 X as compared to a conventional six-transistor (6T) SRAM cell. The idle 9T SRAM cells are placed into a super cutoff sleep mode, thereby reducing the leakage power consumption by 22.9% as compared to the standard 6T SRAM cells in a 65-nm CMOS technology. The leakage power reduction and read stability enhancement provided with the new circuit technique are also verified under process parameter variations.     

一种基于时钟抽取偏置电压技术的存储器位线

基于一种新型时钟延时单元,设计了一种片上存储器的位线。在不增加版图面积的前提下,通过周期性地改变保持管的衬底偏置电压,减小了短路功耗、泄漏功耗和延迟时间,同时增加了电路的抗工艺波动能力。在SMIC 65 nm工艺下,完成了传统位线、改进后的位线以及静态随机存取存储器(SRAM)的设计。仿真结果表明,在1 GHz时钟频率下,改进后的两种位线与传统位线相比,功耗延迟积分别减小了19.1%和15.9%。最后,通过蒙特卡洛分析可知,改进后的位线相比于传统位线具有较强的抗工艺波动能力,即功耗延迟积的方差减小了97.1%。     

Low-power embedded SRAM with the current-mode write technique

In the traditional current-mode SRAMs, only the read operation is performed in the current mode. In this paper, we propose to use the current-mode technique in both the read and write operations. Due to the current mode operation, voltage swings at bit lines and data lines are kept very small during both read and write. Then, the ac power dissipation of bit lines and data lines, which is proportional to the voltage swing, can be significantly saved. A new current-mode 128×8 SRAM has been designed based on a 0.6 μm CMOS technology, and the new SRAM consumes only 30% of the power of an SRAM with current-mode read but voltage mode write operations. Besides a test chip for the new SRAM, it has also been embedded in an 8-bit 1.1-controller. Experimental results show good agreement with the simulation results and prove the feasibility of the new technique     

Robust TFET SRAM cell for ultra-low power IoT applications

Design of ultra-low power SRAM with robust operation for Internet of Thing (IoT) sensor node is a new challenge. In this work, a novel 9T TFET based SRAM bit cell is proposed. The analysis and simulation results demonstrate that the proposed cell eliminates read disturb issue and outperforms the state-of-the-art 9T TFET bit cell in terms of static and dynamic write performance. The presented circuit topology incorporates power cut-off and write ‘0’ only technique to enhance the write performance. The proposed cell exhibits 1.15× higher write margin (WM), 25% lower write delay, consumes 73% (57%) lower write (average) energy, 7% smaller standby leakage power measured at V_DD = 0.3 V. The proposed cell also shows significant improvement in the read/write performance as compared with existing 7T and 8T TFET cells. Our proposed cell also eliminates half-select disturb issue to make it suitable for bit-interleaving architecture that is a must for enhanced soft error immunity.     

Low-Power Cache Design Using 7T SRAM Cell

On-chip cache consumes a large percentage of the whole chip area and expected to increase in advanced technologies. Charging/discharging large bit lines capacitance represents a large portion of power consumption during a write operation. We propose a novel write mechanism which depends only on one of the two bit lines to perform a write operation. Therefore, the proposed 7T SRAM cell reduces the activity factor of discharging the bit line pair to perform a write operation. Experimental results using HSPICE simulation shows that the write power saving is at least 49%. Both read delay and static noise margin are maintained after carefully sizing the cell transistors     

Design and process variation analysis of CNTFET-based ternary memory cells

Two novel ternary CNTFET-based SRAM cells are proposed in this paper. The first proposed CNTFET SRAM uses additional CNTFETs to sink the bit lines to ground; its operation is nearly independent of the ternary values. The second cell utilizes the traditional voltage controller (or supply) of a binary SRAM in a ternary SRAM; it consists of adding two CNTFETs to the first proposed cell. CNTFET features (such as sizing and density) and performance metrics (such as SNM and PDP) and write/read times are considered and assessed in detail. The impact of different features (such as chirality and CNT density) is also analyzed with respect to the operations of the memory cells. The effects of different process variations (such as lithography and density/number of CNTs) are extensively evaluated with respect to performance metrics. In nearly all cases, the proposed cells outperform existing CNTFET-based cells by showing a small standard deviation in the simulated memory circuits.     

ProTaR: An Infrastructure IP for Repairing RAMs in System-on-Chips

Complex system-on-a-chip (SOC) designs usually consist of many memory cores. Efficient yield-enhancement techniques thus are required for the memory cores in SOCs. This paper presents an infrastructure intelligent property (IIP) for testing, diagnosing, and repairing multiple memory cores in SOCs. The proposed IIP can perform parallel testing for multiple memories, and serial diagnosis or repair for one memory each time. In the repair mode, the proposed IIP can execute various redundancy analysis algorithms. Therefore, the user can select a better redundancy analysis algorithm for each memory core being tested according to its redundancy structure. Simulation results show that the proposed IIP needs less test time and redundancy analysis time than the processor-based built-in self-repair scheme. We also have realized the proposed IIP for four types of memories - two 8 K 64 bit SRAMs, one 4 K x 16 bit SRAM, and one 2 K x 32 bit SRAM - based on TSMC 0.18-mum standard cell technology. Simulation results show that the area overhead of the IIP is only about 4.6%.     

A 45 nm 2-port 8T-SRAM Using Hierarchical Replica Bitline Technique With Immunity From Simultaneous R/W Access Issues

We propose a new 2-port SRAM with a single read bit line (SRBL) eight transistors (8 T) memory cell for a 45 nm system-on-a-chip (SoC). Access time tends to be slower as a fabrication is scaled down because of threshold voltage (V_t) random variations. A divided read bit line scheme with shared local amplifier (DBSA) realizes fast access time without increasing area penalty. We also show an additional important issue of a simultaneous read and write (R/W) access at the same row by using DBSA with the SRBL-8T cell. A rise of the storage node causes misreading. A read end detecting replica circuit (RER) and a local read bit line dummy capacitance (LDC) are introduced to solve this issue. A 128 bit lines - 512 word lines 64 kb 2-port SRAM macro using these schemes was fabricated by a 45 nm bulk CMOS low-standby-power (LSTP) CMOS process technology [1]. The memory cell size is 0.597 mum². This 2-port SRAM macro achieves 7 times faster access time without misreading.     

A New Single-Ended SRAM Cell With Write-Assist

A 6T static random access memory (SRAM) cell with a new write-assist (WA) feature is presented. The WA technique reduces the problem of writing a "one" through an nMOS pass device, thereby making a single-ended bit line more attractive. Both active power and leakage power can be significantly reduced. Leakage charge can be pooled to help precharge bit lines. Cell area and performance are competitive with traditional SRAM cell area and performance     

Design of replica bit line control circuit to optimize power for SRAM

A design of a replica bit line control circuit to optimize power for SRAM is proposed. The proposed design overcomes the limitations of the traditional replica bit line control circuit, which cannot shut off the word line in time. In the novel design, the delay of word line enable and disable paths are balanced. Thus, the word line can be opened and shut off in time. Moreover, the chip select signal is decomposed, which prevents feedback oscillations caused by the replica bit line and the replica word line. As a result, the switch power caused by unnecessary discharging of the bit line is reduced. A 2-kb SRAM is fully custom designed in an SMIC 65-nm CMOS process. The traditional replica bit line control circuit and the new replica bit line control circuit are used in the designed SRAM, and their performances are compared with each other. The experimental results show that at a supply voltage of 1.2 V, the switch power consumption of the memory array can be reduced by 53.7%.     

三值钟控绝热静态随机存储器设计

通过对多值逻辑、绝热电路和三值SRAM结构的研究,提出一种新颖的三值钟控绝热静态随机存储器(SRAM)的设计方案。该方案利用NMOS管的自举效应,以绝热方式对SRAM的行列地址译码器、存储单元、敏感放大器等进行充放电,有效恢复储存在字线、位线、行列地址译码器等大开关电容上的电荷,实现三值信号的读出写入和能量回收。PSPICE模拟结果表明,所设计的三值钟控绝热SRAM具有正确的逻辑功能和低功耗特性,在相同的参数和输入信号情况下,与三值常规SRAM相比,节约功耗达68%。     

An Organic FET SRAM With Back Gate to Increase Static Noise Margin and Its Application to Braille Sheet Display

An integrated system of organic FETs (OFETs) and plastic actuators is proposed, and it is applied to a Braille sheet display. Some circuit technologies are presented to enhance the speed and the lifetime for the Braille sheet display. An OFET SRAM is developed to hide the slow transition of the actuators. Developed five-transistor SRAM cell reduces the number of the bit lines by one-half and reduces the SRAM cell area by 20%. Pipelining the write-operation reduced the SRAM write-time by 69%. Threshold voltage control technology using a back gate increased the static noise margin of SRAM and compensated for the chemical degradation of the OFETs after 15 days. The oscillation frequency tuning range from -82% to +13% in a five-stage ring oscillator is also demonstrated with the threshold voltage control technology. The overdrive techniques for the driver OFETs reduced the transition time of the actuator from 34 s to 2 s. These developed circuit technologies achieved the practical 1.75-s operation to change all 144 Braille dots on Braille sheet display and will be essential for the future large area electronics made with OFETs     

SRAM bitmap shape recognition and sorting using neural networks

This paper details the use of neural network technologies in the characterization of bit fail patterns occurring on SRAM chips as an alternative to the more traditional rule-based or knowledge-based approach to fail-pattern occurrence and classification analysis. The results of bit fail pattern count analyses are used both for fault analysis post-processing and manufacturing yield improvement methodologies. The move toward neural network implementation comes in response to prohibitively long processing times required for implementation of rule-based algorithms on more complex devices and the added flexibility of a neural network to learn new fail types in a more adaptive mode. An unsupervised approach to fail pattern identification was implemented on a 128 K SRAM chip using a two-layer Kohonen Self Organizing Map for identification and concurrence of bit fail pattern categories within SRAM chips. A second network utilized a multilayer perceptron (MLP) architecture with backpropagation of error for prediction of the number of occurrences per bitmap of each of the 34 previously identified shape types. The MLP used the output of a SOM as its input vector to assist in the feature extraction by shape type. Both trained networks out-performed existing rule-based algorithms both in ability to identify bit fail pattern types, frequency counts, and speed of processing     

Design of ternary clocked adiabatic static random access memory

Based on multi-valued logic,adiabatic circuits and the structure of ternary static random access memory (SRAM),a design scheme of a novel ternary clocked adiabatic SRAM is presented.The scheme adopts bootstrapped NMOS transistors,and an address decoder,a storage cell and a sense amplifier are charged and discharged in the adiabatic way,so the charges stored in the large switch capacitance of word lines,bit lines and the address decoder can be effectively restored to achieve energy recovery during reading and writing of ternary signals.The PSPICE simulation results indicate that the ternary clocked adiabatic SRAM has a correct logic function and low power consumption.Compared with ternary conventional SRAM,the average power consumption of the ternary adiabatic SRAM saves up to 68%in the same conditions.     

Low-power SRAM design using half-swing pulse-mode techniques

This paper describes a half-swing pulse-mode gate family that uses reduced input signal swing without sacrificing performance. These gates are well suited for decreasing the power in SRAM decoders and write circuits by reducing the signal swing on high-capacitance predecode lines, write bus lines, and bit lines. Charge recycling between positive and negative half-swing pulses further reduces the power dissipation. These techniques are demonstrated in a 2-K×16-b SRAM fabricated in a 0.25-μm dual-V_t CMOS technology that dissipates 0.9 mW operating at 1 V, 100 MHz, and room temperature. On-chip voltage samplers were used to probe internal nodes