等离子增强化学气相沉积法低温生长SiO_x薄膜的针孔缺陷修复

针对等离子增强化学气相沉积(PECVD)方法低温(60℃)生长氧化硅(SiOx)薄膜中存在的针孔缺陷,在SiOx薄膜上采取原子层沉积(ALD)方法生长氧化铝(AlOy),利用ALD方法材料保形生长的特点,进行SiOx薄膜的针孔缺陷修复工艺技术研究。实验结果表明:在SiOx薄膜上利用ALD方法保形生长氧化铝,可以明显降低AlOy/SiOx复合薄膜的水汽渗透率,提高薄膜封装性能。通过实验数据分析认为:复合薄膜的水汽阻隔能力是由于ALD方法及PECVD方法两种薄膜生长方法的综合作用,这种综合作用很有可能来自PECVD方法薄膜中针孔缺陷的修复,而ALD方法正是完成修复过程的技术手段。另外,ALD方法的工艺参数与针孔缺陷的修复效果相关,ALD生长周期时间延长,有利于提高针孔缺陷的修复效果,从而降低了复合薄膜的水汽渗透率。     

用白光空间滤波系统检查IC掩模缺陷

本文介绍一种使用空间滤波的实时单一镜头白光信息处理系统来检查IC光刻掩模缺陷的方法。采用这种方法比传统的镜检法或激光相干处理技术更为简单、快速,且效果明显。它能明显地检查出IC掩模里的黑点、针孔、刻痕、电路缺损、短路和断路等微小缺陷,并可检测出最小线度为2μm的缺陷。     

鉴定HgCdTe晶体和光电二极管特性的电子束感生电流法

在扫描电子显微镜上采用电子束感生电流法鉴定了HgCdTe光伏探测器的晶体缺陷和表面状态。这种非破坏性方法也可使用于其他半导体传感器,并发现它适用于检验室温和低温器件的有效受光面积。探测器材料缺陷和表面处理不当所造成的痕迹,在小达0.05微米时仍可清楚地观测到。器件是在加增透膜前后检验的。该介质膜附着不良和针孔等缺陷亦可用本方法加以检测。本法可鉴定制造器件时所引起的损伤。这种感生信号的成象特性鉴定与扫描电子显微镜的二次电子成象表面鉴定及x射线形貌表面鉴定作了比较。     

PDP器件中介质的制作技术研究

本文讨论了对ＰＤＰ上下基板所用介质层的要求及其浆料选择的原则，研究了丝网印刷、干燥和烧结等工艺对介质层厚度、表面状态、透过率、绝缘性能等的影响，介绍了减小和消除介质层欠点、针孔、气泡等缺陷的措施，确立了一套制作介质层的综合、有效的技术方法。     

Nd:GGG激光晶体的缺陷研究

Nd:GGG晶体是热容固体激光器的一种重要的工作介质.采用提拉法沿〈111〉方向生长出直径为60 mm的Nd:GGG单晶,利用应力仪、偏光显微镜和环境扫描电子显微镜及化学腐蚀等仪器和手段,对晶体的宏观和微观缺陷进行了观察和分析,可为改善生长工艺、生长大尺寸优质Nd:GGG晶体提供指导.     

检测栅极薄氧化层缺陷所需的失效分析技术

二氧化硅在VLSI中起着极其重要的作用.氧化层击穿是MOS VLSI的主要失效机理,并已成为电子设备中可靠性问题的重要原因。难解决的缺陷是圆片加工期间造成的。归因于裂纹、针孔或粒子沾污的有缺陷介质可使氧化层造成局部高电场击穿和漏电流过大。为了分析栅极薄氧化层的介质失效,必须采用先进的分析技术来鉴别失效原因。目前最常用的分析技术有四种:发光显微镜(PEM),液晶检测(LCD)、电子束感生电流(EBIC)和KOH腐蚀法。     

三层介质中激光扫描共聚焦显微镜的模型

建立了一种激光扫描共聚焦显微镜三层介质中点扩展函数的计算模型。在Hammoum分式的基础上得到三层介质中的理论公式,对比分析探测光路中的偶极子振动方向对点扩展函数的影响以及各种点扩展函数,讨论针孔对点扩展函数、收集的能量和信噪比的影响。计算表明,振动方向平均化的偶极子的探测点扩展函数优于沿x轴、z轴振动的偶极子的探测点扩展函数;综合点扩展函数小于照明和探测点扩展函数,且针孔越小,经过针孔过滤后的综合点扩展函数更小;方形针孔和圆形针孔的收集能量曲线类似,但方形针孔的曲线靠右,圆形针孔的信噪比曲线总体上优于方形针孔的信噪比曲线。     

针孔缺陷对集成电路功能成品率影响分析与仿真

对集成电路针孔缺陷引起功能成品率下降的模型进行了研究,给出了分析和仿真针孔功能成品率的两种计算方法——Monte-Carlo方法和关键面积提取方法,这对集成电路成品率设计和分析是非常重要的.     

电子设备环境应力筛选方法探讨

电子设备环境应力筛选是产品研制生产的一种工艺手段,筛选效果取决于旌加于产品的环境应力和电应力水平以及检测仪表的能力.施加应力的大小决定了能否在预定的时间内加速地将潜在的缺陷变为故障;检测能力的大小决定了能否将已被应力激发变成故障的潜在缺陷找出来,以便加以排除.因此,环境应力筛选又可看作是产品质量控制检查和测试过程的延伸.探讨了如何根据标准和产品的具体情况来选取筛选应力、进行电子设备环境应力筛选的方法.     

针孔缺陷对集成电路功能成品率影响分析与仿真

对集成电路针孔缺陷引起功能成品率下降的模型进行了研究 ,给出了分析和仿真针孔功能成品率的两种计算方法—— Monte- Carlo方法和关键面积提取方法 ,这对集成电路成品率设计和分析是非常重要的     

Recoiled-oxygen-free processing for 1.5 nm SiON gate-dielectric insub-100-nm CMOS technology

We have developed high-quality 1.5-nm-SiON gate dielectrics using recoiled-oxygen-free processing. We found that oxygen recoiling from a sacrificial oxide during ion implantation or defects induced by recoiled oxygen change the growth mechanism of SiON gate dielectrics of less than 2 nm and degrade the controllability of film thickness, film quality, and device electrical characteristics. PMOSFETs using the recoiled-oxygen-free process and As-implantation for the channel have better controllability of gate dielectric thickness, up to one-third less gate leakage current, a hundred times more reliable TDDB characteristics, and a 20% improvement in drain current compared to the conventional process. Thus, an Si substrate without recoiled oxygen is essential in forming high-quality SiON gate dielectrics of less than 1.5 nm. In addition, we will show that anneal before SiON gate dielectric formation removes the recoiled oxygen from the Si substrate and improves controllability of the gate SiON gate dielectric thickness     

Charge transport model to predict dielectric breakdown as a function of voltage,temperature, and thickness

As the minimum pitch in interconnects continues to shrink, dielectric breakdown is becoming increasingly more difficult to qualify for each new technology node. Standard voltage-acceleration models provide quick, but general, assessments of the dielectric quality. Instead, a one-dimensional charge transport model has been developed as a tool to investigate the process of the dielectric breakdown and why it occurs. The model couples Poisson's equation with constitutive equations for mobile electrons, trapped electrons, and defects in the dielectric. Bonds in the dielectric matrix are weakened by the electric field, and broken by energetic electrons, creating defects. Failure occurs when a critical defect density is reached, causing trap-to-trap tunneling and an abrupt increase in the current.The model successfully replicates electrical data for leakage current and dielectric failure as a function of voltage, temperature, and thickness. The activation energy for dielectric failure is shown to increase as the electric field decreases, resulting in much higher activation energies at operating conditions compared to testing conditions. The dielectric strength also increases for decreasing thickness based on a previous theory for planar dielectrics, and is shown to cause the failure vs. field slope to increase for thinner dielectrics.     

Ultrathin gate oxide reliability: physical models, statistics, andcharacterization

The present understanding of wear-out and breakdown in ultrathin (t_ox < 5.0 nm) SiO₂ gate dielectric films and issues relating to reliability projection are reviewed in this article. Recent evidence supporting a voltage-driven model for defect generation and breakdown, where energetic tunneling electrons induce defect generation and breakdown will be discussed. The concept of a critical number of defects required to cause breakdown and percolation theory will be used to describe the observed statistical failure distributions for ultrathin gate dielectric breakdown. Recent observations of a voltage dependent voltage acceleration parameter and non-Arrhenius temperature dependence will be presented. The current understanding of soft breakdown will be discussed and proposed techniques for detecting breakdown presented. Finally, the implications of soft breakdown on circuit functionality and the applicability of applying current reliability characterization and analysis techniques to project the reliability of future alternative gate dielectrics will be discussed     

Recent progress of (Ba,Sr)TiO<Subscript>3</Subscript> thin films for tunable microwave devices

The (Ba_1−xSr_x)TiO₃ (BST) ferroelectric thin films exhibit outstanding dielectric properties, even at high frequencies (>1 GHz), and large, electric-field dielectric tunability. This feature makes them suitable for developing a new class of tunable microwave devices. The dielectric properties and dielectric tuning property of BST thin films are closely related to the film compositions, substrate types, and post-deposition process. The successful implementation of BST films as high-frequency dielectrics in electrically tunable microwave devices requires a detailed understanding of both their processing and material properties. This paper will review the recent progress of BST thin films as active dielectrics for tunable microwave devices. The technical aspects of BST thin films, such as processing methods, post-annealing process, film compositions, film stress, oxygen defects, and interfacial structures between film and substrate, are briefly reviewed and discussed with specific samples from the recent literature. The major issues requiring additional investigations to improve the dielectric properties of BST thin films for tunable microwave applications are also discussed.     

Mechanical stress field assisted charge de-trapping in carbon doped oxides

Leakage current and dielectric breakdown effects are conventionally studied under electrical fields alone, with little regard for mechanical stresses. In this letter, we demonstrate that mechanical stress can influence the reliability of dielectrics even at lower field strengths. We applied tensile stress (up to 8 MPa) to a 33% porous, 504 nm thick carbon doped oxide thin film and measured the leakage current at constant electrical fields (up to 2.5 MV/cm). The observed increase in leakage current at relatively low electric fields suggests that mechanical stress assists in trap/defect mediated conduction by reducing the energy barrier potential to de-trap charges in the dielectric.     

Novel Dielectric-Constant Evaluation Method for Low-$k$ Multilevel Metallization Structures in ULSI

Precise evaluation of the dielectric constants of low- $k$ interlayer dielectrics in ULSI is essential in order to analyze the effects of their fabrication process and their structure on their $k$ -values. However, this is difficult to achieve in complicated multilayer structures with various kinds of stacked films having different physical properties. To address this problem, we have developed a novel evaluation method that makes it possible to precisely analyze the effects of structure and fabrication process on the $k$ -values of dielectrics.      

Reliability aspects of Hf-based capacitors: Breakdown and trapping effects

Dielectric breakdown and trapping effects are of serious concern for high-k dielectrics. In this paper acceleration models for dielectric breakdown and leakage current degradation in HfSiO films thicker 10 nm are introduced and the mechanism for leakage current increase during constant voltage stress is evaluated.     

先进的Hf基高k栅介质研究进展

随着CMOS器件特征尺寸的不断缩小,SiO2作为栅介质材料已不能满足集成电路技术高速发展的需求,利用高k栅介质取代SiO2栅介质成为微电子技术发展的必然.但是,被认为最有希望替代SiO2的HfO2由于结晶温度低等缺点,很难集成于现有的CMOS工艺中,新型Hf基高k栅介质的研究成为当务之急.据报道,在HfO2中引入N、Si、Al和Ta可大大改善其热力学稳定性,由此形成的高k栅介质具有优良的电学特性,基本上满足器件的要求.本文综述了这类先进的Hf基高k栅介质材料的最新研究进展.     

Time-dependent dielectric breakdown (TDDB) distribution in n-MOSFET with HfSiON gate dielectrics under DC and AC stressing

This paper discusses time-dependent dielectric breakdown (TDDB) in n-FETs with HfSiON gate stacks under various stress conditions. It was found that the slope of Weibull distribution of T_bd, Weibull β, changes with stress conditions, namely, DC stress, unipolar AC stress and bipolar AC stresses. On the other hand, the time evolution component of stress-induced leakage current (SILC) was not changed by these stresses. These experimental results indicate that the modulation of electron trapping/de-trapping and hole trapping/de-trapping by stress condition changes the defect size in high-k gate dielectrics. Therefore, the control of injected carrier and the characteristics of trapping can provide the steep Weibull distribution of T_bd, leading to long-term reliability in scaled CMOS devices with high-k gate stacks.     

Direct Observation of Anomalous Positive Charge and Electron-Trapping Dynamics in High-k Films Using Pulsed-MOS-Capacitor Measurements

Due to the rapid transient charging and discharging effects in high-k dielectrics, conventional "stress and sense" techniques cannot be reliably applied to study the oxide traps in these dielectrics. We introduce a new transient methodology based on the pulsed-MOS-capacitor measurement, which allows us to observe aspects of the dynamics of transient charging and discharging behavior in the high-k dielectric. The method is relatively simple and easy to employ. It has the advantage that the surface is depleted during the initial transient allowing the effect of anomalous positive charge and electron trapping to be isolated. We apply this technique to explain oxide charging in HfO₂ samples deposited by atomic layer deposition and metal-organic chemical vapor deposition