Evolutionary design of high signal integrity interconnection based on eye-diagram

Frequency of the digital signal in PCBs has remained at about 1 GHz, while that in VLSIs become more than several GHz. The frequency gap comes from signal integrity (SI) deterioration in PCB in GHz-domain. To overcome this problem, we have already proposed segmental transmission line, in which genetic algorithm is used to solve the combinatorial explosion problem in the design. In this paper, we propose a novel fitness based on the eye-diagram, which is widely and generally used for SI evaluation in the high-speed interconnection design field. And we also propose a high-speed eye-diagram calculation method based on virtual eye-diagram. This eye-diagram is constructed by superposing the single-shot pulse responses and can reduce the simulation time. The simulation experiments demonstrate that our proposed fitness increases the eye height and eye width by 3.07 and 1.06 times, respectively, compared with the conventional one.     

基于信号完整性的高速数据采集传输系统设计

高速PCB设计中必须面对信号完整性问题,并采取有效措施;基于信号完整性分析的高速PCB设计流程能够缩短产品开发周期,降低开发成本;根据这个流程设计了一个高速数据采集传输系统,仿真结果表明电路的信号完整性问题得到了改善,对数据采集系统的性能进行测试后表明AD的动态有效位数达到了10位;说明了在高速电路设计中采用基于信号完整性仿真设计是必要的,也是可行的。     

高速PCB的互连综合

串扰和信号完整性等问题已成为高速ＰＣＢ设计得面临的主要问题,高速发展的现代电子技术对新一代ＥＤＡ工具及设计方法提出了更高要求。文中从现行的规则驱动的ＰＣＢ设计方法出发,畅述了互连综合设计方法的实现与特点,并对现行的ＥＤＡ工具进行了分析与展望。     

千兆以太网交换机的信号完整性研究*

以千兆以太网交换机PCB设计出现的问题为背景,研究高速数字电路设计的信号完整性问题,从板层、电源和传输线三方面分析原因,并提出解决方法,测试表明取得了有效的结果。     

基于FPGA的RAID控制卡实现及仿真研究

首先介绍了基于FPGA的一种RAID控制卡的原理及系统设计、印刷电路板(PCB)的具体实现.由于板卡运行在66MHz总线时钟之上,必须考虑高频下电路的性能及电路的信号完整性等, 因而在PCB设计阶段对电路的仿真显得尤为重要.还将介绍基于IBIS模型的信号完整性仿真分析,并利用信号噪声分析软件(Hyperlynx)对高速电路设计中的PCB布局布线、匹配电阻设计和并行线串扰分析进行深入研究.根据仿真分析结果调整原设计,从而提高了信号质量,减少开发成本.     

Semantic integrity enforcement in centralized DBMS and distributed DBMS based on slow (geographically distributed) and fast (local area) networks

In this paper we investigate techniques for decreasing the overhead of semantic integrity enforcement or equivalently the overhead of transaction validation with respect to a set of semantic integrity (SI) assertions. We discuss the problem of semantic integrity enforcement from two points of view. First we describe three approaches to decrease the overhead of SI enforcement. Second we analyze the cost of several SI enforcement methods in centralized and distributed database systems based on slow and fast (local) networks.     

嵌入式3G无线视频监控系统硬件设计与信号完整性仿真

提出了一种基于DaVinci平台的嵌入式3G无线视频监控系统的解决方案。该方案充分利用WCDMA网络的高带宽,可进行两路视频的同步监控。对系统的硬件设计进行了深入的探讨,设计了各个功能模块。应用Hyperlynx软件与IBIS模型对硬件PCB设计进行了仿真分析,有效地解决了系统DDR2接口电路中出现的反射、串扰等信号完整性（SI）方面的问题,充分保证了高速PCB设计的质量和速度。相比传统的有线视频监控,该方案更加灵活,使用范围更加广泛。     

DDR3系统混合建模与协同仿真

DDR3存储器已经成为目前服务器和计算机系统的主流应用,虽然DDR3采用双参考电压、片上校准引擎、动态ODT、fly-by拓扑以及write-leveling等技术在一定程度上提高了信号完整性,但设计实现高数据率仍然比较困难.针对某自研处理器及服务器主板设计,采用混合建模方法,建立了由芯片I/O、封装、PCB、过孔、连接器和DIMM条组成的DDR3的全通道信号完整性仿真平台,通过频域仿真,比较通道中各种无源组件引入的插损和回损,通过时域仿真,分析各组件对接收眼图的不同影响程度,实现Chip,Package,PCB的协同仿真与设计优化,达到了预期指标.     

Digital-signal-waveform improvement on VLSI packaging including inductances

As the digital signal frequency in printed circuit boards (PCBs) increases, waveform distortion, or the signal integrity (SI) problem, is getting more and more serious. The reason the SI problem is becoming serious is that wires or traces need to be regarded as transmission lines which are sensitive to electric noise. In order to overcome this problem, we have proposed a novel methodology called a segmental transmission line (STL), and have shown its effectiveness using computer simulations and fundamental prototypes. However, in the STL design, the combinatorial explosion problem occurs. To solve this problem, a genetic algorithm (GA) was used to design the STL. In this article, we apply the STL to a bus system that includes inductances, which come from the very-large-scale integration (VLSI) packaging. We evaluated the STL in simulation experiments as well as actual experiments using prototypes, and obtained a maximum improvement ratio of 1.53 in the actual experiment.     

Robust power allocation algorithm for analog network coding with imperfect CSI

Power allocation promises significant benefits in wireless networks. However, these benefits depend on knowledge of the channel state information （CSI）, which is hardly perfect. Therefore, robust algorithms that take into account such CSI uncertainties play an important role in the design of practical systems. In this paper, we formulate the power allocation problem as the maximum individual outage probability minimization subject to total power consumption for analog network coding （ANC） protocol of a two-way relay system. We show that these problems can be cast as convex optimization problems. Non-robust power allocation algorithm is first developed under the ideal assumption of perfect CSI. Then we introduce robust optimization methodology that accounts for the imperfect CSI. We show that ignoring CSI uncertainties in our designs can lead to drastic performance degradation. On the other hand, the proposed robust power allocation provides significant performance gain over non-robust power allocation and uniform power allocation in terms of overall system outage probability over a wide range of channel estimation errors. This work highlights the importance of the proposed robust algorithm in realistic two-way relaying networks.     

高速多层板过孔分析与仿真

过孔效应已经成为制约高速PCB设计的关键因素之一,介绍了高速PCB设计中过孔对信号完整性的影响,尤其对于高速多层板过孔的特性进行了详细分析,并采用软件对多层印刷电路板上的过孔模型进行了仿真,着重分析了Stub对过孔传输特性所产生的影响,以及Back-drilling工艺的优势,仿真结果对高速PCB设计具有实际指导作用.     

Codence EDA中PCB分析工具Specctraquest的使用

电子设计自动化(EDA)技术是目前进行电子产品设计中所采用的主要技术,设计者利用它可以设计出更完美的产品,并且极大地缩短了设计周期。但是随着电子技术的不断发展,在设计中,特别是在高速PCB的设计中出现了一些新的问题。例如:延时、串扰、电磁干扰等物理设计问题,迫切需要提供一些仿真分析工具来解决这些问题。本文主要介绍了Cadence EDA软件中的信号完整性仿真设计工具SpecctraQuest的使用与建模方法。     

基于固态电子盘的最小PC测控系统设计

在航空、军事、石油等领域中对测控仪器的占用空间和功耗有着严格的要求,设计出高可靠、小型化的工业智能测控系统显得尤为重要。文章以PC/104工业通用PC构架为基础,设计了基于固态电子盘的最小PC系统,并将以FPGA为核心的测控系统集成在同一个主板上。该系统能够在90mm×68mm的PCB板上提供与PC兼容的测控系统解决方案,而且提供了可配置计算的硬件加速能力。所以非常适合受空间限制的小型化测控系统使用。     

Transceiver designs with matrix-version water-filling architecture under mixed power constraints混合功率约束条件下, 矩阵版注水结构的收发机的设计

In this paper, we investigate the multiple-input multiple-output (MIMO) transceiver design under an interesting power model named mixed power constraints. In the considered power model, several antenna subsets are constrained by sum power constraints while the other antennas are subject to per-antenna power constraints. This kind of transceiver designs includes both the transceiver designs under sum power constraint and per-antenna power constraint as its special cases. This kind of designs is of critical importance for distributed antenna systems (DASs) with heterogeneous remote radio heads (RRHs) such as cloud radio access networks (C-RANs). In our work, we try to solve the optimization problem in an analytical way instead of using some famous software packages e.g., CVX or SeDuMi. In our work, to strike tradeoffs between performance and complexity, both iterative and non-iterative solutions are proposed. Interestingly the non-iterative solution can be interpreted as a matrix-version water-filling solution extended from the well-known and extensively studied vector version. Finally, simulation results demonstrate the accuracy of our theoretical results.     

Optimizing Decoupling Capacitors in 3D Circuits for Power Grid Integrity

This article studies one of the EDA problems for 3D IC design. The article presents a design automation solution for power grid optimization in 3D ICs. The authors propose a congestion-aware 3D power supply network optimization algorithm, which applies a sequence-of-linear-programs-based method to optimize the power grid design. We explore the trade-offs between MIM decaps and traditional CMOS decaps in chip design, and we propose a congestion-aware 3D power supply network optimization algorithm to optimize this trade-off. One of the novel features of our work is that it optimizes the power supply network using both conventional CMOS decaps and metal insulator-metal (MIM) decaps. However, because MIM decaps are built between layers of metal interconnects, they present routing blockages to nets that attempt to cross them, and therein lies the trade-off. The properties of MIM decaps make them attractive for both 2D and 3D chips, but we pay particular attention to the 3D decap problem in this article because, first, the power integrity problem is particularly critical in 3D, and requires novel approaches that leverage advances in materials, and second, the added complexity of handling routing blockages in a constrained environment makes the 3D problem especially challenging.     

Power Supply Noise in SoCs: Metrics, Management, and Measurement

Power integrity is emerging as a major challenge in deep-submicron SoC designs. The lack of predictability is complicating timing closure, physical design, production test, and speed grading of SoCs. This article describes and validates two metrics that quantify the impact of power supply noise. The IC industry is moving quickly to adopt new deep-submicron (DSM) technologies that offer unprecedented integration levels and cost benefits. These advanced technologies pose unexpected challenges to the semiconductor industry. The DSM problems have led the development of SOC design methodologies to deal with the problem of complexity and productivity. To reduce power dissipation, manufacturers have scaled down supply voltage in each successive technology. Designers analyzed power supply noise with static voltage drop (SVD) analysis, which might not reflect the true nature of power supply fluctuations. Dynamic voltage drop (DVD) analysis is emerging as a replacement of SVD analysis for capturing the impact of power supply noise on the timing behavior of logic and memory cells.     

基于DSP的网络摄像机硬件设计和仿真

详细说明了基于TITMS320DM642DSP芯片的网络摄像机的硬件设计,并针对DSP系统实现中所涉及到的高速数字电路设计问题,如时序问题、信号完整性问题,通过采用IBIS模型,在HyperLynx仿真软件平台上布线前进行仿真,利用仿真结果作为布线的约束,并在布线后进行仿真,确保了正确性。实践证实,在高速设计中进行正确的时序分析及仿真可以保证高速PCB设计的质量和速度。     

Protel制板与Multisim仿真电路的实现

为了提高高职学生电路设计与制作的效率,探讨Multisim 10与Protel 2004联合制板实现电路.研究了两种电路转换接口技术,网络表的内涵和实质,及如何处理电子元器件封装标准.同时研究了Protel2004中电路PCB设计中可能出现的问题,并针对问题快速便捷的解决措施,设计出符合实际电路和热转印工艺制作要求的PCB.通过“软”、“硬”结合,“虚”、“实”结合,从电路仿真到电子产品功能的实现,提升对电路应用分析能力和实践能力.     

基于FPGA的高速高密度PCB设计中的信号完整性分析

根据摩尔定律,高速高密度印刷电路板(PCB)的设计变得越来越复杂。针对大型或特大型高速高密度PCB设计中信号完整性的一些关键问题,如：PCB层叠、传输线类型、特征阻抗计算、互连拓扑结构、端接技术、延迟匹配、串扰分析、差分布线等,通过理论分析、仿真验证、工程实践相结合的方式进行讨论,并给出相应的解决方法或设计规则。在此基础上,给出现场可编程门阵列(FPGA)多层PCB板设计原则。具体工程实验证明,在这些规则或机制的驱动下,高速高密度PCB的设计能够获得良好的实际效果。     

FPGA与DDR2 SDRAM互联的信号完整性分析

论述了Virtex-5和DDR2?SDRAM在互联中的信号完整性问题,利用前仿和后仿的措施分析和验证了它们在不同互联拓扑结构下的信号完整性。通过原型机的测试,验证了该理论在高速电路设计中的应用有效性。