An accelerator design for speedup of Java execution in consumer mobile devices

In today’s consumer electronics market, Java has become one of the most important programming languages for the rapid development of mobile applications – spanning from home appliances/controllers, mobile and communication devices, to network-centric applets. However, the demand for high-performance low-power Java-based consumer mobile applications puts forward new challenges to the system design and implementation. This paper analyzes the energy consumption, execution efficiency, and speed issues of Java applications in a typical consumer mobile device environment. By adopting a hardware-assisted approach, we introduce a Java accelerator with a companion Java virtual machine. The accelerator is designed in an asynchronous style, and can be integrated with most existing processors and operating systems. The core architecture, design philosophy, and implementation considerations are presented in detail in this paper.     

An assembler and disassembler framework for Java™ programmers

The Java™ programming language is primarily used for platform-independent programming. Yet it also offers many productivity, maintainability and performance benefits for platform-specific functions, such as the generation of machine code.

We have created reliable assemblers for SPARC™ , AMD64, IA32 and PowerPC which support all user mode and privileged instructions and with 64 bit mode support for all but the latter. These assemblers are generated as Java source code by our extensible assembler framework, which itself is written in the Java language. The assembler generator also produces javadoc comments that precisely specify the legal values for each operand.

Our design is based on the Klein Assembler System written in Self. Assemblers are generated from a specification, as are table-driven disassemblers and unit tests. The specifications that drive the generators are expressed as Java language objects. Thus no extra parsers are needed and developers do not need to learn any new syntax to extend the framework for additional ISAs.

Every generated assembler is tested against a preexisting assembler by comparing the output of both. Each instruction’s test cases are derived from the cross product of its potential operand values. The majority of tests are positive (i.e., result in a legal instruction encoding). The framework also generates negative tests, which are expected to cause an error detection by an assembler. As with the Klein Assembler System, we have found bugs in the external assemblers as well as in ISA reference manuals.

Our framework generates tens of millions of tests. For symbolic operands, our tests include all applicable predefined constants. For integral operands, the important boundary values, such as the respective minimum, maximum, 0, 1 and −1, are tested. Full testing can take hours to run but gives us a high degree of confidence regarding correctness.     

基于Python语言环境的轻量AOP工具的设计实现

作为众多成功开源软件产品之一的Python程序设计语言,其自身最具鲜明性的是“动态语言”特性与独特的“面向对象模型”系统。而AOP(面向方面编程)技术,作为OOP(面向对象编程)中解决代码耦合度问题的新技术思路,经历了若干年的研究探索后,已经在C 以及Java语言环境中被实现为实用工具。本文将尝试基于Python语言环境,利用其“动态语言”特性与的“面向对象模型”,设计实现一个轻量工具。     

用虚拟寄存器技术开发Java处理器的指令级并行性

本文讨论了开发Ｊａｖａ处理器的指令级并行性的策略，提出采用虚拟寄存器技术的Ｊａｖａ处理器（ＶＲＪＰ）结构，并给出了判断相关性和管理虚拟寄存器的方法。分析和实验表明，ＶＲＪＰ能够有效地开发Ｊａｖａ的指令级并行性，提高Ｊａｖａ程序的执行效率。在ＶＲＪＰ中，大多数虚拟寄存器都不需要对应的物理寄存器，大大降低了物理寄存器的访问频率。     

Cost analysis of object-oriented bytecode programs

Cost analysis statically approximates the cost of programs in terms of their input data size. This paper presents, to the best of our knowledge, the first approach to the automatic cost analysis of object-oriented bytecode programs. In languages such as Java and C#, analyzing bytecode has a much wider application area than analyzing source code since the latter is often not available. Cost analysis in this context has to consider, among others, dynamic dispatch, jumps, the operand stack, and the heap. Our method takes a bytecode program and a cost model specifying the resource of interest, and generates cost relations which approximate the execution cost of the program with respect to such resource. We report on COSTA, an implementation for Java bytecode which can obtain upper bounds on cost for a large class of programs and complexity classes. Our basic techniques can be directly applied to infer cost relations for other object-oriented imperative languages, not necessarily in bytecode form.     

Decompilation of Java bytecode to Prolog by partial evaluation

Reasoning about Java bytecode (JBC) is complicated due to its unstructured control-flow, the use of three-address code combined with the use of an operand stack, etc. Therefore, many static analyzers and model checkers for JBC first convert the code into a higher-level representation. In contrast to traditional decompilation, such representation is often not Java source, but rather some intermediate language which is a good input for the subsequent phases of the tool. Interpretive decompilation consists in partially evaluating an interpreter for the compiled language (in this case JBC) written in a high-level language with respect to the code to be decompiled. There have been proofs-of-concept that interpretive decompilation is feasible, but there remain important open issues when it comes to decompile a real language such as JBC. This paper presents, to the best of our knowledge, the first modular scheme to enable interpretive decompilation of a realistic programming language to a high-level representation, namely of JBC to Prolog. We introduce two notions of optimality which together require that decompilation does not generate code more than once for each program point. We demonstrate the impact of our modular approach and optimality issues on a series of realistic benchmarks. Decompilation times and decompiled program sizes are linear with the size of the input bytecode program. This demonstrates empirically the scalability of modular decompilation of JBC by partial evaluation.     

基于椭圆区域协方差描述子和卡尔曼粒子滤波的鲁棒视觉跟踪方法

针对传统的或概率性的协方差跟踪中采用的矩形区域协方差描述子不能精确反映目标的非刚性形变的问题,提出椭圆区域协方差描述子,将各种不同类型的特征融入统一的模型中,实现了基于多特征的目标跟踪,并将其与卡尔曼粒子滤波相结合,提出一种鲁棒的视觉目标跟踪方法.实验结果表明,该方法对光线变化、噪声干扰、部分和完全遮挡、目标的尺度和角度的变化以及目标的快速运动都具有较好的鲁棒性.     

Tool-Supported Refactoring of Existing Object-Oriented Code into Aspects

Aspect-oriented programming (AOP) provides mechanisms for the separation of crosscutting concerns - functionalities scattered through the system and tangled with the base code. Existing systems are a natural testbed for the AOP approach since they often contain several crosscutting concerns which could not be modularized using traditional programming constructs. This paper presents an automated approach to the problem of migrating systems developed according to the object-oriented programming (OOP) paradigm into aspect-oriented programming (AOP). A simple set of six refactorings has been defined to transform OOP to AOP and has been implemented in the AOP-migrator tool, an Eclipse plug-in. A set of enabling transformations from OOP to OOP complement the initial set of refactorings. The paper presents the results of four case studies, which use the approach to migrate selected crosscutting concerns from medium-sized Java programs (in the range of 10K to 40K lines of code) into equivalent programs in AspectJ. The case study results show the feasibility of the migration and indicate the importance of the enabling transformations as a preprocessing step     

Dynamics of cognitive load theory: A model-based approach

Since its conception nearly two decades ago, cognitive load theory (CLT) has been a fertile ground for both empirical and theoretical investigations. The research accumulated over the years has contributed not only to the theory’s validation, but also generated new insights. These new insights helped to refine CLT, making it more precise, but also more complex. A formal (mathematical) simulation model is proposed as a new analytical tool for investigating CLT’s increasingly intricate postulates and their dynamic implications. This paper describes how the theoretical relationships between certain features of instruction and the cognitive capacities of learners can be expressed formally, and how the resulting model can help gain insights into the learning dynamics that arise from these relationships, providing a new aid for research, teaching and practice in the field of instructional design.     

A multi-agent approach to load consolidation in transportation

The operational decisions of today’s logistics sector have many difficulties such as dynamism of the order attributes and environmental changes. This sector is generally operating under unpredictable environments and having high degree of complex interactions. The dispatch officers especially have difficulties while making load/capacity/route planning and load consolidation decisions. They use numerous alternative consolidation techniques in order to be cost effective during their decisions such as time based consolidation or quantity based consolidation or both of them simultaneously. In this paper we propose a multi-agent based load consolidation decision making approach. In the proposed approach the load consolidation decisions for the less-than-truckload orders are made by the software agents. The less-than-truckload orders are assigned/consolidated to the trucks by the negotiation mechanism constructed within the model.     

Impact of two types of partner,perceived or actual,in human–human and human–agent interaction

Participants engaged in the Prisoner’s dilemma game with a partner through a computer terminal. We define two types of partner: a perceived partner and an actual partner, and manipulated the two factors independently. A perceived partner means a partner with whom participants imagined themselves to be interacting; instruction given by an experimenter controls the image of the perceived partner. An actual partner can change its behavior. In one scenario participants actually interacted with a human partner, in another scenario their partner was either a mostly cooperating computer agent or a mostly defecting computer agent. Three experiments were performed. The result suggested that the participants’ selection behavior was largely influenced by the instruction given about the partner by the experimenter and not influenced by the partner’s actual behavior. The analysis of the participants’ impressions of the partner showed that the effect of instruction about the partner disappeared. Individual likeability for a partner was very influenced by the partner’s behavior; as the participants incurred more defect actions from the partner, individual likeability for the partner decreased. On the other hand, social likeability for a partner was not so influenced by the partner’s behavior, but rather related to the participants’ own behavior. The participants who made more defect actions rated their partner’s social likeability lower.     

基于覆盖率驱动的高性能DSP指令集验证方法

针对传统定向测试效率较低且容易遗漏边界条件,以及测试平台扩展性、移植性差等问题,利用SystemVerilog的面向对象特性、随机约束求解机制以及覆盖率统计机制,提出一种快速搭建覆盖率驱动的随机测试平台的方法。采用面向对象方法对指令集建模,同时定义功能覆盖点和交叉覆盖率,并对随机约束规则进行描述,利用SystemVerilog的约束求解机制在覆盖率驱动下生成大量的测试指令码。对"银河飞腾"高性能DSP芯片指令集进行验证,结果表明,与定向测试相比,随机测试的寄存器和数据通路覆盖率提高50%,操作数覆盖率提高90%以上,交叉覆盖率提高75%以上,同时功能覆盖率能在较短的时间内达到预期值,从而缩短验证周期。     

DoS-resistant ID-based password authentication scheme using smart cards

In this paper, we provide a defense mechanism to Kim-Lee-Yoo’s ID-based password authentication scheme, which is vulnerable to impersonation attacks and resource exhaustion attacks. Mutual authentication and communication privacy are regarded as essential requirements in today’s client/server-based architecture; therefore, a lightweight but secure mutual authentication method is introduced in the proposed scheme. Once the mutual authentication is successful, the session key will be established without any further computation. The proposed defense mechanism not only accomplishes the mutual authentication and the session key establishment, but also inherits the security advantages of Kim-Lee-Yoo’s scheme, e.g. it is secure against password guessing attacks and message replay attacks.     

Power-aware scoreboard alternatives for multimedia processors

Intel’s XScale which has powered many multimedia applications uses scoreboard to control instruction execution. Scoreboard stalls the pipeline whenever a source operand or functional unit is needed but not available. While waiting for the availability of the resources, the processor accesses the scoreboard every cycle. Such accesses consume energy without contributing to performance. We address this inefficiency by investigating stall behaviour and introduce an adaptive technique to avoid regular access to the scoreboard during stall periods. Our study shows that by using our technique and for the representative subset of MiBench benchmark suite studied here, it is possible to reduce scoreboard energy consumption by up to 33% while maintaining performance cost within 0.25%.     

The Gmicro/300 32-bit microprocessor

A high-end microprocessor, the Gmicro/300, based on the TRON architecture specification is described. In contrast to other RISC (reduced-instruction-set-computer) or CISC (complex-instruction-set-computer) chips, it executes an instruction with a memory operand and a register operand in one clock cycle. Separate cache memories improve performance more than 13.8%. The Gmicro/300's pipeline structure, its other one-cycle structures, and the effects of using internal caches are discussed     

基于前景理论的群体灰靶决策方法

考虑决策者关于各指标均有期望灰靶对群体决策的影响,提出一种基于前景理论的群体灰靶决策方法.该方法以期望灰靶为参考点来定义前景价值函数,利用奖优罚劣的线性变换算子对前景价值进行规范化处理,能够充分反映评价值是否中靶.根据群体意见一致性以及最高和最低评价对决策结果偏差的影响,构建决策者权重确定模型,并根据综合前景值的正负判断方案是否中靶.最后通过突发事件应急预案选择问题说明了该模型的可行性和有效性.     

Managing knowledge sharing: Emergent and engineering approaches

We wished to determine how the process of knowledge sharing could be managed, seeing that it is a knowledge management dilemma. If knowledge sharing is crucial to an organization’s interests, but is inherently emergent in nature, how can the organization still manage the process? In order to answer this question, a distinction was made between two approaches towards managing knowledge sharing: an emergent approach, focusing on the social dynamics between organizational members and the nature of their daily tasks, and an engineering approach, focusing on management interventions to facilitate knowledge transfer. While the first is central to today’s thinking about knowledge, we used a field study in six organizations to show that both approaches have value in explaining knowledge sharing. Instruments that are part of the engineering approach create conditions for variables in the emergent approach, which in turn also exert a direct influence on knowledge sharing.     

Modeling discrete event scalable network systems

Scalability in simulation tools is one of the most important traits to measure performance of software. The reason is that today’s Internet is the main instance of a large-scale and highly complex system. Simulation of Internet-scale network systems has to be supported by any simulation tool. Despite this fact, many network simulators lacks support for building large models. In this work, in order to propose a new approach for scalability issue in network simulation tools, a network simulator is developed based on behavior of honeybees and high performance DEVS, modular and hierarchical system theoretic approach. A biologically-inspired discrete event modeling approach is described for studying networks’ scalability and performance traits. Since natural systems can offer important concepts for modeling network systems, key adaptive and emergent attributes of honeybees and their societal properties are incorporated into a set of simulation models that are developed using the discrete event system specification approach. Large-scale network models are simulated and evaluated to show the benefits of nature-inspired network models.     

Design with part behaviors: behavior model, representation and applications

A part is primarily characterized by its ‘function(s)’. The function of the part is achieved through its ‘interactions’ with other parts in an assembly under a set of operating conditions. These ‘interactions’ constitute the ‘behavior’ of the part. The ‘part behavior’ is achieved through a set of spatial and design functional relationships between the interacting surfaces of the parts. The set of spatial and design functional relationships for a part constitutes the Part Function Model (PFM) of that part. In this paper, the nature and role of part ‘functions’ and ‘behaviors’ have been studied in the context of a product design system. The paper addresses the following issues: (i) relationship between function, behavior, and geometry of a part; (ii) importance of ‘part behavior’ over ‘part function’, and development of a ‘part behavior’ model; (iii) methodology for transforming the part behaviors into the PFM model of the part; (iv) product model framework for storing the PFM model information with an Object Oriented Programming (OOP) based CAD system (Concentra's Concept Modeller); (v) importance of the PFM model within the product development process; and (vi) application of the PFM model for generating various product specifications of the part. The prototype implementation of a Functional Design System for transforming part behaviors into different types of part specifications has also been presented in this paper.