LDPC码的高性能信道纠错码理论

自从上世纪60年代信道编码理论提出至今,就如何构建一个模拟通信信道容量问题成为了各国学者努力研究的主要课题,并且形成了通信能力体现的一个主要问题。半个世纪以来,各国科学通过构造以两条主线为基础提出的香农条件算法。提出的LDPC码的优异性能吸引人们不断探讨它在各个领域的应用：在宽带接入网中的应用方面,基于二元LDPC的多电平编码计算方法,通过仿真实验证明了该方法在信道传输过程中的高性能算法。在进行算法记录模型方面,用磁记录中的高吞吐率和繁杂LDPC译码方案结合进行。     

一种新颖的低错误平层LDPC码构造方法

针对低密度奇偶校验(LDPC)码在高信噪比区域可能存在错误平层的缺点,提出了一种低错误平层LDPC码的新构造方法。该方法的基本矩阵由渐进边增长(PEG)算法与近似环额外信息度(ACE)算法相结合,目的是提升基本矩阵中环的连通性;然后将基于分割移位(PS)的循环移位系数矩阵对基本矩阵循环扩展,以此构造出校验矩阵。该方法除了能够改善高信噪比区域的错误平层,还具有码长、码率的任意可设性特点。仿真结果表明,PAP-LDPC(3 600,2 700)码在信噪比为4 dB以后并未出现明显的错误平层。     

一种高性能低复杂度的非规则LDPC码的构造方法

该文提出了一种基于置换矩阵(permutation matrix)的非规则低密度奇偶校验(LDPC)码构造方法。首先,提出了基于改进eIRA(IeIRA)算法的全局矩阵M;接着,通过对全局矩阵H进行矩阵置换,生成LDPC码的校验矩阵H;研究了校验矩H中短圈(short cycle)长度与置换矩阵循环移位系数的关系,通过选择循环移位系数,以达到改善误比特率性能的目的。仿真结果表明,该文提出的构造方法在保证线性编码复杂度的前提下,增大了码字的最小距离,减少了小停止集合(stopping set)的数量,降低了误比特率的差错平台(error floor)(达到10-9)。     

基本陷阱集优化的IRA-LDPC码设计

具有非规则重复积累结构的低密度奇偶校验( IRA-LDPC )码是一种编码简单、性能优异的信道编码方法。陷阱集是影响码字性能的重要因素,尤其是基本陷阱集。为了进一步提高IRA-LD-PC码的纠错性能,针对该码校验矩阵的特殊结构,分析了基本陷阱集的分布特点,提出了一种陷阱集优化的IRA-LDPC码构造方法,该方法依据码字结构特点对基本陷阱集进行了搜索和消除,降低了错误平层。仿真结果显示,优化后的0.5码率、1024码长的码字在加性高斯白噪声信道下2.2 dB时误码率便达到10-7。     

LDPC Decoding by Failed Check Nodes for Serial Concatenated Code

The use of serial concatenated codes is an effective technique for alleviating the error floor phenomenon of low‐density parity‐check (LDPC) codes. An enhanced sum–product algorithm (SPA) for LDPC codes, which is suitable for serial concatenated codes, is proposed in this paper. The proposed algorithm minimizes the number of errors by using the failed check nodes (FCNs) in LDPC decoding. Hence, the error‐correcting capability of the serial concatenated code can be improved. The number of FCNs is simply obtained by the syndrome test, which is performed during the SPA. Hence, the decoding procedure of the proposed algorithm is similar to that of the conventional algorithm. The error performance of the proposed algorithm is analyzed and compared with that of the conventional algorithm. As a result, a gain of 1.4 dB can be obtained by the proposed algorithm at a bit error rate of 10^?8. In addition, the error performance of the proposed algorithm with just 30 iterations is shown to be superior to that of the conventional algorithm with 100 iterations.     

New constructions of LDPC codes based on circulant permutation matrices for AWGN channel

Two new design approaches for constructing Low-Density Parity-Check （LDPC） codes are proposed. One is used to design regular Quasi-Cyclic LDPC （QC-LDPC） codes with girth at least 8. The other is used to design irregular LDPC codes. Both of their parity-check matrices are composed of Circulant Permutation Matrices （CPMs）. When iteratively decoded with the Sum-Product Algorithm （SPA）, these proposed codes exhibit good performances over the AWGN channel.     

LDPC码的一种高效加权比特翻转译码算法

针对低密度奇偶校验(LDPC)码中加权比特翻转(WBF)译码算法在迭代过程中绝大多数情况都是进行单比特翻转,导致译码效率低并且可能会发生比特翻转"死循环"的现象,提出一种更为高效的加权比特翻转(EWBF)算法.该算法对翻转阈值进行了改进,使得每次迭代能够翻转多个比特,提高译码效率,并且能够避免译码过程出现的翻转"死循环"现象.仿真结果表明,所提译码算法与WBF算法、改进的WBF(MWBF)算法和IMWBF(Improved MWBF)算法相比,平均迭代次数分别降低51.6%~56.2%、49.6%~54.2%和48.1%~51.3%;而在译码性能方面,算法性能接近甚至优于IMWBF算法,当最大迭代次数设定为30次时,相比于IMWBF算法,在误码率为10-4时可获得0.92 dB的增益.     

提高检突发错误能力的LDPC码的构造方法

当前LDPC码的构造方法都是偏重于提高码的性能、降低编码复杂度2个方面，没有考虑码组之间的汉明距离和汉明距离分布，从而漏检部分突发错误。给出了一种次优的考虑码组汉明距离分布的构造方法，和已有的方法相比，这种方法构造的LDPC码不仅可以检突发长度小于校验矩阵秩的突发错误，并且保持纠随机错误性能不变。     

低功耗异步LDPC解码器运算通路设计

本文设计了异步LDPC解码器运算通路,利用异步电路减少信号到达时间不一致引起的毛刺和时钟引起的功耗.利用输入数据的统计特性设计了运算通路中的主要运算单元,减少了冗余运算.本文还实现了同步运算通路和基于门控时钟的运算通路作为比较.三种设计采用相近的架构,在0.18μm CMOS工艺下实现相同的功能.仿真结果表明,提出的异步设计功耗最小,相比于同步设计和基于门控时钟设计,分别节省了42.0%和32.6%的功耗.虽然性能稍逊于同步设计,但优于门控时钟设计.其中,同步设计的延时是1.09ns,基于门控时钟的设计延时是1.61ns,而异步设计则是1.20ns.     

5G新空口LDPC码的快速编码算法

低密度奇偶校验码(Low Density Parity Code,LDPC)已被用于5G系统,且TS 38.212标准规定了5G新空口(New Radio,NR)LDPC码的构造流程,但没有给出具体的编码算法和解速率匹配方法.针对该问题,首先分析了NR LDPC码的基矩阵的结构特征,给出了线性复杂度的编码算法;其次讨论...     

FPGA implementation of highly secure,hardware‐efficient QC‐LDPC code–based nonlinear cryptosystem for wireless sensor networks

This paper presents the design and implementation of an integrated architecture for embedding security into quasi‐cyclic (QC) low‐density parity‐check (LDPC) code–based cryptographic system through a nonlinear function of low hardware complexity. Instead of using standard S ‐boxes for implementation of nonlinear function, this paper considers a method on the basis of maximum length cellular automata (CA), so that enhanced security can be achieved with simple hardware structure. The proposed system adopts a lightweight random bit stream generator on the basis of linear feedback shift register (LFSR) for generating random error vectors, so that a large number of vectors with very good cryptographic properties can be made available with low hardware cost. Different permutation patterns generated for different message blocks help to provide good degrees of freedom for tuning security with reasonable key size. The hardware architecture for the proposed system is developed and validated through implementation on Xilinx Spartan 3S500E. Analytical and synthesis results show that the proposed scheme is lightweight and offers very high security through continuously changing parameters, thus making it highly suitable for resource‐constrained applications.     

外部信息自适应更新的SCMA系统译码方案

现有上行稀疏码多址接入（Sparse Code Multiple Access,SCMA）通信系统采用的译码算法中,基于串行策略的消息传递算法（Message Passing Algorithm,MPA）因其在每次迭代过程只选择单个消息进行更新,存在着收敛速度较慢等问题。针对以上问题,提出外部信息自适应更新的MPA算法,每次迭代过程中自适应选取多个残差值较大、相互独立的节点,更新其外部信息以达到提高计算效率的目的。仿真结果表明,该算法可有效提升译码性能,在计算复杂度与译码性能之间取得了较好的平衡。