空间单粒子翻转甄别与定位系统原理样机的设计及试验

单粒子翻转（SEU）是影响空间电子设备可靠性的重要因素,本文提出了一种SEU甄别与定位技术方法,研制了原理样机。硅探测器与辐照敏感器件在垂直方向相互临近安装,粒子入射到硅探测器的位置区域与目标辐照器件单粒子翻转的物理位置相对应。采用波形数字化技术实现了多道粒子甄别与能量信号测量,通过数据回读比较法实现了SRAM器件翻转逻辑定位检测。根据实验室测试和单粒子辐照试验结果,可探测高能粒子的LET≥6?06×10-3 MeV·cm2/mg,入射粒子的位置分辨率优于5 mm,最大计数率≥10 000 s-1,SRAM器件的SEU巡检周期时间分辨率为13?76 ms。通过掌握大容量SRAM型器件的SEU甄别与定位及其辐射环境感知能力,有助于提升空间电子设备的在轨工作性能。     

抗辐射加固高压NMOS器件的单粒子烧毁效应研究

由于施加高栅极工作电压,使得器件容易发生重离子辐射损伤效应,其中,重大的重离子辐射损伤效应是单粒子栅穿效应（SEGR）和单粒子烧毁效应（SEB）。本文介绍了抗辐射加固高压SOI NMOS器件的单粒子烧毁效应。基于抗辐射加固版图和p型离子注入工艺,对高压器件进行抗辐射加固,提高器件的抗单粒子烧毁能力,并根据电路中器件的电特性规范,设计和选择关键器件参数。通过仿真和实验结果研究了单粒子烧毁效应。实验结果表明,抗辐射加固器件在单粒子辐照情况下,实现了24 V的高漏极工作电压,线性能量传输（LET）阈值为835 MeV·cm2/mg。     

CMOS APS光电器件单粒子效应重离子试验研究

基于新型互补金属氧化物半导体有源像素传感器(ComplementaryMetalOxideSemiconductorActive Pixel Sensor, CMOS APS)光电器件的内部结构特点,分析了重离子对CMOS APS光电器件的影响,以及CMOS APS光电器件的单粒子效应敏感性。结合CMOS APS光电器件的结构特点和辐射影响分析,形成了基于监测数据逻辑状态和图像"白点"相结合的测试方法。在此基础上,利用重离子加速器进行了单粒子效应模拟试验。试验结果表明:当重离子线性能量传输(Linear Energy Transition, LET)低于9.01 MeV·cm2·mg-1时,像素阵列没有出现扰动现象,仅是电荷在像素阵列的不断累积。同时,试验获得单粒子翻转(Single Event Upset, SEU)饱和截面对应的LET值约为42.0 MeV·cm2·mg-1。     

光电耦合器的单粒子瞬态脉冲效应研究

利用脉冲激光模拟单粒子效应实验装置研究光电耦合器HCPL-5231和HP6N134的单粒子瞬态脉冲(SET)效应.实验获得了相关器件的单粒子瞬态脉冲波形参数与等效LET的关系,并甄别出器件SET效应的敏感位置,初步分析了SET效应产生的机理.利用脉冲激光测试了光电耦合器的SET宽度与等效LET的关系,并尝试测试了两种光电耦合器的SET效应的截面,其中,HCPL-5231的实验结果与其他文献利用重离子加速器得到的数据符合较好,验证了脉冲激光测试器件单粒子效应的有效性.     

光电耦合器4N49单粒子瞬态脉冲效应的试验研究

通过脉冲激光模拟单粒子效应,对光电耦合器4N49的单粒子瞬态脉冲（SET）效应进行了试验研究。在10V工作电压下,获取了4N49在特定线性能量传输（LET）值下的SET波形特征及其变化规律,得到了器件SET效应的等效LET阈值为10MeV•cm²•mg^-1,而饱和截面数值则高达1.2×10^-3cm²。试验验证了4N49的SET效应对后续数字电路的影响状况,定量研究了SET效应减缓电路的有效性,通过设计合理的电路参数可将器件在5V工作电压下的SET效应阈值由7.89MeV•cm²•mg^-1提高至22.19MeV•cm²•mg^-1。4N49的SET效应试验研究为光电耦合器SET效应的测试及防护措施的有效性验证提供了新的试验方法。     

LiF-TLD的响应对致电离粒子LET的依赖性初步实验研究

对LiF热释光探测器（TLD）的响应对致电离粒子的LET的依赖性进行了初步实验研究。用作实验研究的粒子主要是中子,包括热中子和由7Li(p,n)7Be、T（p,n）3He核反应生成的中能中子、快中子（0.018～0.945MeV）及14MeV中子。实验结果表明：LiF(Mg、Cu、P)-TLD的响应对致电离粒子LET的依赖性是显著的。对于较高能量的中子,由LiF-TLD产生的热释光量仅与6Li、7Li在LiF-TLD中导致的吸收剂量相对应,这与某些文献的报道相一致。     

单粒子效应研究中提高LET值的特殊方法

为满足单粒子效应研究对更大的线性能量转移 (LET)值 ( 80MeV·mg- 1 ·cm- 2 以上 )的要求 ,在HI 1 3串列加速器上发展了用于高剥离态离子的加速、引出及 0°束Q3D磁谱仪焦面辐照技术。当用高剥离态 (Q1 =1 5 ,Q2 =2 5 )重离子1 2 7I 45°倾斜入射时 ,已得到的LET值为 86 7MeV·mg- 1 ·cm- 2 ,Si中射程约 2 0 μm。使用谱仪的散焦特性 ,辐照束的强度、均匀性和束斑大小可在大范围内调整 ,注量率为几十至 5× 1 0 5s- 1 ·cm- 2 ,均匀性好于 90 % ,束斑为1 0mm到5 0mm ,其纯度好于 98%。     

高电荷态重离子束流产生技术的研究

为了提高北京HI-13串列加速器束流的硅中射程和LET值,本文开展了高电荷态束流引出技术及pA级弱束流诊断技术研究。采用电刚度和磁刚度模拟技术,配合pA级弱束流束斑观测和束流强度监测技术,获得能量360 MeV、峰总比80%的¹⁹⁷Au离子束流,其在Si中的表面LET为86.1 MeV•cm²•mg^-1、射程为30.1 μm,满足单粒子效应（SEE）实验的要求,拓展了北京HI-13串列加速器上单粒子效应实验所用离子的能量和LET值范围。     

脉宽调制器单粒子效应测试系统研制

本文在分析脉宽调制器(PWM)单粒子效应主要失效模式的基础上,研制了具备频率异常测试、占空比异常测试和参考电压测试功能的PWM单粒子效应测试系统,并在中国原子能科学研究院HI-13串列加速器上开展了单粒子效应试验。试验结果表明:单粒子效应会导致PWM输出信号的脉冲丢失和占空比改变,脉冲丢失时间和占空比改变的持续时间有时可达数ms;UC1825AJ型PWM的单粒子效应LET阈值约为4.4MeV·cm2·mg-1,UC1845AJ型PWM的抗单粒子性能受工艺批次的影响较大。     

LiF—TLD的响应对致电粒子LET的领带性初步实验研究

对LiF热释光探测器（TLD）的响应对致电离粒子的LET的依赖性进行了初步实验研究。用作实验研究的粒子主要是中子,包括热中子和由^7Li(p,n)^7Be、T(p,n)^3He核反应生成的中能中子、快中子（0．018－0．945MeV）及14MeV中子。实验结果表明：LiF(Mg、Cu、P)－TLD的响应对致电离粒子LET的依赖性是显著的。对于较高能量的中子,由LiF-TLD产生的热释光量仅与^6Li、^7Li在LiF-TLD中导致的吸收剂量相对应,这与某些文献的报道相一致。     

Verification of SEU resistance in 65 nm high-performance SRAM with dual DICE interleaving and EDAC mitigation strategies

A dual double interlocked storage cell(DICE)interleaving layout static random-access memory(SRAM)is designed and manufactured based on 65 nm bulk com-plementary metal oxide semiconductor technology.The single event upset(SEU)cross sections of this memory are obtained via heavy ion irradiation with a linear energy transfer(LET)value ranging from 1.7 to 83.4 MeV/(mg/cm2).Experimental results show that the upset threshold(LETth)of a 4 KB block is approximately 6 MeV/(mg/cm2),which is much better than that of a standard unhardened SRAM with an identical technology node.A 1 KB block has a higher LETth of 25 MeV/(mg/cm2)owing to the use of the error detection and correction(EDAC)code.For a Ta ion irradiation test with the highest LET value(83.4 MeV/(mg/cm2)),the benefit of the EDAC code is reduced significantly because the multi-bit upset pro-portion in the SEU is increased remarkably.Compared with normal incident ions,the memory exhibits a higher SEU sensitivity in the tilt angle irradiation test.Moreover,the SEU cross section indicates a significant dependence on the data pattern.When comprehensively considering HSPICE simulation results and the sensitive area distri-butions of the DICE cell,it is shown that the data pattern dependence is primarily associated with the arrangement of sensitive transistor pairs in the layout.Finally,some sug-gestions are provided to further improve the radiation resistance of the memory.By implementing a particular design at the layout level,the SEU tolerance of the memory is improved significantly at a low area cost.Therefore,the designed 65 nm SRAM is suitable for electronic systems operating in serious radiation environments.     

欧空局单粒子监督器在北京HI-13串列加速器上的单粒子效应校核实验

为检验北京HI-13串列加速器单粒子效应(SEE)实验能力与数据测量的可靠性,利用束流参数校核系统——欧空局单粒子监督器进行了单粒子效应校核实验。实验使用C、F、Cl、Cu 4种离子辐照单粒子监督器,通过改变入射角度获得了有效LET值在1.8~67.4 MeV·cm~2·mg~(-1)之间的单粒子翻转(SEU)截面数据。实验结果与比利时HIF、芬兰RADEF装置上测得的截面数据一致性较好,证实了北京HI-13串列加速器单粒子效应实验束流参数测量的准确性及截面数据测试的可靠性。     

Single event effects in static and dynamic registers in a 0.25μm CMOS technology

We have studied single event effects in static and dynamic registers designed in a quarter micron CMOS process. In our design, we systematically used guardrings and enclosed (edgeless) transistor geometry to improve the total dose tolerance. This design technique improved both the SEL and SEU sensitivity of the circuits. Using SPICE simulations, the measured smooth transition of the cross-section curve between LET threshold and saturation has been traced to the presence of four different upset modes, each corresponding to a different critical charge and sensitive area. A new architecture to protect the content of storage cells has been developed, and a threshold LET around 89 MeV cm ² mg^-1 has been measured for this cell at a power supply voltage of 2 V     

CMOS器件单粒子效应电路级建模与仿真

单粒子效应电路级建模与仿真是近年来的热点问题。为实现更高的准确度和更精细的机制分析,研究了单粒子瞬态受重离子入射位置的影响并解析建模,基于纳米尺度测试芯片的辐照试验结果验证了仿真方法的准确性。以此为基础开发了瞬时辐射效应仿真软件TREES,其输入文件为GDSII格式的版图,软件中通过解析版图提取所有有源区的形状、尺寸信息。软件还包括其他用户自定义选项,包括重离子LET值、待分析区域、激励设置等。输出文件包括对应单次入射的波性文件、单粒子效应敏感区热点图、单粒子效应截面数据等。软件第1版实现了与商用设计流程相集成,可作为Cadence工具栏中的嵌入式软件。软件第2版为不依赖于上下游商业软件的独立软件。本工作可用于评价单元电路或中小规模单粒子效应敏感性,对于熟悉电路级仿真的设计人员,可用于在设计阶段快速评价集成电路的抗辐射加固性能。     

Heavy ion-induced single event upset sensitivity evaluation of 3D integrated static random access memory

Heavy ion-induced single event upsets(SEUs)of static random access memory(SRAM), integrated with three-dimensional integrated circuit technology, are evaluated using a Monte Carlo simulation method based on the Geant4 simulation toolkit. The SEU cross sections and multiple cell upset(MCU) susceptibility of 3D SRAM are explored using different types and energies of heavy ions.In the simulations, the sensitivities of different dies of 3D SRAM show noticeable discrepancies for low linear energy transfers(LETs). The average percentage of MCUs of 3D SRAM increases from 17.2 to 32.95%, followed by the energy of ~(209)Bi decreasing from 71.77 to 38.28 MeV/u. For a specific LET, the percentage of MCUs presents a notable difference between the face-to-face and back-toface structures. In the back-to-face structure, the percentage of MCUs increases with a deeper die, compared with the face-to-face structure. The simulation method and process are verified by comparing the SEU cross sections of planar SRAM with experimental data. The upset cross sections of the planar process and 3D integrated SRAM are analyzed. The results demonstrate that the 3D SRAM sensitivity is not greater than that of the planar SRAM. The 3D process technology has the potential to be applied to the aerospace and military fields.     

Single event upset immunity of strontium bismuth tantalateferroelectric memories

An embedded 1 Kbit nonvolatile (NV) serial memory manufactured with strontium bismuth tantalate (SBT) ferroelectric (FE) technology was shown to be immune to effects of heavy ion irradiation. The memories did not lose any data in the non-volatile mode when exposed to xenon (maximum effective LET of 128 MeV-cm²/mg and a total fluence of 1.5×10⁷ ions/cm²). The ferroelectric memories also did not exhibit any loss in the ability to rewrite new data into the memory bits, indicating that no significant degradation of the FE dipoles occurred as a result of the heavy ion exposure. The fast read/write times of FE memories also means that single event gate rupture is unlikely to occur in this technology     

Analysis of single-event transient sensitivity in fully depleted silicon-on-insulator MOSFETs

Based on 3 D-TCAD simulations, single-event transient(SET) effects and charge collection mechanisms in fully depleted silicon-on-insulator(FDSOI) transistors are investigated. This work presents a comparison between28-nm technology and 0.2-lm technology to analyze the impact of strike location on SET sensitivity in FDSOI devices. Simulation results show that the most SET-sensitive region in FDSOI transistors is the drain region near the gate. An in-depth analysis shows that the bipolar amplification effect in FDSOI devices is dependent on the strike locations. In addition, when the drain contact is moved toward the drain direction, the most sensitive region drifts toward the drain and collects more charge. This provides theoretical guidance for SET hardening.