小数_N分频锁相频率合成器技术

本文介绍加快锁相环转换时间一种方法－小数－Ｎ颁频锁相环频率合成器技术,并利用ＦＨＩＬＩＰＳ公司ＳＡ７０２５器件进一步说明小数－Ｎ分频工作原理。     

用大规模锁相环集成电路MC145146实现小数分频

介绍了一种利用大规模锁相环集成电路MC145146实现小数分频的原理,并用MC12013作前置分频器进行了实验,证明了其正确性。     

小数分频在吞脉冲频率合成器中的实现

结合ANYO公司的LC72130的具体电路,介绍了吞脉冲与小数分频的概念。并由此推导出了吞脉冲锁相频率合成器的输出频率凡、双模前置分频器的输出频率FP和参考频率FR之间的关系式。应用此关系式提出了一种新的小数分频理论及实现电路框图,使单环锁相频率合成器的平均分频比变为小数,从而可以解决频率合成器中高鉴相频率和高分辨率之间的矛盾。     

小数分频技术在通信领域中的应用

介绍了锁相环中两种小数分频技术方案。这些技术可以用在多种频段空间内的合成器中，并可使相位噪声降低。     

一种100～200MHz的小数分频锁相环

本文介绍了一种小数分频环的原理,并对100～200MHz,参考频率为100kHz、分辨率为100Hz的小数环进行了实验,证明了此方法的可行性.     

小数分频及相位补偿

提出二种小数分频器和二种相位补偿电路,介绍了电路实现和对环路性能的改善程度,线路简单,程控方便,集成度高。     

一种级联型小数分频调制电路的设计实现

本文设计并实现了一个三阶的级联型调制电路用于实现5.8GHz小数分频锁相环。调制电路通过字长15bit的累加器作为基本单元,利用三级累加器的溢出值组成锁相环分频器的控制字序列。仿真结果表明,调制电路能够按照设计要求输出正确的分频序列,在分频比区间[0.1,0.95]内平均误差仅为0.4%。0.18μm CMOS工艺下,基于该调制电路实现的5.8GHz锁相环芯片能够准确锁定目标频点,相噪声性能为-109dBc/Hz。     

吞脉冲多位小数分频器

本文介绍了多位小数分频的基本原理,详细介绍了一种吞脉冲三位小数分频器方案。经过实验证明,此方案设计合理,具有较高的实用价值。     

基于DVFS的移动通信终端省电方案

本文首先概述了TD-SCDMA终端的耗电特性,接着对动态电压与频率调节技术进行了分析,最后运用动态管理技术提出了一种基于动态电压与频率调节技术的终端省电方案,有效地延长了终端的工作时间.     

Influence of charge trapping on oxide scaling down

The aim of this work is the characterization, in terms of trapped charge and charge to breakdown, of the quality of an oxide with reduced thickness. A comparison between two evaluation methods, the widely used exponentially ramped current stress (ERCS) and the constant current stress (CCS), is established obtaining contradictory results. A measurement of the charge trapped in the oxide bulk is performed by sensing the modification of the Fowler–Nordheim barrier under constant current stress. Using this technique it is possible to correlate the charge trapping characteristics with the charge to breakdown and to explain the inconsistencies.     

Improved nonlinear frequency scaling algorithm for squint FMCW SAR

An improved nonlinear frequency scaling algorithm is proposed to process squint frequency modulated continuous wave synthetic aperture radar data. The algorithm uses a decimation technique to decrease the bandwidth of the signal introduced by the frequency scaling operation, effectively removing the range frequency aliasing. Simulated results show the validity of the algorithm.     

A 32-bit PowerPC system-on-a-chip with support for dynamic voltage scaling and dynamic frequency scaling

A PowerPC system-on-a-chip processor which makes use of dynamic voltage scaling and on-the-fly frequency scaling to adapt to the dynamically changing performance demands and power consumption constraints of high-content, battery powered applications is described. The PowerPC core and caches achieve frequencies as high as 380 MHz at a supply of 1.8 V and active power consumption as low as 53 mW at a supply of 1.0 V. The system executes up to 500 MIPS and can achieve standby power as low as 54 /spl mu/W. Logic supply changes as fast as 10 mV//spl mu/s are supported. A low-voltage PLL supplied by an on-chip regulator, which isolates the clock generator from the variable logic supply, allows the SOC to operate continuously while the logic supply voltage is modified. Hardware accelerators for speech recognition, instruction-stream decompression and cryptography are included in the SOC. The SOC occupies 36 mm/sup 2/ in a 0.18 /spl mu/m, 1.8 V nominal supply, bulk CMOS process.     

A robust approach for high resolution frequency estimation

A robust estimation method for frequencies of received signals is considered. The influence function of a robust estimate is derived for the sinusoidal signals. The variance of the robust estimate is also derived using the influence function. It is found that the robust estimate attains the Cramer-Rao lower bound (CRLB) for the contaminated Gaussian distribution. It is of order O(N^-3) and is close to the CRLB for the perfect Gaussian distribution. The authors introduce some basic definitions for the high-resolution frequency estimation method and prove that the robust estimate has the high-resolution property. This property is also confirmed by numerical simulations     

Some aspects of the analysis of experimental data for short-term frequency scaling

Over one hundred hours of British Telecom's half-second event data from the OTS and ATS-6 satellites has been analysed with respect to short-term frequency scaling of attenuation. The ratio of attenuation at two frequencies is particularly vulnerable to system effects and noise. Data analysis techniques are discussed and it is shown that a least-squares analysis is not suitable when the time period is short. Appreciable variation occurred in the mean value of the short-term ratio from one event to another. Only on a few occasions did significant changes occur during an event. Simultaneous data from other equipment gives confidence that these changes are due to propagation effects.     

Constant voltage scaling of FETs for high frequency and high power applications

A constant voltage scaling scheme is examined for the enhancement of frequency and power performance of FETs. For low electric fields, this scheme is self-consistent within Shockley's formulation and improves the overall frequency and power performance figure of merit by a factor of κ⁶ with a κ times reduction in the device area. For high electric fields, the improvement is reduced to κ³ times due to the velocity saturation effect. Reduced breakdown voltage further limit the improvement.     

声光频谱仪频率分辨率判断方法研究

频率分辨率是声光频谱仪的一个重要指标。声 光布拉格器件实际衍射光宽度远大于 理论宽度,因 此对声光频谱仪频率分辨率的估计需根据实际衍射光的宽度来判断。本文在现有光学测试平 台下,对单频信号 产生的衍射光,通过高斯函数建立数学模型,利用二分迭代法得到两高斯函数在满足瑞利 判据条件下可 分辨的最小间距。根据光路系统衍射光偏转距离与对应频率带宽,估计系统频率分辨率与 实测系统频率分辨率基本一致。研究结果表明,本文方法能有效估计声光频谱仪的频率分辨 率。     

A high resolution frequency multiplier for clock signal generation

This paper presents a high resolution frequency multiplier (FMUL) with the ability to multiply frequency with a programmable high multiplication factor, in the order of 10²-10⁴ and of the form N/M. It was designed for chip-sets that use a real time clock (32768 Hz) for power-save operation, and an additional high-frequency oscillator, in the range of 40-60 MHz, for regular operation. Using the FMUL spares the need for the additional high-frequency oscillator. The FMUL's frequency resolution is 100 ppm, and its jitter is less than 200 ps. The circuit is designed to work with 25 V supply voltage. It is implemented in a standard 0.8 pm N-well CMOS process, and its area is 0.48 mm²     

The impact of scaling down to deep submicron on CMOS RF circuits

Recent papers reporting CMOS RF building blocks have aroused great expectations for RF receivers using deep-submicron technologies. This paper examines the trend in CMOS scaling, in order to establish the required current levels and achievable performance for different feature sizes, if robust, easily manufacturable designs are to be implemented for cellular applications. The boundary conditions (system-level constraints) for such designs, in terms of the number of trimmed and untrimmed external components and the roles they play in relaxing active circuit requirements, are emphasized throughout to make comparison of active RF circuits meaningful. At 1 GHz, 0.25-μm CMOS appears to be the threshold for robust, low-NF RF front ends with current consumption competitive with today's BJT implementations