ULSI Cu互连CoSiN扩散阻挡薄膜的研究

CoSiN薄膜可以作为超大规模集成电路Cu布线互连材料使用。利用磁控溅射技术制备了CoSiN/Cu/CoSiN/SiO2/Si薄膜,利用四探针测试仪、薄膜测厚仪、原子力显微镜、X射线光电子能谱仪等来检测多层膜电阻率、薄膜厚度、表面形貌、元素含量及价态等。考察亚45 nm级工艺条件下CoSiN薄膜对Cu的扩散阻挡性能。实验结果表明,在氩气气氛条件下经500℃,30 min热退火处理后多层膜的电阻率和成分没有发生明显变化,CoSiN薄膜能够保持良好的铜扩散阻挡性能;经600℃,30 min热退火处理后,Cu大量出现在表面,CoSiN薄膜对Cu失去扩散阻挡性能。     

一种低成本的硅垂直互连技术

采用KOH刻蚀工艺制作硅垂直互连用通孔,淀积SiO2作为硅垂直互连的电绝缘层,溅射Ti和Cu分别作为Cu互连线的黏附层/扩散阻挡层和电镀种子层.电镀10μm厚的Cu作为硅垂直互连的导电层.为实现金属布线的图形化,在已有垂直互连的硅片上试验了干膜光刻工艺.采用化学镀工艺,在Cu互连线上沉积150～200 nm厚的NiMoP薄膜作为防止Cu腐蚀和Cu向其上层介质扩散的覆盖层.高温退火验证了Ti阻挡层和NiMoP覆盖层的可靠性.     

基于LTCC基板BCB/Cu薄膜混合多层互连技术研究

针对微系统小型化集成对高性能成膜基板需求,研究了基于LTCC基板的BCB/Cu薄膜多层互连关键技术及过程控制要求。提出一种高可靠"T"型界面互连方式的薄膜磁控溅射Cr/Cu/Cr和Cr/Pd/Au复合膜层结构及其制备方法。研究了LTCC基板收缩率偏差、LTCC-薄膜界面缺陷及粗糙度、BCB介质膜固化应力、介质膜金属化的应力等因素对厚薄膜混合基板质量的影响。制备的12层厚薄膜混合基板(10层LTCC基板,2层薄膜布线) 60片,100%全部通过GJB2438 C.2.7成膜基片评价考核要求,相比LTCC基板,布线密度提高4倍,尺寸缩小40%。     

磁控溅射的TaN薄膜的扩散阻挡性能

用反应磁控溅射方法在SiO2/Si(100)衬底和Cu薄膜间溅射一层TaN阻挡层,测试不同N气分压及热处理温度下Cu/TaN/SiO2/Si薄膜的显微结构和电阻特性.同时利用微细加工技术加工了镂空的Cu互连叉指测试结构,研究了TaN薄膜在镂空的铜互连结构中的扩散阻挡性能.结果发现,在退火温度不超过400 ℃时,薄膜电阻率均低于80μΩ·cm,而当溅射N分压超过10%,退火温度超过400℃时,薄膜电阻率很快上升.低N气分压下(≤10%)溅射时,即使退火温度达到600 ℃,薄膜电阻基本不变.     

Ni80Fe20/Cu基磁性多层膜和自旋阀的微结构

用高分辨电子显微学及平行电子能量损失谱方法研究了Ni80Fe20/Cu基磁性多层膜和自旋阀的显微结构.高分辨像显示,磁性多层膜及自旋阀均具有沿薄膜生长方向的柱晶结构.Ni,Fe,Cu和Mn元素的成分分布图显示,柱晶内仍保持完整的层状结构.沿薄膜生长方向的自旋阀元素分布曲线分析表明,NiFe层中的Ni元素沿柱晶晶界向相邻Cu层扩散.讨论了这些低维磁电子学材料的显微结构对磁输运性能的影响.     

LTCC基板上薄膜多层布线工艺技术

LTCC基板上薄膜多层布线工艺是MCM-C/D多芯片组件的关键技术。它可以充分利用LTCC布线层数多、可实现无源元件埋置于基板内层、薄膜细线条等优点,从而使芯片等元器件能够在基板上更加有效地实现高密度的组装互连。文章介绍了LTCC基板上薄膜多层布线工艺技术,通过对导带形成技术、通孔柱形成技术和聚酰亚胺介质膜技术的研究,解决了在LTCC基板上薄膜多层布线中介质膜"龟裂",通孔接触电阻大、断路,对导带的保护以及电镀前的基片处理等工艺难题。     

Microstructure in Ni_(80) Fe_(20)/Cu magneticmultilayers and spin valve

用高分辨电子显微学及平行电子能量损失谱方法研究了Ni80Fe20Cu基磁性多层膜和自旋阀的显微结构。高分辨像显示,磁性多层膜及自旋阀均具有沿薄膜生长方向的柱晶结构。Ni,Fe,Cu和Mn元素的成分分布图显示,柱晶内仍保持完整的层状结构。沿薄膜生长方向的自旋阀元素分布曲线分析表明,NiFe层中的Ni元素沿柱晶晶界向相邻Cu层扩散。讨论了这些低维磁电子学材料的显微结构对磁输运性能的影响。     

MCM-C中厚膜电阻的寿命分布及退化规律的研究

重点研究了MCM-C基板的可靠性，包括厚膜电阻、基板布线以及互连通孔。试验采取加温度应力与电应力的双应力加速寿命试验。试验中发现，厚膜电阻的退化先于基本布线和互连通孔，故厚膜电阻的退化在MCM-C基板可靠性中起主要的作用；重点讨论了厚膜电阻在热电应力下的失效规律及寿命分布，试验结果表明厚膜电阻的寿命分布服从威布尔分布。     

混合多层互连技术的研究

本文主要通过多层陶瓷与薄膜多层界面状况，通孔的形状及通孔填充条件，对混合多层布线中的互连技术进行探讨，论述了实验中遇到的问题及相应的解决方法。     

VLSI／ULSI集成电路多层金属互连技术

随着半导体微电子器件制造技术迅速发展，多层金属互连技术对于提高器件集成度、速度和可靠性更为重要，需要不断发展新型多层金属互连结构、材料和工艺，本文介绍近年正在发展的一些多层金属互连新技术，如多层复合金属化体系、Ｃｕ等新型薄膜互连材料，ＴｉＮ在互连技术中的多种用途，新的介质薄膜材料及工艺、平坦化技术等。     

掺Na制备柔性聚酰亚胺衬底CIGS薄膜太阳电池

研究了Na掺入对低温沉积柔性聚酰亚胺(PI)衬底Cu(In,Ga)Se2(CIGS)薄膜的结构和电学特性影响。研究结果表明:Na元素的掺入使Ga元素的扩散受到了阻滞,但对CIGS薄膜晶粒尺寸没有明显的影响,少量的Na可提高CIGS薄膜的载流子浓度和降低电阻率;Na的掺入可明显提高CIGS薄膜太阳电池的器件特性,通过优化掺Na工艺,制备的柔性PI衬底—CIGS薄膜太阳电池的最高转换效率达到10.4%。     

Sol-gel-derived ZnO/Cu/ZnO multilayer thin films and their optical and electrical properties

Sol-gel preparation of transparent conducting ZnO/Cu/ZnO multilayer thin films has been investigated. CuO thin films were deposited on glass substrates via a dip-coating method. The CuO thin films were further subjected to reductive annealing in hydrogen to form highly conductive Cu thin films with sheet resistances as low as 10 Ω/□. ZnO/Cu/ZnO multilayers were successfully prepared in a similar way by reducing ZnO/CuO/ZnO. The sheet resistance of the ZnO/Cu/ZnO multilayer thin films is about 10 kΩ/□, which is much higher than that of the pure Cu thin films. The formation of large discrete Cu crystallites in the multilayers explains the poor electrical conductivity of the sol-gel-derived ZnO/Cu/ZnO multilayers.     

Adhesion studies of CVD copper metallization

The adhesion of chemical vapor deposition (CVD) Cu thin films to various barriers was observed to improve with a post-deposition anneal or a physical vapor deposition (PVD) Cu flash layer on the barrier before depositing CVD Cu. The ambient exposure of the barrier before the deposition of CVD Cu has been observed to lead to degradation of adhesion in both CVD Cu seed and CVD/PVD Cu high vacuum integrated metallization schemes. The integrated CVD and PVD Cu deposition scheme exhibits better adhesion due to the inherent annealing provided during the PVD deposition which is carried out at temperatures between 300 and 400°C. We have evaluated both qualitative and quantitative tests — tape test, Stud pull test and 4-point bend test — in understanding adhesion and observed that each of these tests give different details of interface breakdown.     

辐照对聚酰亚胺基板铜薄膜金属化TiN阻挡层的影响

采用物理气相沉积方法在聚酰亚胺基板上沉积Cu薄膜,利用TiN阻挡Cu元素向聚酰亚胺基板内部扩散。研究了在60Co-g射线辐照条件下,TiN阻挡层的阻挡效果,扫描俄歇微探针谱图分析表明:TiN层可以有效地阻挡Cu元素向聚酰亚胺基板内的扩散。当照射剂量大于2105 Gy后,TiN失去阻挡Cu元素扩散的效果。     

Cr/Cu/Al/Cr薄膜电极的防氧化性能

采用Al作为Cu导电层的主要防氧化保护层,在普通浮法玻璃上利用磁控溅射和湿法刻蚀技术制备Cr/Cu/Al/Cr复合薄膜及其电极,研究不同的热处理温度对复合薄膜及其电极的结构、表面形貌和导电性能的影响。由于有Al层作为保护层,在热处理过程中,Al先与穿过Cr保护层的氧进行反应,从而可以更有效地保护Cu膜层在较高的温度下不被氧化,所制备的薄膜在经过600℃的热处理之后仍然具有较好的导电性能。而对于Cr/Cu/Al/Cr电极,侧面裸露的金属层在热处理过程中的氧化是其导电性能逐渐下降的主要原因,退火温度超过500℃之后,电极侧面裸露部分的氧化范围不断往电极的中间扩散,导致了薄膜电极导电性能显著恶化。虽然如此,Cr/Cu/Al/Cr薄膜电极在430℃附近仍然具有较好的导电性能,电阻率为7.3×10-8Ω.m,符合FED薄膜电极的要求。以此薄膜电极构建FED显示屏,通过发光亮度均匀性的测试验证了Cr/Cu/Al/Cr电极的抗氧化性。     

Fabrication and characterization of low-cost ultrathin flexible polyimide interposer

A passive interposer, which is a way to bridge the feature gap between the integrated circuit (IC) and the package substrate, is a key building block for high performance 3-D systems. In this paper, polyimide (PI) is proposed as an alternative to glass and silicon based interposers for cost-effective 2.5-D/3-D IC integration. The development of interconnect technology using an ultrathin flexible polyimide interposer (UFPI) for 2.5-D/3-D packaging applications is described in detail. A semi-additive process consisting of copper seed layer deposition, photolithography, and electrolytic copper pattern plating is used for fabricating a double-sided flexible fan out interposer. A UFPI with electrodeposited micro-scale copper (Cu) fine patterns and laser drilling microvia is investigated using a scanning electron microscope (SEM), energy-dispersive spectrometry (EDS), X-ray spectrometry, and an optical 3-D profilometer. The UFPI with fine pitch on 12.5 μm thin PI substrates has been demonstrated. The result is a proof-of-concept to exploit the opportunities of cost-effective 2.5D flexible interposer production.     

Robust Low Oxygen Content Cu Alloy for Scaled-Down ULSI Interconnects Based on Metallurgical Thermodynamic Principles

A low oxygen content (LOC) CuAl alloy with no barrier metal (Ta) oxidation was obtained using an oxygen absorption process based on metallurgical thermodynamic principles. LOC CuAl dual damascene interconnects (DDIs) were successfully implemented into 45-nm-node LSIs with 140-nm-pitched lines and 70-nm-diameter $(phi)$ vias. An oxygen absorber of very thin Al film, which was deposited on an electrochemically deposited (ECD) Cu film, captured the oxygen atoms in the ECD Cu due to its larger negative change in the standard Gibbs-free energy of oxidation than in the Cu and the barrier (Ta), preventing the Ta barrier from oxidizing during high-temperature annealing. The high-quality Cu/barrier interface in the LOC CuAl DDIs remarkably improved the via reliability against stress-induced voiding and electromigration. No reliability degradation of the 70-nm-$phi$ vias was observed in the 45-nm-node LOC CuAl DDIs, while keeping the scalability from the 65-nm-node generation.      

Stability Analysis of Cr-MIS Solar Cells

The 50 ? Cu/30 ? Cr/20 ? SiO,/Si solar cell structure has been analyzed by Auger, ESCA and ellipsometer measurements. An oxidation-reduction failure mechanism has been proposed for shelf-life degradation, and experimental evidence for such behavior is presented. The effect of this degradation is a decrease in the oxide thickness at the interface bringing about a photovoltaic performance degradation. The performance degradation involves a typical change in Voc, from about 0.55 V to 0.52 V with little or no change in Jsc or fill factor. The performance of all Cr-MIS devices then stabilizes when a thermodynamic equilibrium is attained. The light-effect degradation is more complex and the rearrangement of bonding in the interface oxide and at the SiOx/Si interface might reduce the rate of degradation. The Cr-MIS solar cell should be designed with an oxide thickness more than the static optimum value to allow for a decrease in oxide thickness to the optimum value.     

聚酰亚胺衬底CIGS薄膜附着性的改善

为改善聚酰亚胺(PI)衬底Cu(In,Ga)Se2(CIGS)薄膜的附着性,提出在NaF沉积前预先在Mo层上蒸发沉积100nm厚的In-Ga-Se(IGS)薄膜的新掺Na工艺。结果表明:这种IGS-NaF-CIGS式新工艺可显著改善CIGS薄膜的附着,而且CIGS薄膜材料和器件特性没有显著退化;新工艺促进了NaInSe2的生成,减少了In-Se二元相的残余,但也造成薄膜电阻率的升高和电池填充因子的下降,进而导致制备的PI衬底CIGS电池的转换效率由9.8%降至9.0%。综合考虑附着性的改善和器件效率的轻微下降,新工艺利大于弊,有很好的应用前景。     

Delamination of polyimide/Cu films under mixed mode loading

Organic passivation layers are used as coatings in semiconductor devices for protection of metallization films against a variety of environmental effects. Polyimides (PI) have been used successfully as conformable protection layers on aluminium and also recently on copper metallization. While adhesion properties of Cu interconnects to compliant polymer substrates have been investigated so far, studies on PI/Cu passivation layers are scarce. In this study the adhesion strength of polyimide passivation layer to Cu film stacks on Si has been studied by using different fracture mechanic methods including four point bending, double cantilever beam and single lap shear tests. The focus is investigation of the dependency of the critical energy release rate to the mode mixity obtained by different testing techniques and evaluation of the delamination data using analytical models and by means of FEA and cohesive zone modelling.