An implantable multielectrode array with on-chip signal processing

This active probe can be used for the long-term recording of extracellular neural biopotentials and as a basis for closed-loop neural prostheses. The probe incorporates on-chip circuitry for amplifying, multiplexing, and buffering neural signals recorded from ten recording electrodes spaced 100-/spl mu/m apart. It requires only three leads and operates from a single 5-V supply. On-chip self-test circuitry for testing electrode impedance levels is provided. The on-chip circuitry is fabricated in a die area of 1.3 mm/SUP 2/ using 6-/spl mu/m LOCOS enhancement-depletion NMOS technology, and dissipates 5 mW of power. The probe is 4.7 mm long and 15 /spl mu/m thick, and has a shank which tapers from 160 /spl mu/m near the base to less than 15 /spl mu/m near the tip.     

Band-tunable and multiplexed integrated circuits for simultaneous recording and stimulation with microelectrode arrays

Two thin-film microelectrode arrays with integrated circuitry have been developed for extracellular neural recording in behaving animals. An eight-site probe for simultaneous neural recording and stimulation has been designed that includes on-chip amplifiers that can be individually bypassed, allowing direct access to the iridium sites for electrical stimulation. The on-probe amplifiers have a gain of 38.9 dB, an upper-cutoff frequency of 9.9 kHz, and an input-referred noise of 9.2 microV rms integrated from 100 Hz to 10 kHz. The low-frequency cutoff of the amplifier is tunable to allow the recording of field potentials and minimize stimulus artifact. The amplifier consumes 68 microW from +/- 1.5 V supplies and occupies 0.177 mm2 in 3 microm features. In vivo recordings have shown that the preamplifiers can record single-unit activity 1 ms after the onset of stimulation on sites as close as 20 microm to the stimulating electrode. A second neural recording array has been developed which multiplexes 32 neural signals onto four output data leads. Providing gain on this array eliminates the need for bulky headmounted circuitry and reduces motion artifacts. The time-division multiplexing circuitry has crosstalk between consecutive channels of less than 6% at a sample rate of 20 kHz per channel. Amplified, time-division-multiplexed multichannel neural recording allows the large-scale recording of neuronal activity in freely behaving small animals with minimum number of interconnect leads.     

Solid-State Electrodes for Multichannel Multiplexed Intracortical Neuronal Recording

Thin-film arrays of extracellular recording electrodes have been developed for use in studies of information processing in neural structures and eventual use in closed-loop control of neural prostheses. These probes consist of a silicon substrate which supports an array of thin-film conductors. The conductors are insulated above and below with deposited dielectrics. The electrode sites are defined by openings in the upper dielectric layer and are inlaid with gold to form low-impedance recording surfaces. The probes are typically 15 pim in thickness with shank widths as narrow as 20 ?m. The probe fabrication process is compatible with the inclusion of signal processing circuitry directly on the probe substrate. A 12 channel on-chip signal processor design with per-channel gain of 100, bandwidth of 100 Hz-6 kHz, multiplexed output, and recording-site impedance check capability is described. The probes have adequate strength to penetrate the gerbil pia-arachnoid layer and have recorded single neuron activity of over 500 ?V peak-to-peak from tip, side, and mid-carrier sites. Signal-to-noise ratios as high as 10:1 have been achieved. An equivalent circuit model for the conducting leads, the recording site, and the electrode-electrolyte interface is described. Development of biocompatible insulation and encapsulation materials for long-term implantation of active probes is underway.     

A 16-channel CMOS neural stimulating array

A probe designed for the highly selective long-term stimulation of neuronal assemblies in the central nervous system is described. The micromachined multishank probe incorporates CMOS circuitry to control the output current on 16 iridium oxide (IrO) electrode sites. Serial site addresses and current amplitude data are loaded into the probe at 4 MHz and converted to analog stimulus currents. The probe circuitry dissipates only 80 μW from ±5-V supplies when not delivering stimulus currents and uses five external leads. It permits the IrO sites to be activated by voltammetry from off-chip, provides per-channel pulse time-outs to prevent accidental overstimulation of the tissue, and signals the external world, using a status bit, in the event of certain trouble conditions. The stimulating site impedances and the stimulus currents can be measured from off chip on demand. The circuitry is implemented in a single-metal, single-poly, CMOS process with 3-μm minimum features using 7100 transistors in an area of 11 mm²     

Single-unit neural recording with active microelectrode arrays

This paper discusses the single-unit recording characteristics of microelectrode arrays containing on-chip signal processing circuitry. Probes buffered using on-chip unity-gain operational amplifiers provide an output resistance of 200 ohm with an input-referred noise of 11-muV root-mean-square (rms) (100 Hz-10 kHz). Simultaneous in vivo recordings from single neurons using buffered and unbuffered (passive) iridium recording sites separated by less than 20 microm have shown that the use of on-chip circuitry does not significantly degrade system noise. Single-unit neural activity has also been studied using probes containing closed-loop preamplifiers having a voltage gain of 40 dB and a bandwidth of 13 kHz, and several input dc-baseline stabilization techniques have been evaluated. Low-noise in vivo recordings with a multiplexed probe have been demonstrated for the first time using an external asymmetrical clock running at 200 kHz. The multiplexed system adds less than 8-muV rms of noise to the recorded signals, suppressing the 5-V clock transitions to less than 2 ppm.     

A high-yield IC-compatible multichannel recording array

This paper reports the development of a multielectrode recording array for use in studies of information processing in the central nervous system and in the closed-loop control of neural prostheses. The probe utilizes a silicon supporting carrier which is defined using a deep boron diffusion and an anisotropic etch stop. This substrate supports an array of polysilicon or tantalum thin-film conductors insulated above and below with silicon nitride and silicon dioxide. Typical probe dimensions include a length of 3 mm, shank width of 50 µm, and a thickness of 15 µm. These structures are capable of simultaneous high-amplitude multichannel recording of neural activity in the cortex. The probe fabrication process requires only four masks and is single-sided using wafers of normal thickness, resulting in yields which exceed 80 percent. The process is also compatible with the inclusion of on-chip MOS circuitry for signal amplification and multiplexing. A complete ten-channel signal processor which requires only three external probe leads is being developed.     

A 64-site multishank CMOS low-profile neural stimulating probe

Describes a low-profile micromachined CMOS probe for multisite stimulation and recording in the central nervous system. The probe uses flexible silicon interconnects to allow the signal processing portion of the probe to fold at right angles to the penetrating probe shanks, limiting the implanted profile above the cortex to less than 1 mm. The probe is designed to stimulate a 4 mm³ volume of neural tissue with a spatial resolution of 400 μm using 1000 μm² electrode sites. Eight of the 64 sites on the probe can be driven simultaneously over a current range from -127 μA to +127 μA with 1 μA resolution. An on-chip preamplifier allows the neural activity on any selected site to be recorded with an overall gain of 30 and bandwidth from 50 Hz to 9 kHz. The probe operates with a stimulus current linearity of 0.98 up to clock frequencies as high as 5 MHz and dissipates less than 15 μA in standby from ±5 V supplies     

Low-voltage electronics for the stimulation of biological neuralnetworks using fully complementary BiCMOS circuits

This paper describes low-voltage neural stimulating circuitry developed using fully complementary BiCMOS (FC-BiCMOS) process technology for providing charge-balanced bipolar stimulating currents to tissue in the central nervous system. The electronics features an FC-BiCMOS buffer, a 7-b biphasic current-output digital-to-analog converter, a 14-b frequency divider, a nonoverlapping two-phase clock generator, and an auto timeout safety scheme while driving any two of eight selected sites from 0 to ±126 μA with ±2 μA resolution. The circuit area is 1.6 mm² in 3-μm features. Micropower circuit techniques allow the probe to dissipate <10 μW in standby and operate at 10 MHz from ±2.5 V supplies     

A three-dimensional microelectrode array for chronic neuralrecording

Describes a 3-D microelectrode array for the chronic recording of single-unit activity in the central nervous system. The array is formed by a microassembly of planar silicon multishank microprobes, which are precisely positioned in a micromachined platform that resides on the surface of the cortex. Interconnects between the probes and the platform are formed using electroplated nickel lead transfers, implemented using automated computer control. All dimensions are controlled to ±1 μm and shank/probe separations as small as 100 μm are possible. Four-probe 16-shank prototype arrays have been tested chronically in guinea pig cortex. After three months in vivo, no significant tissue reaction has been observed surrounding these structures when they remain free to move with the brain, with normal appearing tissue between shanks spaced at 150 μm to 200 μm intervals. The array structure is compatible with the use of signal processing circuitry both on the probes and on the platform. A platform-based signal processing system has been designed to interface with several active probes, providing direct analog access to the recording sites, performing on-chip analog-to-digital conversion of neural activity, and providing simple binary-output recognition of single-unit spike events using a user-input threshold voltage     

Wavelength conversion at 10 Gb/s using a semiconductor opticalamplifier

Data at 10 Gb/s has been translated from an input signal wavelength to another wavelength, either longer or shorter, using gain compression in a 1.5-μm semiconductor optical amplifier for wavelength conversion. To achieve operation at such high bit rates, the probe (shifted) input must be intense enough to compress the gain of the amplifier significantly. This reduces the gain recovery time of the amplifier because of probe stimulated emission. A consequence of the intense probe is an extinction ratio deduction. Using moderate input powers, wavelength conversion is achieved over a 17-nm (2-THz) range, with 0.7-3-dB power penalties     

Pseudomorphic InP HEMTs with dry-etched source vias having 190 mWoutput power and 40% PAE at V-band

We report state-of-the-art V-band power performance of 0.15-μm gate length InGaAs/InAlAs/InP HEMT's which have 15 μm×23 μm dry-etched through-substrate source vias (substrate thickness 50 μm). The 500-μm wide InP HEMT's were measured in fixture at 60 GHz and demonstrated an output power of 190 mW with 40% power-added efficiency (PAE) and 6.8 dB power gain at an input power of 16 dBm. These results represent the best combination of power and PAE reported to date at this frequency for any solid state device. The results are achieved through optimization of the InP-based heterostructure which incorporates a graded pseudomorphic InGaAs channel and a graded pseudomorphic InAlAs Schottky barrier layer, and the use of 15 μm×23 μm dry-etched through-substrate source vias     

A 2-GHz wide-band direct conversion receiver for WCDMA applications

A 2-GHz direct conversion receiver for third-generation mobile communications using wide-band code division multiple access achieves -114-dBm sensitivity for 128-kb/s data at 4.096-Mcps spreading rate. The receiver is distributed on four dies. The active RC channel selection filter can be programmed to three different bandwidths from 5 to 20-MHz radio-frequency (RF) spacing; and the gain control is merged with filtering. RF and baseband chips use a 25-GHz, 0.3-μm BiCMOS technology while the two analog-to-digital converters are implemented with a 0.5-μm CMOS. The double-sideband noise figure is 5.1 dB at the 94-dB maximum voltage gain, and the IIP3 and ITP2 are -9.5 and +38 dBm, respectively, The receiver draws 128 mA from a 2.7-V supply     

CCD arrays for readout of electrophotographic latent images

Arrays of charge sensing elements have been fabricated for nondestructive electronic readout of latent images on electrophotographic materials. The arrays are implemented in the form of a monolithic integrated circuit in which each sensing element is a 5-μm ×5-μm MOS capacitor; 2048 such elements are arranged in a linear format with effective 5-μm element-to-element pitch. On-chip circuitry allows for multiple sampling at each sensing site for enhancing signal-to-noise ratio. The resulting signals from the sense elements are multiplexed onto charge-coupled-device (CCD) shift registers for high-speed serial readout. To allow for the small sensor-to-film gap (on the order of 10 μm) required for capacitive sensing, the chip's bond pads are recessed in deep grooves below the active array surface. The array is packaged within a hydrostatic air bearing which maintains a constant and uniform gap. The response of the array to targets of high spatial frequency recorded on various electrophotographic materials is in excellent agreement with analytical predictions     

A low-distortion K-band GaAs power FET

A K-band low-distortion GaAs power MESFET was developed by incorporating a pulse-type channel doping profile using molecular-beam-epitaxial technology and a novel 0.3-μm T-shaped gate. The low-distortion FETs offer about 10 to 15 dBc improvement in second-harmonic distortion compared to devices fabricated on a uniformity doped active layer. Significantly larger power load-pull contours are obtained with the low-distortion devices, indicating the improved linearity of these devices. In an 8-20-GHz single-stage broad-band amplifier, up to 10 dBc improvement in harmonic performance was achieved using the low-distortion device. This low-distortion device exhibits very linear transconductance as a function of the gate bias. A typical 750-μm-gate-width device is capable of 26 dBm of output power with 6 dB of gain, and power-added efficiency in excess of 35% when measured at 18 GHz. At 25 GHz, the device is capable of 24 dBm of output power with 5 dB associated gain     

A 0.8-μm CMOS two-dimensional programmable mixed-signalfocal-plane array processor with on-chip binary imaging and instructionsstorage

This paper presents a CMOS chip for the parallel acquisition and concurrent analog processing of two-dimensional (2-D) binary images. Its processing function is determined by a reduced set of 19 analog coefficients whose values are programmable with 7-b accuracy. The internal programming signals are analog, but the external control interface is fully digital. On-chip nonlinear digital-to-analog converters (DAC's) map digitally coded weight values into analog control signals, using feedback to predistort their transfer characteristics in accordance to the response of the analog programming circuitry. This strategy cancels out the nonlinear dependence of the analog circuitry with the programming signal and reduces the influence of interchip technological parameters random fluctuations. The chip includes a small digital RAM memory to store eight sets of processing parameters in the periphery of the cell array and four 2-D binary images spatially distributed over the processing array. It also includes the necessary control circuitry to realize the stored instructions in any order and also to realize programmable logic operations among images. The chip architecture is based on the cellular neural/nonlinear network universal machine (CNN-UM). It has been fabricated in a 0.8-μm single-poly double-metal technology and features 2-μs operation speed (time required to process an image) and around 7-b accuracy in the analog processing operations     

A CMOS delta-sigma true RMS converter

Conventionally, monolithic electronics true rms converters are constructed by bipolar circuitry. This paper describes a new architecture based on delta-sigma (ΔΣ) modulation to realize a low-cost rms converter in CMOS technologies, especially intended for handheld digital multimeters. The signal-to-quantization noise ratio as well as transfer characteristics of this architecture have been deduced to obtain initial design parameters. The use of an indirect charge transfer technique makes the converter gain depend only on an on-chip capacitor ratio, reducing gain drift and offering good gain accuracy. Measured results show that this converter achieves a signal-to-noise ratio of 88 dB and a relative error of ±0.2% for arbitrary inputs with a signal crest factor up to three. The signal bandwidth exceeds 50 kHz, and the full-scale input range is greater than 0.4 V_rms. Without trimming and calibration, this converter has an absolute gain error less than ±0.4%. This chip is fabricated in a 0.8-μm double-poly, double-metal CMOS process and occupies active area of 1 mm ²     

A 16×16 crosspoint switch for ternary encoded signals

A crosspoint-switching chip that can switch bipolar, alternate mark inversion encoded (AMI) signals directly, is described. AMI encoding is a form of ternary, return-to-zero (RZ) coding where a binary zero is represented by an absence of a pulse and ones are represented with an alternating sequence of positive and negative pulses. Bipolar signals are used widely in interoffice telecommunications such as the T1, T1C, T2, and T3 digital transmission systems. The switching chip has 16 input and 16 output channels. Control of the chip allows any input to be connected to any output or outputs, providing a nonblocking connection. The architecture allows for expansion of the crosspoint array by paralleling several chips. The chip, fabricated using a standard 3-μm CMOS technology, is capable of handling data rates up to 15 Mb/s per channel, has about 17000 transistors, and has an area of about 32.5 mm²     

A CMOS four-channel×1K time memory LSI with 1-ns/b resolution

A four-channel 1024-b time-to-digital converter chip, which records input signals to memory cells at 1-ns intervals, has been developed. To achieve 1-ns precision, the chip incorporates a feedback stabilized delay element. The chip was fabricated on a 5.0-mm×5.6-mm die using 0.8-μm CMOS technology. It dissipates only 7 mW/channel under typical operating conditions     

A 550-MSample/s 8-Tap FIR digital filter for magnetic recordingread channels

An area-efficient low-power and low-latency 550-MSample/s FIR filter for magnetic recording read channel applications is presented. A parallel direct type II architecture operates on real-time deinterleaved (even and odd) input data samples and employs a fast low-area multiplier based on selection of radix-8 premultiplied coefficients in conjunction with one-hot encoded bus leading to a very compact layout and reduced power dissipation. The chip has been fabricated using a 0.18-μm L-effective CMOS technology and is currently being used in commercial applications     

Low power CMOS preamplifier for neural recording applications

A fully-differential bandpass CMOS (complementary metal oxide semiconductor) preamplifier for extracellular neural recording is presented. The capacitive-coupled and capacitive-feedback topology is adopted. The preamplifier has a midband gain of 20.4 dB and a DC gain of 0. The -3 dB upper cut-off frequency of the preamplifier is 6.7 kHz. The lower cut-off frequency can be adjusted for amplifying the field or action potentials located in different bands. It has an input-referred noise of 8.2 μVrms integrated from 0.15 Hz to 6.7 kHz for recording the local field potentials and the mixed neural spikes with a power dissipation of 23.1 μW from a 3.3 V supply. A bandgap reference circuitry is also designed for providing the biasing voltage and current. The 0.22 mm2 prototype chip, including the preamplifier and its biasing circuitry, is fabricated in the 0.35-μm N-well CMOS 2P4M process.