自对准硅化物CMOS／SOI技术研究

在ＣＭＯＳ／ＳＩＭＯＸＳＯＩ电路制作中引入了自对准钴（Ｃｏ）硅化物（ＳＡＬＩＣＩＤＥ）技术，研究了ＳＡＬＩＣＩＤＥ工艺对ＳＯＩＭＯＳＦＥＴ单管特性和ＣＭＯＳ／ＳＯＩ电路速度性能的影响．实验表明，采用ＳＡＬＩＣＩＤＥ技术能有效地减小ＭＯＳＦＥＴ栅、源、漏电极的寄生接触电阻和方块电阻，改善单管的输出特性，降低ＣＭＯＳ／ＳＯＩ环振电路门延迟时间，提高ＣＭＯＳ／ＳＯＩ电路的速度特性．     

自对准硅化物SOI／CMOS技术研究

在ＳＯＩ／ＣＭＯＳ电路制作中引入了自对准钴硅化物（ＳＡＬＩＣＩＤＥ）技术，研究了ＳＡＬＩＣＩＤＥ工艺对ＳＯＩ／ＭＯＳＦＥＴ单管特性和ＳＯＩ／ＣＭＯＳ电路速度性能的影响。实验表明，ＳＡＬＩＣＩＤＥ技术能有效地减小ＭＯＳＦＥＴ栅、源、漏电极的寄生接触电阻和薄层电阻，改善单管的输出特性，降低ＳＯＩ／ＣＭＯＳ环振电路门延迟时间，提高ＳＯＩ／ＣＭＯＳ电路的速度特性。     

大容量FLASHMEMORY芯片28F032SA及其在心电记录中的应用

介绍ＩＮＴＥＬ公司３２－Ｍｂｉｔ ＦＬＡＳＨ ＭＥＭＯＲＹ芯片２８Ｆ０３２ＳＡ的性能及其用法；给出了２８Ｆ０３２ＳＡ与８０Ｃ１９８单片机的一种接口电路及ＰＬ／Ｍ－９６语言编程示例。     

CMOS电路芯片ESD保护电路设计技术的发展

本文简要地回顾了ＣＭＯＳ电路芯片上ＥＳＤ保护电路设计技术发展概况，给出了在中小规模、大规模及超大规模各阶段的ＣＭＯＳ电路芯片上ＥＳＤ保护电路的主流技术，双寄生的ＳＣＲ结构ＶＬＳＩ ＣＭＯＳ芯片上ＥＳＤ保护电路的最新设计技术，就其ＥＳＤ保护原理、设计技术及取得的成果做了较详细分析和探讨。对于研制高密度、高速度的ＶＬＳＩ ＣＭＯＳ电路。开展高ＥＳＤ失效阈值电压，小几何尺寸及低ＲＣ延迟时间常数保护电路的     

具有优良性能的MCBiCMOS IC结构

本文分析了几种常规ＢｉＣＭＯＳ门电路的特性，对ＭＣＢｉＣＭＯＳ集成电路结构的二输入与非门和１１级环形振荡器进行了实验研究，并与常规ＢｉＣＭＯＳ进行了比较。实验结果说明：ＭＣＢｉＣＭＯＳ具有电路结构简单；芯片面积小；工作速度高，负载能力强和低压工作性能好等优点。     

调频连续波雷达灵敏度频率控制技术

提出了调频连续波（ＦＭＣＷ）雷达灵敏度频率控制（ＳＥＣ）技术这一新概念，论述了ＳＦＣ电路的基本原理，并结合毫米波ＬＦＭＣＷ场面监视雷达的要求介绍了ＳＦＣ电路的设计思想，给出了试验结果。     

有长途锁定功能的发号集成电路W9145

有长途锁定功能的发号集成电路Ｗ９１４５夏栋Ｗ９１４５系列发号电路是华邦生产的硅门电路ＣＭＯＳ集成电路（ＩＣ）。它具有Ｐ／Ｔ兼容、首拨０或９后发号锁定，及门个号码存储、免提发号等功能。Ｗ９１４５可取代ＷＥｇｌ４５，ＨＭｇｌ１４和ＵＭ９１２６５。该电路的...     

MPEG-2视频反量化电路的VHDL描述与验证

设计了用于ＭＰＥＧ－２ＭＰ＠ＭＬ视频解码ＶＬＳＩ的ＩＱ电路结构,基于对ＩＱ的运算字长和精度关系的分析,有针对性地提出相应的硬件电路结构设计,减少了电路规模以适应ＭＰＥＧ－２ＭＰ＠ＭＬ视频较大的数据量,电路采用了ＶＨＤＬ进行描述并通过模拟和验证。结果表明该电路可以完成ＭＰＥＧ－２解码的功能。     

采用CoSi2 SALICIDE结构CMOS/SOI器件辐照特性的实验研究

讨论了ＣｏＳｉ２ＳＡＬＩＣＩＤＥ结构对ＣＭＯＳ／ＳＯＩ器件和电路抗γ射线总剂量辐照特性的影响。通过与多晶硅栅器件对比进行的大量辐照实验表明,ＣｏＳｉ２ＳＡＬＩＣＩＤＥ结构不仅可以降低ＣＭＯＳ／ＳＯＩ电路的源漏寄生串联电阻和局域互连电阻,而且对ＳＯＩ器件的抗辐照特性也有明显的改进作用。     

SVM电路及其在大屏幕彩电上的应用

ＳＶＭ电路及其在大屏幕彩电上的应用·电路应用·３５０００４福建日立电视机有限公司吴浦飞ＳＶＭ（ＳＣＡＮＶＥＬＯＣＩＴＹＭＯＤＵＬＡ－ＴＩＯＮ）电路，即扫描速度调制电路，是近几年来大屏幕彩色电视机普遍采用的一种图象轮廓水平清晰度提升电路。它的功能是取出...     

3.21 ps ECL gate using InP/InGaAs DHBT technology

A new circuit configuration for an emitter-coupled logic (ECL) gate that can reduce propagation delay time has been demonstrated. Nineteen-stage ring oscillators were fabricated using InP/InGaAs double-heterojunction bipolar transistors (DHBTs) with cutoff frequency f/sub T/ and maximum oscillation frequency f/sub max/ of about 232 and 360 GHz, respectively, to evaluate the speed performance of the proposed ECL gate. The minimum propagation delay is 3.21 ps/gate. The proposed ECL gate is about 8% faster than the conventional ECL gate.     

An ECL gate with improved speed and low power in a BiCMOS process

An emitter-coupled logic (ECL) gate exhibiting an improved speed-power product over the circuits presented in the past is described. The improvement is due to a combination of a push-pull output stage driven by a controlled current source, thus reducing the static and increasing the dynamic current. This circuit has better driving capabilities and improved speed, yet it uses an order of magnitude less power than a regular ECL gate. Due to its reduced power consumption, this gate allows for a higher level of integration of ECL logic. The realization of this circuit using a regular bipolar process is also possible     

Capacitor-free level-sensitive active pull-down ECL circuit withself-adjusting driving capability

This paper introduces a new self-adjusting active pull-down scheme for ECL circuit. The circuit offers self-terminating dynamic pull-down action by sensing the output level rather than using traditional load-dependent capacitive coupling. No capacitor or large resistor is required, and therefore it adds no process complexity and no area penalty. Implemented in an ECL gate array in a 1.2 μm double-poly self aligned bipolar technology, the circuit offers 300-ps delay at a power consumption of 1 mW/gate under FO=1 and C_L=0.55 pF loading condition. This is a 4.4 times speed improvement over the conventional ECL circuit. Furthermore, the circuit consumes only 0.25 mW for a gate speed of 700 ps/gate, which is a 1/7.8 power reduction compared with the conventional ECL circuit. The circuit requires a regulated reference voltage, which is also studied     

An ultra-high-speed ECL-BiCMOS technology with silicon filletself-aligned contacts

We have developed a half-micron super self-aligned BiCMOS technology for high speed application. A new SIlicon Fillet self-aligned conTact (SIFT) process is integrated in this BiCMOS technology enabling high speed performances for both CMOS and ECL bipolar circuits. In this paper, we describe the process design, device characteristics and circuit performance of this BiCMOS technology. The minimum CMOS gate delay is 38 ps on 0.5 μm gate and 50 ps on 0.6 μm gate ring oscillators at 5 V. Bipolar ECL gate delay is 24 ps on 0.6 μm emitter ring oscillators with collector current density of 40 kA/cm². A single phase decision circuit operating error free over 8 Gb/s and a static frequency divider operating at 13.5 GHz is demonstrated in our BiCMOS technology     

一种ECL可编程分频器的研制

本文在分析TTL可编程分频器逻辑功能的基础上,设计了模数在1～16之间任意可变的ECL可编程分频器,利用SPICE电路模拟程序对电路进行了直流和瞬态分析。同时,针对超高速ECL电路的特点,完成了电路版图及工艺设计,并进行了工艺试制。做出了工作频率可达50MHz以上的ECL可编程分频器,比原TTL可编程分频器的工作频率提高了5倍之多。     

Diode-HBT-logic circuits monolithically integrable with ECl/CMLcircuits

A novel logic approach, diode-HBT logic (DHL), that is implemented with GaAlAs/GaAs HBTs and Schottky diodes to provide high-density and low-power digital circuit operation is described. This logic family was realized with the same technology used to produce emitter-coupled-logic/current-mode-logic (ECL/CML) circuits. The logic operation was demonstrated with a 19-stage ring oscillator and a frequency divider. A gate delay of 160 ps was measured with 1.1 mW of power per gate. The divider worked properly up to 6 GHz. Layouts of a DHL flip-flop and divider showed that circuit area and transistor count can be reduced by about a factor of 3, relative to ECL/CML circuits. The new logic approach allows monolithic integration of high-speed ECL/CML circuits with high-density DHL circuits with high-density DHL circuits     

一种新型TTL非门电路的设计

叙述了一种新型ＴＴＬ非门电路的设计思路，电路工作原理和调试实验，人析了其集成的可行性，说明了新电路如何克服现有的ＴＴＬ非门电路自身的弱点，使其工作更加稳定可靠，这种新型ＴＴＬ门电路的应用提高了数字逻辑电路工作的稳定性。     

High-speed low-power Darlington ECL circuit

Presents an ECL circuit with a Darlington configured dynamic current source and active-pull-down emitter-follower stage for low-power high-speed gate array application. The dynamic current source provides a large dynamic current during the switching transient to improve the power delay of the logic stage (current switch). A novel self-biasing scheme for the dynamic current source and the active-pull-down transistor with no additional devices and power in the biasing circuit is described. Based on a 0.8-μm double-poly self-aligned bipolar technology at a power consumption of 1 mW/gate, the circuit offers 28% improvement in the loaded (FI/FO=3, C_L=0.3 pF) delay and 42% improvement in the load driving capability compared with the conventional ECL circuit. The design and scaling considerations of the circuit are discussed     

Modified feedback ECL gate for Gb/s applications

This paper introduces a modification of the feedback emitter-coupled logic (FECL) gate that makes it suitable for Gb/s applications. The circuit can be used as a single-ended-to-differential signal converter without the need for an external reference voltage and finds application in digital optical links in which data is typically transmitted single ended. The gate is compared with FECL and ECL gates, and its application to realize logic functions is discussed. A 6-Gb/s series gated decision circuit and a 2-Gbaud/s four-channel optical receiver array employing modified FECL gates are also described     

3GHz硅双极型微波静态分频器的设计

本文报道了一种超高速ＥＣＬ静态二分频器；介绍了该分频器的核心器件─—ＮＰＮ晶体管的结构和实现该结构的有关先进工艺，包括深槽隔离、多晶硅发射极、钻硅化物和浅结薄基区等；使用这种多晶硅发射极晶体管，３ｐｍ特征尺寸设计的１９级环形振荡器的平均门延迟小于５０ｐｓ．讨论了提高分频器工作频率的一些有效方法并给出了３．２ＧＨｚ硅静态分频器的电路设计和版图设计．