A superconducting tracking A/D converter

The design and fabrication of a superconducting A/D converter using Josephson technology are described. The 4-b A/D converter circuit was fabricated using a ten-level all-Nb technology. It uses a self-aligned lift-off process to define the Nb-Al₂O₃ -Nb Josephson junctions. Results from experiments performed on the prototype system at a few kilohertz sampling rate are presented     

A Clock Generator for High-Speed High-Resolution Pipelined A/D Converter Zhao Lei(赵磊) , Yang Yintang(杨银堂), Zhu Zhangming(朱樟明), Liu Lianxi(刘帘羲)

A clock generator circuit for a high-speed high-resolution pipelined A/D converter is presented.The circuit is realized by a delay locked loop(DLL),and a new differential structure is used to improve the precision of the charge pump.Meanwhile,a dynamic logic phase detector and a three transistor NAND logic circuit are proposed to reduce the output jitter by improving the steepness of the clock transition.The proposed circuit,designed by SM1C 0.18μm 3.3 V CMOS technology,is used as a clock generator for a 14 bit 100 MS/s pipelined ADC.The simulation results have shown that the duty cycle ranged from 10%to 90%and can be adjusted.The average duty cycle error is less than 1%.The lock-time is only 13 clock cycles.The active area is 0.05 mm2 and power consumption is less than 15 mW.     

A second-order high-resolution incremental A/D converter withoffset and charge injection compensation

Measurement and instrumentation applications require absolute accuracy, e.g. offset and gain errors cannot be tolerated. These applications are characterized by DC performance such as differential and integral nonlinearities, offset and gain errors, and they often require high resolution. The second-order incremental A/D converter, which makes use of sigma-delta modulation associated with a simple digital filter, is capable of achieving such requirements. Experimental results of circuits fabricated in a SACMOS 3-μm technology indicate that 15-bit absolute accuracy is easily achievable, even with a low reference voltage     

All-digital A/D converter TAD with high-resolution and low-power for sensor/RF digitization

For achieving both high resolution and low power of a sensor/RF interface, time-domain processing using full-digital circuits, which deals with only two voltage levels (i.e., V _in-supply-voltage and ground-level), is presented. In a much broader sense, digital circuits can be used for time-domain processing instead of conventional analog signal processing. In this study, an all-digital 6- to 16-bit adaptive sensor-interface ADC is experimentally evaluated for high-resolution and low-power operation along with high scalability. The circuit architecture is completely digital, using a ring-delay-line (RDL) driven by an input voltage V _in as its power supply. Resolutions can be controlled by setting its conversion time T _cv, resulting in 16 bit (1 kS/s, 34 μW) and 6 bit (1 MS/s, 48 μW) with a prototype IC in a low-cost 0.65-μm (650-nm) digital CMOS, achieving the sensor digitizer (sensor-digitization product) of a pressure sensor ASIC. The all-digital structure has been scaled into a 0.18-μm technology, and the test IC presented a higher performance with 28 μV/LSB (160-kS/s). Finally, as an RF digitization application, the circuit is demonstrated to realize the time-domain processing of an RF signal, working as both mixer and ADC, achieving minimum/maximum detectable sensitivity of 0.7-μVrms/100-mVrms, respectively, for a 40-kHz sine wave at the LNA input terminal of a 0.18-μm digital CMOS one-chip radio-controlled clock receiver IC.     

一种可重构流水线ADC的设计

对多标准无线通信系统中的A／D转换器进行了研究,根据无线通信系统的特点,构建了一个新型可重构流水线A／D转换器结构,该A／D转换器的可重构功能是通过在低分辨率下关断子级流水线来实现的。转换器的系统指标为6～14b,从而可以在保证不影响ADC性能的前提下,引入新颖的可重构控制以进一步降低功耗。最后对改进的可重构流水线ADC进行了性能仿真。     

10位逐次逼近型A/D转换器的芯片设计

介绍了一种10位、3M sample/s逐次逼近型A/D转换器的设计,描述了具有可变时钟电路结构的有效工作方式.该模数转换器在0.6 μ m双多晶硅、双金属层CMOS工艺上实现,芯片总面积为3.2mm2.转换器采用单5V电源供电,功耗仅为3 5mW.     

Design techniques for a low-power low-cost CMOS A/D converter

A 10 bit 200 kHz algorithmic analog-to-digital converter (ADC) was designed to demonstrate design techniques for low-power low-cost CMOS integrated systems. A switched-bias power-reduction technique reduces the total system power by 10%. A layout technique employing extra thin poly-layer lines instead of conventional dummy devices reduces plasma-induced comparator offsets. Based on a standard digital CMOS process with a single poly layer, the ADC adopts metal-to-metal capacitors for internal charge storage. The experimental ADC was fabricated in a 0.6 μm single-poly double-metal n-well CMOS technology, and showed a power consumption of 7 mW and a signal-to-noise-and-distortion ratio (SNDR) of 53 dB at the Nyquist sampling rate with a 3.3 V single supply voltage. The measured differential and integral nonlinearities of the prototype are less than ±0.8 and ±1.8 LSB, respectively     

A/D和D/A转换器IC

代码转换器提高DSP效率 TLV320AIC10 16位代码转换器提供连续数据传输,可支持DSP自动缓冲单元,减少因缓冲(最高达64kB)不足而引起的中断。该器件特性有每秒22k的采样速率,一个串行接口,增益范围为-36～24dB的可编程增益放大器,一个2:1模拟多路复用器,以及节能备用模式。其它性能包括:工作电压3～5.5V,在采样速率为每秒8k时功耗为39mW。     

基于LTC2753的数模转换器电路设计

介绍了Linear公司的双路电流输出的数模(D/A)转换器LTC2753的主要特性、电路结构及应用电路.并在此基础上设计了偏移量和增益调整电路.     

A high-frequency and high-resolution fourth-order /spl Sigma//spl Delta/ A/D converter in BiCMOS technology

A high-performance cascaded sigma-delta modulator is presented. It has a new three-stage fourth-order topology and provides functionally a maximum signal to quantization noise ratio of 16 bits and 16.5-bit dynamic range with an oversampling ratio of only 32. This modulator is implemented with fully differential switch-capacitor circuits and is manufactured in a 2-/spl mu/m BiCMOS process. The converter, operated from +/-2.5 V power supply, +/-1.25 V reference voltage and oversampling clock of 48 MHz, achieves 97 dB resolution at a Nyquist conversion rate of 1.5 MHz after comb-filtering decimation. The power consumption of the converter is 180 mW.<>     

高速A/D转换器的选择--在选择A/D变换器时,其应用场合是一条重要的依据

模数转换器是连接模拟和数字世界的一个重要接口.A/D转换器将现实世界的模拟信号变换成数字位流以进行处理、传输及其他操作.     

基于控阈技术的并行式A/D转换器设计

该文将数字电路设计中空间-时间等效思想及阈值控制技术两者引入A/D转换器的设计，所设计出的A/D转换器在保证较高速度的同时具有相对简单的电路结构。     

A monolithic 8-bit A/D converter with 120 MHz conversion rate

A monolithic 8-bit flash A/D converter is described which digitizes a 40-MHz signal at a conversion rate of over 100 MHz. To obtain full resolution and high accuracy at ultrahigh speed operation, a three-stage comparator with small talk back and other new logic circuits were designed. The process used is a self-aligned bipolar technology. Signal-to-noise ratio of 45 dB was measured at the 30-MHz input frequency.     

基于单片机和555定时器的A/D转换器设计

为克服在A/D转换中输入电压范围窄的问题,介绍了一种采用单片机AT89C51和NE555定时器构成的A/D转换器.详细分析了其工作原理和A/D转换的特性.该A/D转换器对低频输入信号在较高电压范围内具有一定的实用价值.     

Current-mode A/D converter

The authors report the design of a new current-mode A/D converter, based on a modified successive-approximations model, in 1.2 μm CMOS technology. The proposed circuit is characterised by good accuracy and fast dynamic performance, low power consumption and small occupation area. SPICE simulations allow the design approach to be validated and the electrical performance of the ADC to be predicted     

A low-power inverted ladder D/a converter

Interpolating, dual resistor ladder digital-to-analog converters (DACs) typically use the fine, least significant bit (LSB) ladder floating upon the static most significant bit (MSB) ladder. The usage of the LSB ladder incurs a penalty in dynamic performance due to the added output resistance and switch matrix parasitic capacitance. Current biasing of the LSB ladder addresses this issue by employing active circuitry. We propose an inverted ladder DAC, where an MSB ladder slides upon two static LSB ladders. While using no active components this scheme achieves lower output resistance and parasitic capacitance for a given power budget. We present a 0.35-/spl mu/m, 3.3-V implementation consuming 22-/spl mu/A current with output resistance of 40 k/spl Omega/ and effective parasitic capacitance of 650 fF.     

A high-resolution time-to-digital converter using a three-level resolution

In this article, a three-level resolution Vernier delay line time-to-digital converter (TDC) was proposed. The proposed TDC core was based on the pseudo-differential digital architecture that made it insensitive to nMOS and pMOS transistor mismatches. It also employed a Vernier delay line (VDL) in conjunction with an asynchronous read-out circuitry. The time interval resolution was equal to the difference of delay between buffers of upper and lower chains. Then, via the extra chain included in the lower delay line, resolution was controlled and power consumption was reduced. This method led to high resolution and low power consumption. The measurement results of TDC showed a resolution of 4.5 ps, 12-bit output dynamic range, and integral nonlinearity of 1.5 least significant bits. This TDC achieved the consumption of 68.43 µW from 1.1-V supply.     

了解D/A转换器的架构--架构与制造工世决定D/A 转换器的性能

数模转换器(D/A)在许多应用中起着重要的作用.了解常用D/A架构及相关的权衡折衷方法,将有助于您针对某项具体应用选择最为合适的D/A.     

A Nyquist-rate delta-sigma A/D converter

This paper describes an analog-to-digital converter which combines multiple delta-sigma modulators in parallel so that time oversampling may be reduced or even eliminated. By doubling the number of Lth-order delta-sigma modulators, the resolution of this architecture is increased by approximately L bits. Thus, the resolution obtained by combining M delta-sigma modulators in parallel with no oversampling is similar to operating the same modulator with an oversampling rate of M. A parallel delta-sigma A/D converter implementation composed of two, four, and eight second-order delta-sigma modulators is described that does not require oversampling. Using this prototype, the design issues of the parallel delta-sigma A/D converter are explored and the theoretical performance with no oversampling and with low oversampling is verified. This architecture shows promise for obtaining high speed and resolution conversion since it retains much of the insensitivity to nonideal circuit behavior characteristic of the individual delta-sigma modulators