4.9-GHz low-phase-noise transformer-based superharmonic-coupled GaInP/GaAs HBT QVCO

The low-phase-noise GaInP/GaAs heterojunction bipolar transistor (HBT) quadrature voltage controlled oscillator (QVCO) using transformer-based superharmonic coupling topology is demonstrated for the first time. The fully integrated QVCO at 4.87GHz has phase noise of -131dBc/Hz at 1-MHz offset frequency, output power of -4dBm and the figure of merit (FOM) -198dBc/Hz. The state-of-the-art phase noise FOM is attributed to the superior GaInP/GaAs HBT low-frequency device noise and the high quality transformer formed on the GaAs semi-insulating substrate.     

A Low Voltage Divide-by-4 Injection Locked Frequency Divider With Quadrature Outputs

This letter presents a low voltage quadrature divide-by-4 (divide4) injection-locked frequency divider (QILFD). The QILFD consists of a 1.8-GHz quadrature voltage controlled oscillator (QVCO) and two NMOS switches, which are inserted into the quadrature outputs of the QVCO for signal injection. The low-voltage CMOS divide4 QILFD has been implemented with the TSMC 0.18-mum 1P6 M CMOS technology and the core power consumption is 3.12mW at the supply voltage of 1.2V. The free-running frequency of the QILFD is tunable from 1.73 to 1.99GHz, the measured phase noise of QILFD is -118dBc/Hz at 1-MHz offset from the free running frequency of 1.82GHz. At the input power of 0dBm, the total locking range is from 6.86 to 8.02GHz as the tuning voltage is varied from 0 to 1.2V. The phase noise of the locked output spectrum is lower than that of free running ring oscillator by 11dBc/Hz. The phase deviation of quadrature output is about 0.8deg     

47.8 GHz InP HBT quadrature VCO with 22% tuning range

A 38-47.8 GHz quadrature voltage controlled oscillator (QVCO) in InP HBT technology is presented. The measured output power is -15 dBm. The simulated phase noise ranges from -84 to -86 dBc/Hz at 1 MHz offset. It is believed that this is the first millimetre-wave QVCO implemented in InP HBT technology as well as the highest measured oscillation frequency for any QVCO     

A 28-GHz monolithic integrated quadrature oscillator in SiGe bipolar technology

This paper presents a 28-GHz monolithic quadrature voltage-controlled oscillator (QVCO) realized in a preproduction 0.4-/spl mu/m SiGe bipolar technology with 85-GHz transit frequency. QVCOs efficiently drive quadrature modulators and demodulators in receivers or transmitters. At 28.9 GHz, the circuit provides -14.7 dBm of output power and phase noise of -84.2 dBc/Hz at a 1-MHz offset. The two output signals are in quadrature with phase error of about 5/spl deg/. Tuning of the QVCO may be done in the frequency range from 24.8 to 28.9 GHz with nearly constant output power. The circuit consumes 25.8 mA from the 5 V voltage supply.     

A 0.35 μm CMOS divide-by-2 quadrature injection-locked frequency divider based on voltage-current feedback topology

This paper presents a new divide-by-2 quadrature injection-locked frequency divider (QILFD). The QILFD consists of a new transformer-coupled quadrature voltage controlled oscillator (QVCO) with the voltage-current feedback technique and two NMOS switches, which are in parallel with the QVCO resonators for signal injection. The proposed CMOS QILFD has been implemented with the TSMC 0.35 μm CMOS technology and the core power consumption is 16.52 mW at the supply voltage of 2.2 V. The free-running frequency of the QILFD is tunable from 2.85 GHz to 3.07 GHz. At the input power of 0 dBm, the divide-by-2 operation range is from 5.48 GHz to 6.48 GHz. The phase deviation of free running quadrature output is about 0.53°.     

CMOS Colpitts Quadrature VCO Using the Body Injection-Locked Coupling Technique

This paper presents a new low phase noise quadrature voltage-controlled oscillator (QVCO), which consists of two differential complementary Colpitts voltage-controlled oscillators (VCOs) with a tail inductor. The output of the tail inductor in one differential VCO is injected to the bodies of the nMOSFETs in the other differential VCO and vice versa. The proposed CMOS QVCO has been implemented with the TSMC 0.18 mum CMOS technology and the die area is 0.725 times 0.839 mm². At the supply voltage of 1.1 V, the total power consumption is 9.9 mW. The free-running frequency of the QVCO is tunable from 5.26 GHz to 5.477 GHz as the tuning voltage is varied from 0.0 V to 1.1 V. The measured phase noise at 1 MHz frequency offset is -124.36 dBc/Hz at the oscillation frequency of 5.44 GHz and the figure of merit (FOM) of the proposed QVCO is -189.1 dBc/Hz.     

A 5-GHZ Low-Power Series-Coupled BiCMOS Quadrature VCO With Wide Tuning Range

This letter presents a novel quadrature voltage controlled oscillator (QVCO) implemented in a 47-GHz SiGe BiCMOS technology. The QVCO is a serially coupled LC VCO that utilizes SiGe heterojunction bipolar transistors for oscillation and metal oxide semiconductor field effect transistors for coupling. The SiGe BiCMOS QVCO prototype achieves about 14.6% tuning range from 4.3 to 5GHz. The phase noise of the QVCO is measured as -114.3 dBc/Hz at 2-MHz offset. The 5-GHz QVCO core consumes 6-mA current from a 3.3-V power supply and occupies 0.88mm² area     

一种2.4GHz正交输出频率综合器

介绍了一种用于bluetooth的基于0.35μm CMOS工艺的2.4GHz正交输出频率综合器的设计和实现.采用差分控制正交耦合压控振荡器实现I/Q信号的产生.为了降低应用成本,利用一个二阶环路滤波器以及一个单位增益跨导放大器来代替三阶环路滤波器.频率综合器的相位噪声为-106.15dBc/Hz@1MHz,带内相位噪声小于-70dBc/Hz,3.3V电源下频率综合器的功耗为13.5mA,芯片面积为1.3mm×0.8mm.     

A Low-Voltage Quadrature CMOS VCO Based on Voltage-Voltage Feedback Topology

A novel low-voltage quadrature voltage-controlled oscillator (QVCO) with voltage feedback to the input gate of a switching amplifier is proposed and implemented using the standard TSMC 0.18-mum CMOS 1P6M process. The proposed circuit topology is made up of two low-voltage LC-tank VCOs, where the coupled QVCO is obtained using the transformer coupling technique. At the 0.7-V supply voltage, the output phase noise of the VCO is -124.9 dBc/Hz at 1-MHz offset frequency from the carrier frequency of 2.4GHz, and the figure of merit is -185.35dBc/Hz. Total power consumption is 5.18 mW. Tuning range is about 135 MHz while the control voltage was tuned from 0 to 0.7V     

CMOS Quadrature VCO Implemented With Two First-Harmonic Injection-Locked Oscillators

This letter presents a new quadrature voltage-controlled oscillator (QVCO). The LC-tank QVCO consists of two first-harmonic injection-locked oscillators (ILOs). The outputs of one ILO are injected to the gates of the tail transistors on the other ILO and vice versa so as to force the two ILOs operate in quadrature. The proposed CMOS QVCO has been implemented with the TSMC 0.18 mum CMOS technology and the die area is 0.582 times 0.972 mm². At the supply voltage of 1.0 V, the total power consumption is 8.0 mW. The free-running frequency of the QVCO is tunable from 5.31 GHz to 5.75 GHz as the tuning voltage is varied from 0.0 V to 1.0 V. The measured phase noise at 1 MHz offset is -120.01 dBc/Hz at the oscillation frequency of 5.31 GHz and the figure of merit (FOM) of the proposed QVCO is about -185.48 dBc/Hz.     

A 0.22 V Quadrature VCO in 90 nm CMOS Process

This letter presents an ultra-low voltage quadrature voltage-controlled oscillator (QVCO). The LC-tank QVCO consists of two low-voltage voltage-controlled oscillators (VCOs) with the body dc biased at the drain bias through a resistor. The superharmonic and back-gate coupling techniques are used to couple two differential VCOs to run in quadrature. The proposed CMOS QVCO has been implemented with the UMC 90 nm CMOS technology and the die area is 0.827 $, times ,$0.913 mm $^{2}$. At the supply voltage of 0.22 V, the total power consumption is 0.33 mW. The free-running frequency of the QVCO is tunable from 3.42 to 3.60 GHz as the tuning voltage is varied from 0.0 to 0.3 V. The measured phase noise at 1 MHz offset is ${-}112.97$ dBc/Hz at the oscillation frequency of 3.55 GHz and the figure of merit (FOM) of the proposed QVCO is about ${-}188.79$ dBc/Hz.      

A symmetrical 6-GHz fully integrated cascode coupling CMOS LC quadrature VCO

A fully symmetrical integrated quadrature LC oscillator with a wide tuning range of 1.2GHz is presented. The quadrature voltage-controlled oscillator (QVCO) is implemented using a symmetrical coupling method which has been used to produce the large tuning range with a low control voltage and to achieve good phase noise performance in 0.18/spl mu/m complementary metal oxide semiconductor technology. The measured phase noise at 1MHz offset from the center frequency (5.5GHz) is -115 dBc/Hz. The QVCO draws 3.2mA from a 1.8V supply. The equivalent phase error between I and Q signal was at most 0.5/spl deg/.     

CMOS second-harmonic quadrature voltage controlled oscillator using substrate for coupling

In this work, a new circuit configuration for second-harmonic quadrature voltage controlled oscillator (QVCO) with CMOS technology is proposed. The proposed QVCO is made by coupling two identical cross-connected VCOs. The coupling elements (two resistors and two capacitors) do not increase the power consumption of the core VCOs and do not disturb the resonant frequency of the tank circuit in the core VCOs and also, according to the simulations the coupling elements do not adversely affect the phase noise. The role of the substrate terminal of cross-connected MOSFETs of the core oscillators as common mode nodes is demonstrated. Using this node for coupling makes it possible to eliminate the tail transistors in the core oscillators and therefore the circuit can operate with supply voltages as low as 0.5 V. Using the same method to couple more than two core oscillators, results in a multiphase VCO.     

5-GHz Low-Phase Noise CMOS Quadrature VCO

A 5-GHz low-phase noise CMOS quadrature voltage controlled oscillator (QVCO) is described. Two differential pairs (one for negative gm generation and the other one for the coupling input) of each resonator have separate biasing transistors which are switched on and off by the coupling input of each resonator. The proposed QVCO implemented in a 0.13-mum CMOS technology shows 17-dB phase noise improvement from a conventional QVCO with constant tail current sources while the two QVCOs consume the same power of 5.28mW. The phase noise of the proposed QVCO is measured to be -102dBc/Hz and -117dBc/Hz at 100KHz and 1-MHz offset, respectively     

Low-power CMOS LC QVCO using zero-biased transistor coupling of MWCNT network-based VCO structure

This paper presents design, analysis and implementation of a 2.4 GHz QVCO (Quadrature Voltage Controlled Oscillator), for low-power, low-voltage applications. Cross coupled LC VCO (Inductor–Capacitor Voltage Controlled Oscillator) topology realized using integration of a micro-scaled capacitor and a MWCNT (Multi-Wall Carbon Nano-Tube) network based inductor together with the CMOS circuits is utilized together with MOS transistors as coupling elements to realize QVCO. With the passive coupling achieved from the MOS transistors, power consumption is minimized while maintaining a small chip area. The variable capacitors and the inductors are designed using ANSYS and imported through DAC components in ADS (Advanced Design software). Accurate simulation of the QVCO is performed in the software environments and the results are provided. The measurement results show that the QVCO provides quadrature signals at 2.4 GHz and achieves a phase noise of −130 dBc/Hz 1 MHz away from the carrier frequency. The VCO produces frequency tuning from 2.1 GHz to 2.60 GHz (20.83%) with a control voltage varying from 0 to 0.3 V. It achieves a peak to peak voltage of 0.59 V with an ultra low power consumption of 3.8 mW from a 0.6 V supply voltage. The output power level of the QVCO is −10 dBm, with an improved quality factor of 45. The phase error of the QVCO is measured as 3.1°.     

A 6-GHz capacitively-coupled Colpitts CMOS quadrature voltage controlled oscillator

In this work a new low-noise low-power Colpitts quadrature voltage controlled oscillator (QVCO) made by coupling two identical current-switching differential Colpitts voltage controlled oscillators (VCO) is proposed; coupling of the VCOs is done using some capacitors in an “in-phase anti-phase” scheme. In this coupling configuration first harmonics (as well as higher harmonics) from each VCO are injected to the other VCO, as opposed to coupling schemes in which only even harmonics are injected. An analysis of the linearized circuit which confirms 90° phase difference between output signals of the proposed circuit is presented. Since no extra noise sources or power consumption are introduced to the core VCOs, the proposed QVCO achieves low phase noise performance and low power consumption. The proposed circuit is designed and simulated in a commercial 0.18 μm CMOS technology. The simulated phase noise of the proposed QVCO at 3 MHz offset frequency is ?138.3 dBc/Hz, at 6 GHz. The circuit dissipates 8.16 mW from a 1.8 V supply and its frequency can be tuned from 5.6 to 6.3 GHz.     

System simulations of a 1.5 V SiGe 81–86 GHz E-band transmitter

This paper presents simulation results for a sliding-IF SiGe E-band transmitter circuit for the 81–86 GHz E-band. The circuit was designed in a SiGe process with f _T  = 200 GHz and uses a supply of 1.5 V. The low supply voltage eliminates the need for a dedicated transmitter voltage regulator. The carrier generation is based on a 28 GHz quadrature voltage oscillator (QVCO). Upconversion to 84 GHz is performed by first mixing with the QVCO signals, converting the signal from baseband to 28 GHz, and then mixing it with the 56 GHz QVCO second harmonic, present at the emitter nodes of the QVCO core devices. The second mixer is connected to a three-stage power amplifier utilizing capacitive cross-coupling to increase the gain, providing a saturated output power of +14 dBm with a 1 dB output compression point of +11 dBm. E-band radio links using higher order modulation, e.g. 64 QAM, are sensitive to I/Q phase errors. The presented design is based on a 28 GHz QVCO, the lower frequency reducing the phase error due to mismatch in active and passive devices. The I/Q mismatch can be further reduced by adjusting varactors connected to each QVCO output. The analog performance of the transmitter is based on ADS Momentum models of all inductors and transformers, and layout parasitic extracted views of the active parts. For the simulations with a 16 QAM modulated baseband input signal, however, the Momentum models were replaced with lumped equivalent models to ease simulator convergence. Constellation diagrams and error vector magnitude (EVM) were calculated in MATLAB using data from transient simulations. The EVM dependency on QVCO phase noise, I/Q imbalance and PA compression has been analyzed. For an average output power of 7.5 dBm, the design achieves 7.2% EVM for a 16 QAM signal with 1 GHz bandwidth. The current consumption of the transmitter, including the PA, equals 131 mA from a 1.5 V supply.     

A very low-power quadrature VCO with back-gate coupling

A new quadrature voltage-controlled oscillator (QVCO) topology is proposed where the back-gates of the core transistors are used as coupling terminals. The use of back-gates reduces the power dissipation and removes the additional noise contributions compare to the conventional coupling transistor based topology. The advantages of the proposed QVCO topology in comparison with prior works are exploited based on simulation. A QVCO based on the proposed topology with additional design ideas has been implemented using a 0.18-/spl mu/m triple-well technology for 1 GHz-band operation, and measurement shows the phase noise of -120 dBc/Hz at 1-MHz offset with output power of 2.5 dBm, while dissipating only 3 mA for the whole QVCO from 1.8-V supply.     

Analysis of resonator phase shift for two series LC quadrature VCOs

Based on the investigation of resonator phase shift, an analytical framework to compare the phase noise between two series LC quadrature voltage-controlled oscillators (QVCOs) is presented. The bottom- series QVCO is analytically demonstrated to have lower phase noise than the top-series QVCO. Simulation data show good agreement with the presented analysis.     

Bottom-series coupled quadrature VCO using the inductive gate voltage boosting technique

This article presents a new low-voltage bottom-series coupled quadrature voltage-controlled oscillator (QVCO), which consists of two n-core cross-coupled VCOs with the bottom-series coupling transistors. The low-voltage operation is obtained via an inductive gate voltage boosting technique. The proposed CMOS QVCO has been implemented with the TSMC 0.18?µm CMOS technology and the die area is 0.897?×?0.767?mm². At the supply voltage of 0.7?V, the total power consumption is 1.5?mW. The free-running frequency of the QVCO is tuneable from 3.77 to 4.12?GHz as the tuning voltage is varied from 0.0 to 0.7?V. The measured phase noise at 1?MHz frequency offset is ?123.35?dBc/Hz at the oscillation frequency of 4.12?GHz and the figure of merit of the proposed QVCO is ?193.5?dBc/Hz.