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Classical and modern receiver architectures 总被引:4,自引:0,他引:4
This article is a review of several classical and modern wireless receiver architectures used in wideband wireless communication systems. The emphasis is on configurations suitable for integration on a single silicon chip. A full understanding of the design trade-offs discussed in this article is necessary for the proper introduction of a new modulation scheme presented in the article by Mirabbasi and Martin (2000) entitled, "Hierarchical QAM: a spectrally efficient DC-free modulation scheme". 相似文献
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As devices shrink, creating integrated circuits (ICs) that work with the required accuracy becomes more difficult due to issues related to device physics. Receivers are part of an area referred to as "mixed-signal design," meaning that both analog and digital circuitry will be on the same IC. This too presents many challenging issues, as the analog circuitry is highly sensitive to disruptions caused by the noisy digital circuitry. Therefore, accurate modeling and simulation is crucial in the design of wireless receivers to ensure the best possible operation of the fabricated IC. Through simulation and modeling a designer can determine if receiver architecture will meet the required specifications and pinpoint the possible problems before valuable time is spent developing the actual circuit. This article will present design issues for multistandard wireless receivers to give the reader an understanding of the challenges involved in link-budget analysis. TITAN (Toolbox for Integrated Transceiver Analysis), a link-budget analysis tool developed at The Ohio State University Analog VLSI Laboratory, will be presented as an example of a tool for receiver simulation. To determine design performance, various requirements must be translated to model parameters. Among the requirements for receivers are noise floor (NF), second- and third-order distortion (IP2 and IP3, respectively), reciprocal mixing, and phase noise. TITAN offers a graphical interface and encapsulated models to the designer, eliminating the possibility of formula corruption. The interface provides a more intuitive and sophisticated way of setting up the simulation and provides the designer with more readable results. Additionally, a blocking profile component allows the architecture to be tested across multiple standards. 相似文献
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提出一种基于EM411GPS接收模块和PIC18F2520单片机的手持式GPS接收机设计方案。该方案具有电路简单、成本低、灵敏度高等优点,并可将接收的数据以FAT文件格式保存到SD卡中,通过SD卡将GPS数据导入电子地图,便于野外作业和户外运动使用。 相似文献
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便携式GPS接收机设计 总被引:1,自引:0,他引:1
提出一种基于EM411 GPS接收模块和PIC18F2520单片机的手持式GPS接收机设计方案.该方案具有电路简单、成本低、灵敏度高等优点,并可将接收的数据以FAT文件格式保存到SD卡中,通过SD卡将GPS数据导入电子地图,便于野外作业和户外运动使用. 相似文献
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Fei Xiang Guisheng Liao Cao ZengWeiwei Wang 《AEUE-International Journal of Electronics and Communications》2013,67(10):839-847
A novel technique for mitigating the multipath-induced code delay estimation error in Global Positioning System (GPS) is proposed. In contrast to conventional methods that aim to eliminate multipath signals, the proposed method exploits them to enhance the direct signal without affecting the accuracy of GPS code delay estimates. To achieve this, coherent accumulation of the received GPS signals is first done by transforming the received data into frequency domain and the parameters of multipath signals are then estimated by sparse reconstruction algorithm. Subsequently, a modified local reference signal is employed in delay lock loop (DLL) of the GPS receiver, which mitigates the pseudo-range estimation error and increases the correlation value of direct GPS signal. Simulation results demonstrate the performance and robustness of the proposed method. 相似文献
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一种多级GPS抗干扰接收机设 总被引:2,自引:0,他引:2
针对空时联合处理在GPS抗干扰方面应用时其性能取决于天线阵元数,从而带来计算量和体积增大的问题,提出了一种多级抗干扰GPS接收机的设计方法,在与空时联合处理同样的抗干扰性能的情况下具有较小的复杂度。最后给出的仿真结果表明其在减少运算量、提高抗干扰性能方面有优势。 相似文献
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Two conceptually different p-i-n FET receiver circuit architectures are evaluated using a SPICE circuit simulation. The popular p-i-n FET transimpedance amplifier is compared to a new architecture that uses distributed gain and dual feedback. To highlight the importance of circuit architecture to receiver performance, identical device parameters are used in each circuit model. Frequency, phase, and pulse responses are computed and presented in graphical form. Results demonstrate that the popular receiver is adversely sensitive to FET transconductance variations and distorts the pulse reponse, whereas the distributed gain and dual feedback design is substantially independent of transistor parameters and free of pulse distortion. 相似文献
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《Electron Devices, IEEE Transactions on》1985,32(12):2699-2703
Two conceptually different p-i-n FET receiver circuit architectures are evaluated using a SPICE circuit simulation. The popular p-i-n FET transimpedance amplifier is compared to a new architecture that uses distributed gain and dual feedback. To highlight the importance of circuit architecture to receiver performance, identical device parameters are used in each circuit model. Frequency, phase, and pulse responses are computed and presented in graphical form. Results demonstrate that the popular receiver is adversely sensitive to FET transconductance variations and distorts the pulse reponse, whereas the distributed gain and dual feedback design is substantially independent of transistor parameters and free of pulse distortion. 相似文献
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A novel correlator architecture for handling the satellite-to-receiver time skew in a Global Positioning System (GPS) receiver is presented. The correlator's signal integration and numerically-controlled oscillator updates are referenced to receiver time epochs rather than satellite epochs as in traditional architectures. To avoid straddling navigation data bits, the correlation is split into two parts. The technique was successfully implemented and integrated into a field programmable gate array-based multichannel software GPS receiver 相似文献