一种高可靠性、低功耗单节锂电池保护电路

A single lithium-ion battery protection circuit with high reliability and low power consumption is proposed.The protection circuit has high reliability because the voltage and current of the battery are controlled in a safe range.The protection circuit can immediately activate a protective function when the voltage and current of the battery are beyond the safe range.In order to reduce the circuit’s power consumption,a sleep state control circuit is developed.Additionally,the output frequency of the ring oscillation can be adjusted continuously and precisely by the charging capacitors and the constant-current source.The proposed protection circuit is fabricated in a 0.5 m mixed-signal CMOS process.The measured reference voltage is 1.19 V,the overvoltage is 4.2 V and the undervoltage is 2.2 V.The total power is about 9 W.     

引入悬浮栅对有机薄膜晶体管的阈值电压进行调整

The structure of organic thin film transistors (OTFTs) is optimized by introducing floating gate into the gate dielectric to reduce the threshold voltage of OTFTs in this article. Then the optimized device is simulated and the results of the simulation show the threshold voltage of optimized device is reduced by about 10 V. The reduction of the threshold voltage is helpful and useful for the application of OTFTs in many areas. In addition, this way to reduce threshold voltage of OTFT is compatible with traditional silicon technology and can be used in manufacture.     

Characterization of a room temperature terahertz detector based on a GaN/AlGaN HEMT

We report on the characterization of a room temperature terahertz detector based on a GaN/AlGaN high electron mobility transistor integrated with three patch antennas.Experimental results prove that both horizontal and perpendicular electric fields are induced in the electron channel.A photocurrent is generated when the electron channel is strongly modulated by the gate voltage.Despite the large channel length and gate-source/drain distance, significant horizontal and perpendicular fields are achieved.The device is well described by the self-mixing of terahertz fields in the electron channel.The noise-equivalent power and responsivity are estimated to be 100 nW/（Hz）^1/2 and 3 mA/ W at 292 K,respectively.No decrease in responsivity is observed up to a modulation frequency of 5 kHz. The detector performance can be further improved by engineering the source-gate-drain geometry to enhance the nonlinearity.     

A novel HBT trigger SCR in 0.35 μm SiGe BiCMOS technology

The silicon-controlled rectifier (SCR) device is known as an efficient electrostatic discharge (ESD) protection device due to the highest ESD robustness in the smallest layout area. However, SCR has some drawbacks, such as high trigger voltage and low holding voltage. In order to reduce the trigger voltage of the SCR device for ESD protection, a new heterojunction bipolar transistor (HBT) trigger silicon controlled rectifier (HTSCR) device in 0.35 μm SiGe BiCMOS technology are proposed. The underlying physical mechanisms critical to the trigger voltage are demonstrated based on transmission line pulsing (TLP) measurement and physics-based simulation results. The simulation results prove that the trigger voltage of the HTSCR is decided by the collector-to-emitter breakdown voltage of the HBT structure in floating base configuration. The ESD experiment test results demonstrate the HTSCR can offer superior performance with a small trigger voltage, an adjustable holding voltage and a high ESD robustness. In comparison to the conventional MLSCR, the trigger voltage of the fabricated HTSCR can reduce to less than 50% of that of the MLSCR, and the I_t2 of the HBT trigger SCR is 80% more than that of the MLSCR.     

Design of Diode Type Un-Cooled Infrared Focal Plane Array Readout Circuit

The diode infrared focal plane array uses the silicon diodes as a sensitive device for infrared signal measurement. By the infrared radiation, the infrared focal plane can produces small voltage signals. For the traditional readout circuit structures are designed to process current signals, they cannot be applied to it. In this paper,a new readout circuit for the diode un-cooled infrared focal plane array is developed. The principle of detector array signal readout and small signal amplification is given in detail. The readout circuit is designed and simulated by using the Central Semiconductor Manufacturing Corporation (CSMC) 0.5 μm complementary metal-oxide-semiconductor transistor (CMOS) technology library. Cadence Spectre simulation results show that the scheme can be applied to the CMOS readout integrated circuit (ROIC) with a larger array, such as 320×240 size array.     

A novel double-trench LVTSCR used in the ESD protection of a RFIC

A low-voltage triggering silicon-controlled rectifier(LVTSCR),for its high efficiency and low parasitic parameters,has many advantages in ESD protection,especially in ultra-deep sub-micron(UDSM) IC and high frequency applications.In this paper,the impact factors of the snapback characteristics of a LVTSCR and the configuring modes are analyzed and evaluated in detail.These parameters include anode series resistance,gate voltage,structure and size of devices.In addition,a double-trench LVTSCR is presented that can increase the hold-on voltage effectively and offers easy adjustment.Also,its snapback characteristics can obey the ESD design window rule very well.The strategy of ESD protection in a RFIC using a LVTSCR is discussed at the end of the paper.     

Transient analysis of nonuniform transmission lines with nonlinear terminal networks

A semi-analytical method in time domain is presented for analysis of the transient response of nonuniform transmission lines. In this method, the telegraph equations in time domain is differenced in space domain first, and is transformed into a set of first-order differential equations of voltage and current with respect to time. By integrating these differential equations with respect to time, and precise computation, the solution of these differential equations can be obtained. This method can solve the transient response of various kinds of transmission lines with arbitrary terminal networks. Particularly, it can analyze the nonuniform lines with initial conditions, for which there is no existing effective method to analyze the time response so far. The results obtained with this method are stable and accurate. Two examples are given to illustrate the application of this method.     

DETECTION IN WEIBULL AND LOG-NORMAL NOISES

The discrete-time detection of narrowband coherent and incoherent pulse train signals in nar-rowband non-Gaussian noise is investigated.The locally optimum(LO)detector structures aredeveloped and found to be in the form of incorporating a locally optimum zero-memory nonlinear-ity(LOZNL)into the Neyman-Pearson optimum detector for narrowband Gaussian noise.Manypractical detectors belong in the same class of structures with the LO detector.The expressions forthe efficacies of the detectors are derived.In particular,Weibull and log-normal noise models areconsidered.The LOZNL's,and the efficacies of the detectors are given,and numerical results aregraphically presented.It is shown that,in the sense of the Pitman asymptotic relative efficiency(ARE),the asymptotic performance of many detectors whose nonlinearity can more effectively suppressthe tail of the noise envelope distribution is apparently better than that of the Neyman-Pearson opti-mum detector for narrowband Gaussian noise.     

Ultra-Low Power Pipeline Structure Exploiting Noncritical Stage with Circuit-Level Timing Speculation

With the increase of the clock frequency and silicon integration,power aware computing has become a critical concern in the design of the embedded processor and system-on-chip(SoC).Dynamic voltage scaling(DVS) is an effective method for low-power designs.However,traditional DVS methods have two deficiencies.First,they have a conservative safety margin which is not necessary for most of the time.Second,they are exclusively concerned with the critical stage and ignore the significant potential free slack time of the noncritical stage.These factors lead to a large amount of power waste.In this paper,a novel pipeline structure with ultra-low power consumption is proposed.It cuts off the safety margin and takes use of the noncritical stages at the same time.A prototype pipeline is designed in 0.13 m technology and analyzed.The result shows that a large amount of energy can be saved by using this structure.Compared with the fixed voltage case,50% of the energy can be saved,and with respect to the traditional adaptive voltage scaling design,37.8% of the energy can be saved.     

ADAPTIVE NONPARAMETRIC DETECTOR ON CORRELATION GAUSSIAN NOISE

The problem of adaptive nonparametric detector in correlation Gaussian noise isconsidered.The nonparametric detectors are CFAR(Constant-False-Alarm-Rate)detectors,whenthe input received reference cells are IID(Identical Independent Distribution)variances.But the falsealarm probability(P_(fa))of the nonparametric detectors could not be constant if the samples of thereference range cells are not independent.A simple and easily implemented adaptive nonparametricdetection method is proposed in the paper.In orde to maintain CFAR the weight of the detection rangecell of the detector must be changed by different output values of the IIR filter for measurement of thecorrelation coefficient(p)of the input noise.In this paper the closed form expressions for detectionprobability(P_d)and P_(fa)of the weighted nonparametric detector are derived.The ARE(AsymptoticRelative Efficiency)of the weighted detectors is investigated.In the end the detection performance ofthe adaptive nonparametric detector is determined by Monte Carlo simulation on the digital computer.     

一种新型的用浮空场限环实现的可集成在SPIC中的高压电压探测器

提出一种可以集成在 SPIC(智能功率集成电路 )内部的高压电压探测器的方法 ,其理论是基于基本的结终端技术中的浮空场限环系统 ,把场限环系统作为表面电压分压器 .在通常的场限环外侧再增加两个环 ,对外侧环电压再一次分压 ,并把最外侧环设计成高压电压探测器 .这样当主结电压上升到一个高压时 ,最外侧的环可以只有几伏到十几伏的变化 ,这样环 (探测器 )上的信号既可以表征主结高电压 ,又可以由低压逻辑电路处理 .以一个 40 0 V的结构为例 ,分析并模拟了这个结构 .结果证明可以有效探测 SPIC的高压并可以集成在 SPIC中 .同时 ,该结构可以与 CMOS和 BCD     

一种新型的用浮空场限环实现的可集成在SPIC中的高压电压探测器*

提出一种可以集成在SPIC(智能功率集成电路)内部的高压电压探测器的方法,其理论是基于基本的结终端技术中的浮空场限环系统,把场限环系统作为表面电压分压器.在通常的场限环外侧再增加两个环,对外侧环电压再一次分压,并把最外侧环设计成高压电压探测器.这样当主结电压上升到一个高压时,最外侧的环可以只有几伏到十几伏的变化,这样环(探测器)上的信号既可以表征主结高电压,又可以由低压逻辑电路处理.以一个400V的结构为例,分析并模拟了这个结构.结果证明可以有效探测SPIC的高压并可以集成在SPIC中.同时,该结构可以与CMOS和BCD工艺兼容,且工艺上也不会增加步骤.     

灵巧功率集成电路中功率MOSFET电流感知方法的研究

功率器件的过流保护是提高灵巧功率集成电路可靠性的关键,采用不同的电流检测方法会有不同的误差。通过对功率MOSFET的电流检测技术的研究,对比分析了几种常用的电流感知方法,重点阐述了应用在灵巧功率集成电路中感知高压功率器件电流的SenseFET结构的工作原理,并分析了影响电流检测准确度的误差源。可以为设计高性能的电流检测过程提供参考。     

A mixed-mode voltage down converter with impedance adjustmentcircuitry for low-voltage high-frequency memories

This paper proposes a low voltage operation technique for a voltage down converter (VDC) using a mixed-mode VDC (MM-VDC), that combines an analog VDC and a digital VDC, and provides high frequency application using an impedance adjustment circuitry (IAC). The MM-VDC operates with a small response delay and a large supply current. Moreover, the IAC is adopted by the MM-VDC for wide range frequency operation under low voltage conditions. The IAC can change the supply current capability in accordance with the load operation frequency to avoid the overshoot and undershoot problems caused by the unmatched supply current. A 64 Mb-DRAM test device operated with the MM-VDC achieves well-controlled internal voltage (VCI) level and achieves high frequency operation. These systems, the MM-VDC and the IL-VDC, can be applicable for both low voltage and high frequency operation     

一种新型的具有简易APFC的SPIC电路

提出了一种新型的具有简易APFC的单片SPIC电路.通过采用集成在SPIC内部的延迟电路,使有APFC电路的总线电压由600V下降为400V.在电路中,采用长沟道的NMOS管来代替大电阻以节省版图面积.在保证所需的功率因数的情况下,总线电压的下降可以直接导致功率开关器件的比导通电阻下降,减小功率器件的损耗,提高电路的效率.同时,总线电压下降,也使电路成本降低.此外,还同时设计了相应的高压过压保护电路.理论分析与模拟结果都证明该设计是正确的和有效的.     

A voltage down converter with submicroampere standby current forlow-power static RAMs

A submicroampere standby current voltage downconverter (VDC) for high-density, low-power static RAMs is described. The current consumption of the VDC in standby mode can be decreased by using a novel low-current and temperature-independent current source circuit. The total current is less than 0.5 μA at external voltage ranging from 3 to 5 V and at temperatures ranging from -20 to 80°C. The voltage-follower circuits for standby and operation modes are stable despite the low current consumption in the standby mode. The phase margin of the voltage follower for standby mode is 50°, and that for operation mode is 90°. This indicates that the VDC is a promising circuit for battery-backup and high-density static RAMs     

一种新型的具有简易APFC的SPIC电路

提出了一种新型的具有简易APFC的单片SPIC电路.通过采用集成在SPIC内部的延迟电路,使有APFC电路的总线电压由600V下降为400V.在电路中,采用长沟道的NMOS管来代替大电阻以节省版图面积.在保证所需的功率因数的情况下,总线电压的下降可以直接导致功率开关器件的比导通电阻下降,减小功率器件的损耗,提高电路的效率.同时,总线电压下降,也使电路成本降低.此外,还同时设计了相应的高压过压保护电路.理论分析与模拟结果都证明该设计是正确的和有效的.     

A 3 /spl mu/m NMOS high-performance LPC speech synthesizer chip

A high performance speech processing integrated circuit (SPIC) based on linear predictive coding (LPC) techniques is presented. Both system and technological aspects of the SPCI design are covered in detail. The SPIC synthesizer chip will normally be used in a three-chip minimum system configuration including the synthesizer, a microcomputer, and an external vocabulary ROM. The speech quality can be tailored to the user's requirements by varying the bit rate between the vocabulary ROM and the microcomputer from 1.1 to 8.5 kbit/s. Among the specific features of the SPIC are pitch synchronous synthesis, speech parameters interpolation capability, silence, and power-down mode. Moreover, the digital filter output is interpolated at a high sampling rate (32 kHz) to avoid the necessity for off-chip filtering. An 8-bit PCM output (A law) and a 16-bit linear-coded output are provided. The SPIC can be delivered in two different bonding configurations either for small system application (three-chip system) or for larger system configuration.     

一种应用于PD的高精度限流保护调节电路

在POE(PowerOverEthernet)系统的终端受电设备中,限流保护调节电路保证了其稳定可靠工作。根据IEEE802.3af标准规定,受电设备开关电源启动到正常工作的过程中,电流要限制在100mA以内,在正常工作情况下电流要限制在390mA以下。本设计通过栅源比例电阻使采样功率管栅源电压与输出功率管的栅源电压保持一致,采样功率管精确采样输出功率管的电流值,采样电流经栅源比例电阻转换为电压后,调节输出功率管栅源电压,来完成PD(PowerDevice)限流保护。     

级联式Buck-Boost校正电路在高压电子镇流器中的应用

本文提出了一种带有无源无损缓冲结构的级联式buck-boost校正电路,并成功地应用在高压式电子镇流器中.缓冲电路通过抑制反向恢复电流所引起的di/dt和漏源极电压的dv/dt,有效地减少了开关损耗和EMI噪音.Buck电路中的IGBT实现零电流开通和零电压关断,同时续流二极管也工作在零电压状态.研制的380 V交流输入,400 V直流输出,额定功率600W的实验样机,其功率因数达0.98,THD小于11%.