Improved charge control and frequency performance inInAs/AlSb-based heterostructure field-effect transistors

We demonstrate high-speed InAs/AlSb-based heterostructure field-effect transistors (HFET's) displaying greatly improved charge control properties and enhanced high-frequency gate performance. Microwave devices with a 0.5×84 μm² exhibit a peak unity current gain cut-off frequency of f_T=93 GHz. The HFET usable operational range was extended to V_DS=1.5 V (from V _DS=0.4-0.5 V) thus greatly enhancing the applicability of InAs/AlSb-based HFET's for low-power, high-frequency amplification. We also report on the bias dependence of f_T, and demonstrate that InAs/AlSb-based HFET's offer an attractive frequency performance over an adequately wide range of drain biases     

Nonlinear source and drain resistance in recessed-gateheterostructure field-effect transistors

We have profiled the parasitic source and drain resistances versus current in recessed-gate HFET's with heavily-doped caps, using an InAlAs/n⁺-InP HFET as a vehicle. We observe a dramatic reduction in the parasitic resistances at moderate-to-high currents as significant current passes through the cap. Consequently, we note very little dependence in g, on the length of the extrinsic gate-source region. This is an experimental verification of predictions of two-layer models in the literature     

High-transconductance delta-doped InAs/AlSb HFETs with ultrathinsilicon-doped InAs quantum well donor layer

Modulation-doping of InAs/AlSb quantum wells generally requires the use of chalcogenide donor impurities because silicon, the usual donor of choice in MBE, displays an amphoteric behavior in antimonide compounds. In this letter, we demonstrate the use of an ultrathin 9 Å silicon doped InAs well to delta-dope the current-carrying InAs channel of an InAs/AlSb heterostructure field-effect transistor (HFET). Using this new approach, we have fabricated delta-doped 0.6-μm gate InAs/AlSb HFETs with a measured extrinsic transconductance of 800 mS/mm at V_DS=0.8 V, a cutoff frequency f_T=60 GHz (F_MAX=87 GHz), and well-behaved I-V curves. HFET's with a 2-μm gatelength also feature very high transconductances in the 700-800 mS/mm range at V_DS=1.5 V. The present work eliminates the requirement for chalcogenide compound donor sources to delta-dope InAs/AlSb quantum wells by allowing the use of silicon in the fabrication of high-performance InAs/AlSb HFET's     

Impact ionization suppression by quantum confinement: Effects onthe DC and microwave performance of narrow-gap channel InAs/AlSb HFET's

InAs/AlSb heterostructure field-effect transistors (HFET's) are subject to impact ionization induced short-channel effects because of the narrow InAs channel energy gap. In principle, the effective energy gap to overcome for impact ionization can be increased by quantum confinement (channel quantization) to alleviate impact ionization related nonidealities such as the kink effect and a high gate leakage current. We have studied the effects of quantum well thickness on the dc and microwave performance of narrow-gap InAs/AlSb HFET's fabricated on nominally identical epitaxial layers which differ only by their quantum well thickness. We show that a thinner quantum well postpones the onset of impact ionization and suppresses short-channel effects. As expected, the output conductance g_DS and the gate leakage current are reduced. The f_MAX/f_T ratio is also significantly improved when the InAs well thickness is reduced from 100 to 50 Å. The use of the thinner well reduces the cutoff frequency f_T, the transconductance g_m, and the current drive because of the reduced low-field mobility due to interface roughness scattering in thin InAs/AlSb channel layers: the low-field mobility was μ=21 000 and 9000 cm²/Vs for the 100- and 50-Å quantum wells, respectively. To our knowledge, the present work is the first study of the link between channel quantization, in-plane impact ionization, and device performance in narrow-gap channel HFET's     

Epitaxially-grown GaN junction field effect transistors

Junction field effect transistors (JFETs) are fabricated on a GaN epitaxial structure grown by metal organic chemical vapor deposition (MOCVD). The dc and microwave characteristics of the device are presented. A junction breakdown voltage of 56 V is obtained corresponding to the theoretical limit of the breakdown field in GaN for the doping levels used. A maximum extrinsic transconductance (g_m ) of 48 mS/mm and a maximum source-drain current of 270 mA/mm are achieved on a 0.8 μm gate JFET device at V_GS=1 V and V_DS=15 V. The intrinsic transconductance, calculated from the measured g_m and the source series resistance, is 81 mS/mm. The f_T and f_max for these devices are 6 GHz and 12 GHz, respectively. These JFET's exhibit a significant current reduction after a high drain bias is applied, which is attributed to a partially depleted channel caused by trapped hot-electrons in the semi-insulating GaN buffer layer. A theoretical model describing the current collapse is presented, and an estimate for the length of the trapped electron region is given     

0.10 μm graded InGaAs channel InP HEMT with 305 GHzfT and 340 GHz fmax

We report here 305 GHz f_T, 340 GHz f_max, and 1550 mS/mm extrinsic g_m from a 0.10 μm In_xGa _1-xAs/In_0.62Al_0.48As/InP HEMT with x graded from 0.60 to 0.80. This device has the highest f_T yet reported for a 0.10 μm gate length and the highest combination of f _T and f_max reported for any three-terminal device. This performance is achieved by using a graded-channel design which simultaneously increases the effective indium composition of the channel while optimizing channel thickness     

Two-dimensional metal-semiconductor field effect transistor forultra low power circuit applications

We describe a novel 2-dimensional metal-semiconductor field effect transistor (2-D MESFET) in which opposing Schottky side gates formed on the sidewall of a modulation-doped AlGaAs-InGaAs heterostructure modulate the channel width and the drain current. The drain current ranged from 0 to 210 μA and the maximum measured transconductance was 212 μS (212 mS/mm) at room temperature for a 1×1 micron channel. The threshold voltage was -0.45 V and the subthreshold ideality factor was 1.30. The estimated gate capacitance was 0.8 fF/μm, or about half the equivalent capacitance of conventional HFET's. The cutoff frequency f_T was estimated to be 21 GHz. The narrow channel effect, which limits the minimum power consumption in conventional FET's, is practically eliminated in this device     

Demonstration of submicron depletion-mode GaAs MOSFETs withnegligible drain current drift and hysteresis

We successfully fabricated submicron depletion-mode GaAs MOSFETs with negligible hysteresis and drift in drain current using Ga₂ O₃(Gd₂O₃) as the gate oxide. The 0.8-μm gate-length device shows a maximum drain current density of 450 mA/mm and a peak extrinsic transconductance of 130 mS/mm. A short-circuit current gain cutoff frequency (f_T) of 17 GHz and a maximum oscillation frequency (f_max) of 60 GHz were obtained from the 0.8 μm×60 μm device. The absence of drain current drift and hysteresis along with excellent characteristics in the submicron devices is a significant advance toward the manufacture of commercially useful GaAs MOSFETs     

Cat-CVD SiN-passivated AlGaN-GaN HFETs with thin and high Al composition barrier Layers

The effect of SiN surface passivation by catalytic chemical vapor deposition (Cat-CVD) on Al/sub 0.4/Ga/sub 0.6/N-GaN heterostructure field-effect transistors (HFETs) was investigated. The channel sheet resistance was reduced by the passivation due to an increase in electron density, and the device characteristics of the thin-barrier HFETs were significantly improved by the reduction of source and drain resistances. The AlGaN(8 nm)-AlN(1.3 nm)-GaN HFET device with a source/drain distance of 3 /spl mu/m and a gate length of 1 /spl mu/m had a maximum drain current density of 0.83 A/mm at a gate bias of +1.5 V and an extrinsic maximum transconductance of 403 mS/mm. These results indicate the substantial potential of Cat-CVD SiN-passivated AlGaN-GaN HFETs with thin and high Al composition barrier layers.     

Extrapolated fmax of heterojunction bipolar transistors

It is shown that the extrapolated f_max of heterojunction bipolar transistors (HBT's) can be written in the form f _max=√f_T/8π(RC)_eff, where f_T is the common-emitter, unity-current-gain frequency, and where (RC)_eff is a general time constant that includes not only the effects of the base resistance and collector-base junction capacitance, but also the effects of the parasitic emitter and collector resistances, and the dynamic resistance 1/g_m, where g_m is the transconductance. Simple expressions are derived for (RC) _eff, and these are applied to two state-of-the-art devices recently reported in the literature. It is demonstrated that, in modern HBT's, (RC)_eff can differ significantly from the effective base-resistance-collector-capacitance product conventionally assumed to determine f_max     

High speed p-type SiGe modulation-doped field-effect transistors

We report on the fabrication and characterization of high-speed p-type modulation-doped field-effect transistors (MODFETs) with 0.7-μm and 1-μm gate-lengths having unity current-gain cut-off frequencies (f_T) of 9.5 GHz and 5.3 GHz, respectively. The devices were fabricated on a high hole mobility SiGe heterostructure grown by ultra-high-vacuum chemical vapor deposition (UHV-CVD). The dc maximum extrinsic transconductance (g_m) is 105 mS/mm (205 mS/mm) at room temperature (77 K) for the 0.7-μm gate length devices. The fabricated devices show good pinch-off characteristics and have a very low gate leakage current of a few μA/mm at room temperature and a few nA/mm at 77 K     

A closed-loop evaluation and validation of a method for determiningthe scattering limited carrier velocity in MOSFETs

A closed-loop evaluation of a saturation transconductance (g _msat⁽ⁱ⁾) based method for determining the scattering limited carrier velocity (ν_sat) in enhancement MOSFETs was performed with the use of a 2-D device simulator. Consistency in the extracted ν_sat over a wide range of gate oxide thickness (T_ox), channel doping concentration, and bias condition was tested and verified. Also analyzed are the appropriate measurement condition, the significance of the parasitic effect due to the source and drain resistances, the applicability of the method used for compensating this parasitic effect, and the expected accuracy of the extracted ν_sat under ideal conditions. A plausible explanation is provided for the inconsistency between ν_sat determined from g_msat⁽ⁱ⁾(0), the extrapolated transconductance, and ν_sat determined from the slope of [ g_msat⁽ⁱ⁾(0)]^-1 versus T _ox characteristics observed in published results. The g_msat ⁽ⁱ⁾-based method for extracting ν_sat has been applied to MOSFETs fabricated with three vastly different technologies, and the experimentally-based ν_sat of electrons at 300 K ranges from 7.37×10⁶ to 7.92×10⁶ cm/s, which shows its independence of technology     

Effects of Parasitic Capacitance, External Resistance, and Local Stress on the RF Performance of the Transistors Fabricated by Standard 65-nm CMOS Technologies

Effects of parasitic capacitance, external resistance, and local stress on the radio-frequency (RF) performance of the transistors fabricated by 65-nm CMOS technology have been investigated. The effect of parasitic capacitance, particularly C_gb, becomes significant due to the reduced spacing between the gate and the substrate contact (SC) in proportion to scaling down. Current drivability (I_dsat) per unit width has been improved through introduction of mobility enhancement techniques. The influence of external resistance becomes more pronounced for large-dimensional RF transistors due to severe IR drop. Such improved current drivability and large external resistance is responsible for dc performance (g_m) degradation and, eventually, cutoff frequency (f_T) degradation. Local stress effects associated with silicon nitride capping layer and STI stress have been investigated. f_T is largely affected by local stress change, i.e., g_m degradation at minimal gate poly (GP) pitch and gate-to-active spacing, f_T is dominated by increased parasitic capacitance (C_gb) with increasing GP pitch and gate-to-active spacing. Above 10% improvement in f_T has been observed through layout optimization for C_gb reduction by increasing the transistor active-to-SC spacing.     

High-temperature performance of GaAs-based HFET structurecontaining LT-AlGaAs and LT-GaAs

Using low-temperature grown layers a GaAs-based HFET structure was developed, which demonstrates for the first time high performance at high temperatures up to 540°C, where the gate diode shunts through. The device was designed for operation in the hot electron regime using an LT-AlGaAs passivation layer. Thus, the open channel current density and gain bandwidth product are exceptionally stable (I_D500°C /I_DR.T.=0.9; f^T200°Cf_TR.T.=0.9). The f_max cutoff frequency is the most temperature sensitive parameter {(f_max/f_T)_R.T.=3.9 and (f_max/f_T)_200°C=2.8} due to the thermal activation of the buffer layer leakage, which is kept extremely small using LT-GaAs     

0.12-μm gate III-V nitride HFET's with high contact resistances

HFET's with 0.12-μm gate length were fabricated on a III-V nitride wafer. The contact resistance from unannealed Ti/Au ohmic contact was 10 Ω·mm. Even with this relatively high contact resistance, f_T of 46.9 GHz and f_max of 103 GHz were measured with the Ti/Au contacts, the highest yet achieved on III-V nitride FETs. The improvement in the frequency response was mainly due to the decrease in the gate length (0.12 μm). In addition, the effects of high contact resistances at high frequency are discussed     

High-linearity high-current-drivabilityGa0.51In0.49P/GaAs MISFET usingGa0.51In0.49P airbridge gate structure grown byGSMBE

A novel structure Ga_0.51In_0.49P/GaAs MISFET with an undoped Ga_0.51In_0.49P layer serving as the airbridge between active region and gate pad was first designed and fabricated. Wide and flat characteristics of g_m and f_max versus drain current or gate voltage were achieved. The device also showed a very high maximum current density (610 mA/mm) and a very high gate-to-drain breakdown voltage (25 V). Parasitic capacitances and leakage currents were minimized by the airbridge gate structure and thus high f_T of 22 GHz and high f_max of 40 GHz for 1 μm gate length devices were attained. To our knowledge, both were the best reported values for 1 μm gate GaAs channel FET's     

High performance 0.1 μm gate-length p-type SiGe MODFET's andMOS-MODFET's

High performance p-type modulation-doped field-effect transistors (MODFET's) and metal-oxide-semiconductor MODFET (MOS-MODFET) with 0.1 μm gate-length have been fabricated on a high hole mobility SiGe-Si heterojunction grown by ultrahigh vacuum chemical vapor deposition. The MODFET devices exhibited an extrinsic transconductance (g_m) of 142 mS/mm, a unity current gain cut-off frequency (f_T) of 45 GHz and a maximum oscillation frequency (f_MAX) of 81 GHz, 5 nm-thick high quality jet-vapor-deposited (JVD) SiO₂ was utilized as gate dielectric for the MOS-MODFET's. The devices exhibited a lower gate leakage current (1 nA/μm at V_gs=6 V) and a wider gate operating voltage swing in comparison to the MODFET's. However, due to the larger gate-to-channel distance and the existence of a parasitic surface channel, MOS-MODFET's demonstrated a smaller peak g _m of 90 mS/mm, f_T of 38 GHz, and f_max of 64 GHz. The threshold voltage shifted from 0.45 V for MODFET's to 1.33 V for MOS-MODFET's. A minimum noise figure (NF_min) of 1.29 dB and an associated power gain (G_a) of 12.8 dB were measured at 2 GHz for MODFET's, while the MOS-MODFET's exhibited a NF _min of 0.92 dB and a G_a of 12 dB at 2 GHz. These DC, RF, and high frequency noise characteristics make SiGe/Si MODFET's and MOS-MODFET's excellent candidates for wireless communications     

Accurate small-signal modeling of HFET's for millimeter-waveapplications

In this paper we discuss the small-signal modeling of HFET's at millimeter-wave frequencies. A new and iterative method is used to extract the parasitic components. This method allows calculation of a π-network to model the heterojunction field-effect transistor (HFET) pads, thus extending the validity of the model to higher frequencies. Formulas are derived to translate this π-network into a transmission line. A new and general cold field-effect transistor (FET) equivalent circuit, including a Schottky series resistance, is used to extract the parasitic resistances and inductances. Finally, a new and compact set of analytical equations for calculation of the intrinsic parameters is presented. The real part of Y₁₂ is accounted for in these equations and its modeling is discussed. The accounting of Re(Y₁₂ ) improves the S-parameter modeling. Model parameters are extracted for an InAlAs/InGaAs/InP HFET from measured S-parameters up to 50 GHz, and the validity of the model is evaluated by comparison with measured data at 75-110 GHz     

High-power 10-GHz operation of AlGaN HFET's on insulating SiC

We report the first high-power RF characterization of AlGaN HFET's fabricated on electrically insulating SiC substrates. A record total power of 2.3 W at 10 GHz was measured from a 1280-μm wide HFET at V _ds=33 V. An excellent RF power density of 2.8 W/mm was measured on a 320-μm wide HFET. These values are a result of the high thermal conductivity of SiC, relative to the typical substrate, sapphire     

Investigation Into the Scalability of Selectively Implanted Buried Subcollector (SIBS) for Submicrometer InP DHBTs

Recent attempts to achieve 400 GHz or higher f_T and f _MAX with InP heterojunction bipolar transistors (HBTs) have resulted in aggressive scaling into the deep submicrometer regime. In order to alleviate some of the traditional mesa scaling rules, several groups have explored selectively implanted buried subcollectors (SIBS) as a means to decouple the intrinsic and extrinsic collector design. This allows tau_C to be minimized without incurring a large total C_BC increase, and hence, a net improvement in f_T and f_MAX is achieved. This paper represents the first investigation into the series resistance and capacitance characteristics of submicrometer-width SIBS regions (as narrow as 350 nm) for InP double HBTs. Although the SIBS resistance is higher than that of epitaxially grown layers, the SIBS concept is able to provide good dopant activation and a significant decrease in C_BC. S-parameter measurements are presented to clarify the impact of SIBS geometry variations, caused by both intentional device design and process variations, on f_T and f_MAX. Parasitic resistances and high background doping limit the f_T improvement, but the C_BC reduction is sufficient to demonstrate a 30% increase in f_MAX. Results indicate that further improvements in f_T and f_MAX using the SIBS concept will be possible