Generating a family of testable designs using the BILBO methodology

There are usually many different ways to make a digital circuit testable using the BILBO methodology. Each solution can have different values of test time and area overhead. A design system based on the BILBO methodology has been developed that can efficiently explore the testable design space to generate a family of designs ranging from the minimal test time design to the minimal area overhead design. A designer can select an appropriate design based on trade-offs between test time and area overhead. The branch and bound technique is employed during the exploring process to prune the design space. This significantly reduces the execution time of this process. To effectively bound the exploring process, a very efficient test scheduler has been developed. Unlike previous approaches, this new test scheduler can process a partially testable design as well as a complete testable design. A test schedule for a design is constructed incrementally. The test scheduling procedures are presented along with experimental results that show that this test scheduler usually outperforms existing schedulers. In many cases, it generates an optimal test schedule. Experiments have been performed on several circuits generated by MABAL, a CAD synthesis tool, to demonstrate the performance and practicality of this system.This work was supported by the Defense Advanced Research Projects Agency and monitored by the Federal Bureau of Investigation under Contract No. JFBI90092. The views and conclusions considered in this document are those of the authors and should not be interpreted as necessarily representing the official policies, either expressed or implied, of the Defense Advanced Research Projects Agency or the U.S. Government.     

Ring-like testing of digital circuits

Here we propose a new approach to the testing of digital devices, which can potentially save diagnostic hardware. An example is given for testing combinational devices. Estimates are given for reliability and hardware complexity, and an algorithm for designing operability tests is described.     

Transparent random access memory testing for pattern sensitive faults

This paper presents a new methodology for RAM testing based on the PS(n, k) fault model (the k out of n pattern sensitive fault model). According to this model the contents of any memory cell which belongs to an n-bit memory block, or the ability to change the contents, is influenced by the contents of any k -1 cells from this block. The proposed methodology is a transparent BIST technique, which can be efficiently combined with on-line error detection. This approach preserves the initial contents of the memory after the test and provides for a high fault coverage for traditional fault and error models, as well as for pattern sensitive faults. This paper includes the investigation of testing approaches based on transparent pseudoexhaustive testing and its approximations by deterministic and pseudorandom circular tests. The proposed methodology can be used for periodic and manufacturing testing and require lower hardware and time overheads than the standard approaches.This work was supported by the NSF under Grant MIP9208487 and NATO under Grant 910411.     

数字集成电路故障测试策略和技术的研究进展

IC制造工艺的发展，持续增加着VLSI电路的集成密度，亦日益加大了电路故障测试的复杂性和困难度。作者在承担相应研究课题的基础上，综述了常规通用测试方法和技术，并分析了其局限性。详细叙述了边界扫描测试(BST)标准、可测性设计(DFT)思想和内建自测试(BIST)策略。针对片上系统(SoC)和深亚微米(VDSM)技术给故障测试带来的新挑战，本文进行了初步的论述和探讨。     

Testable design of large random access memories

In this paper we propose a method for testable design of large Random Access Memories. The design technique relies on modification of address decoders to achieve multi-writes and multi-reads during test mode. Almost no modification is required in the design of memory array.A number of different designs for decoders are proposed. In all the designs the objective has been to keep the extra hardware for enhancing testability to as small as possible while causing a minimal or no degradation at all in the speed performance of RAM. Use of extra control and observation points is allowed as long as such points cause only a very small increase in the number of extra pins.We also propose the design of decorders in which only a limited number of cells of RAM are written to or read from during test mode.     

Integration of partial scan and built-in self-test

Partial-Scan based Built-In Self-Test (PSBIST) is a versatile Design for Testability (DFT) scheme, which employs pseudo-random BIST at all levels of test to achieve fault coverages greater than 98% on average, and supports deterministic partial scan at the IC level to achieve nearly 100% fault coverage. PSBIST builds its BIST capability on top a partial scan structure by adding a test pattern generator, an output data compactor, and a PSBIST controller in a way similar to that of deriving a full scan BIST from a full scan structure. However, to make the scheme effective, there is a minimum requirement regarding which flip-flops in the circuit should be replaced by scan flip-flops and/or initialization flip-flops. In addition, test arents are usually added to boost the fault coverage to the range of 95 to 100 percent. These test points are selected based on a novel probabilistic testability measure, which can be computed extremely fast for a special class of circuits. This ciass of circuits is precisely the type of circuits that we obtain after replacing some of the flip-flops.withscan and/or initilization flip-flops. The testability measure is also used for a very useful quick estimation of the fault coverage right after the selection of sean flip-flops, even before the circuit is modified to incorporate PSBIST capability. While PSBIST provides all the benefits of BIST, it incurs lower area overhead and performance degradation than full scan. The area overhead is further reduced when the boundary scan cells are reconfigured for BIST usage.     

Balance testing and balance-testable design of logic circuits

We propose a low-cost method for testing logic circuits, termed balance testing, which is particularly suited to built-in self testing. Conceptually related to ones counting and syndrome testing, it detects faults by checking the difference between the number of ones and the number of zeros in the test response sequence. A key advantage of balance testing is that the testability of various fault types can be easily analyzed. We present a novel analysis technique which leads to necessary and sufficient conditions for the balance testability of the standard single stuck-line (SSL) faults. This analysis can be easily extended to multiple stuck-line and bridging faults. Balance testing also forms the basis for design for balance testability (DFBT), a systematic DFT technique that achieves full coverage of SSL faults. It places the unit under test in a low-cost framework circuit that guarantees complete balance testability. Unlike most existing DFT techniques, DFBT requires only one additional control input and no redesign of the underlying circuit is necessary. We present experimental results on applying balance testing to the ISCAS 85 benchmark circuits, which show that very high fault coverage is obtained for large circuits even with reduced deterministic test sets. This coverage can always be made 100% either by adding tests or applying DFBT.This research was supported by the National Science Foundation under Grant No. MIP-9200526. Parts of this paper were published in preliminary form in Proc. 23rd Symp. Fault-Tolerant Computing, Toulouse, June 1993, and in Proc. 31st Design Automation Conf, San Diego, June 1994.     

An efficient design of embedded memories and their testability analysis using Markov chains

This article presents a design strategy for efficient and comprehensive random testing of embedded random-access memory (RAM) where neither are the address, read/write and data input lines directly controllable nor are the data output lines externally observable. Unlike the conventional approaches, which frequently employ on-chip circuits such as linear feedback shift register (LFSR), data registers and multibit comparator for verifying the response of the memory-under-test (MUT) with the reference signature of a fault-free gold unit, the proposed technique uses an efficient testable design, which helps accelerate test algorithms by a factor of 0.5n, if the RAM is organized into an n×1 array and improve the test reliability by eliminating the LFSR that is known to have aliasing problems. Another serious problem in embedded memory testing by random test patterns is the problem of memory initialization, which has been tackled here by adding word-line flag registers. The paper has made indepth empirical studies of the functional faults such as stuck-at, coupling, and pattern-sensitive by suitably representing these faults by Markov chains and by simulating these chains to derive various test lengths required for detecting these faults. The simulation results conclusively show that, in order to test a IM-bit RAM for detecting the common functional faults, the proposed technique needs only one second as opposed to about an hour needed by the conventional random testing where memory cells are tested sequentially.An abridged version of this article was published in the IEEE International Conference on Wafer-Scale Integration, January 1989. This research was partially supported by the NSF under grant number MIP-9013092 and by ONR under grant number 85-K-0716.     

A class of two-dimensional cellular automata and their applications in random pattern testing

A basic framework to characterize the behavior of two-dimensional (2-D) cellular automata (CA) has been proposed. The performance of the regular structure of the 2-D CA has been evaluated for pseudo-random pattern generation. The potential increase in the local neighborhood structure for 2-D CA has led to better randomness of the generated patterns as compared to LFSR and 1-D CA. The quality of the random patterns generated with 2-D CA based built-in-self-test (BIST) structure has been evaluated by comparing the fault coverage on several benchmark circuits. Also a method of synthesizing 2-D CAs to generate patterns of specified length has been reported. The patterns generated can serve as a very good source of random two-dimensional sequences and also variable length parallel pattern generation having virtually nil correlation among the bit patterns.     

Built-In Self-Test of Field Programmable Analog Arrays based on Transient Response Analysis

In this work a strategy for testing analog networks, known as Transient Response Analysis Method, is applied to test the Configurable Analog Blocks (CABs) of Field Programmable Analog Arrays (FPAAs). In this method the Circuit Under Test (CUT) is programmed to implement first and second order blocks and the transient response of these blocks to known input stimuli is analyzed. Taking advantage of the inherent programmability of the FPAAs, a BIST-based scheme is used in order to obtain an error signal representing the difference between fault-free and faulty CABs. Two FPAAs from different manufacturers and distinct architectures are considered as CUT. For one of the devices there is no detailed information about its structural implementation. For this reason, a functional fault model based on high-level parameters of the transfer function of the programmed blocks is adopted, and then, the relationship between these parameters and CAB component deviations is investigated. The other considered device allows a structural programming in which the designer can directly modify the values of programmable components. This way, faults can be injected by modifying the values of these components in order to emulate a defective behavior. Therefore, it is possible to estimate the fault coverage and test application time of the proposed functional test method when applied to both considered devices.

基于自相似业务流的Hurst加权随机早检测算法

Floyd提出的随机早丢弃（RED，random carly detection）是基于传统的泊松（Possion）模型，不适应网络流量普遍呈现自相似性的特点。基于此目的，提出了一种新的RED算法——Hurst加权随机早检测算法（HWRED，Hurst weighted random early detection）。新算法能够根据输入流量的自相似系数Hurst，调整RED算法参数。仿真结果表明，新算法提高了队列长度的稳定性，减少了丢包率、排队时延和排队抖动，提高了网络的链路利用率。     

组合电路内建自测试技术的研究

随着集成电路技术的发展,可测性设计在电路设计中占有越来越重要的地位,内建自测试作为可测性设计的一种重要方法也越来越受到关注。文中首先介绍了内建自测试的实现原理,在此基础上以八位行波进位加法器为例,详细介绍了组合电路内建自测试的设计过程。采用自顶向下的设计方法对整个内建自测试电路进行模块划分,用VHDL语言对各个模块进行代码编写并在QuartusII软件环境下通过了综合仿真,结果表明此设计合理,对电路的测试快速有效。     

基于Java和DAO设计模式的网上购物系统的实现

随着网络技术和面向对象技术的发展,面向对象的多层开发已经成为主流。在这里数据库仅仅作为对象持久化的一种工具来使用。本文通过一个具体的网上购物系统详细介绍了DAO设计模式的组成以及如何利用OJB来实现DAO设计模式。     

无纸化考试选择题随机组卷的算法设计

在计算机网环境下进行无纸化考试时,由于机房空间的限制,邻座考生之间的相互抄袭难以控制,导致考试结果的信度降低。为了有效地确保考试的客观性、公正性,提高考试信度,针对单选题的组卷问题,从试题的随机抽取、试题排列顺序的随机改变、选项位置随机排列等方面,运用软件技术,重新构建考生的试卷,给出组卷策略的算法设计。实践表明,该软件技术措施的综合应用,在较大程度上提高了考试结果的信度。     

基于加权随机森林算法的空巢电力用户识别方法

针对当前政府和社会对空巢老人的识别缺乏有效技术手段的问题,提出了一种基于加权随机森林算法的空巢电力用户识别方法。首先通过调查问卷获取部分准确空巢用户标签,并从用电水平、用电波动、用电趋势 3 个方面构建用户用电特征库,由于空巢与非空巢存在用户数据不平衡问题,采用加权随机森林算法改善机器学习对数据敏感的现象,将该算法模型在电力公司采集系统部署上线,并对2 000户未知类型用户进行空巢识别,其空巢识别准确率达到 74.2%。结果表明,从用电角度研究对空巢老人的识别,可以帮助电网公司了解空巢老人的个性化、差异化需求,从而为用户提供更精细的服务,也可以协助政府和社会开展帮扶工作。     

On-chip testing of random access memories

This article gives an overview of the Built-In Self-Test techniques for stand alone Random-Access Memory chips. It identifies the limitations of the existing fault models and the test algorithms used to test large RAMs. Methods to reduce test time for testing large RAMs are categorized. The article argues that even linear time test algorithms must use architecture and design for testability induced parallelisms to keep the total test time to an acceptable limit. Following that two algorithms are presented that can be used to test large RAMs for neighborhood pattern sensitive faults. Test lengths and test time for application of these algorithms are computed and it is suggested that a microprogrammed controller based scheme be used to implement self-test in stand alone RAMs.Part of this work was completed when the author was a Visting Professor at the University of Roorkee, India.     

一种成像雷达的通信一体化信号设计与分析

雷达与通信系统一体化可以最大限度地利用雷达设备, 使雷达的优良性能为通信服务.根据信号共享的原则, 在保持成像雷达和通信各自功能实现的前提下, 设计了一种基于随机频率步进调制的成像雷达通信一体化信号.该信号的设计方法是对发送的通信数据进行随机编码处理, 然后将其调制到雷达载波的频点上发送出去, 实现通信功能; 而引入压缩感知理论后, 采用这种信号仍能获得高分辨率的雷达图像, 在一定功能上实现了成像雷达和通信的一体化.     

基于电力线信道噪声的真随机数发生器的设计

提出了一种基于电力线信道噪声的真随机数发生器的设计,即通过对电力线信道上的噪声采样的方法来产生随机数。使用EAX加密算法作为后处理算法,消除由于外部干扰产生的偏差和自相关性。通过理论分析和实验验证,可以弥补现有常用真随机数生产法的不足,获得分布均匀、相对独立的随机数。     

Analytical method of pattern analysis for cluster-fed reflectors with random feed displacements

An innovative analytical method for the evaluation of the directivity patterns of cluster-fed reflector antennas with random feed element position and orientation displacements is presented. In this approach, the sensitivities of the incident magnetic field, far electrical field and directivity are derived with respect to the feed element position and orientation displacements. The effect of random position and orientation displacements on the directivity pattern is investigated via the numerical characteristics of the directivity with pre-calculated sensitivities; meanwhile, the upper and lower bounds of the directivity pattern are illustrated. A seven-element cluster-fed offset reflector is utilised as a numerical example to show the application of this method with different feed element position and orientation displacements. Comparison with the Monte Carlo method demonstrates the effectiveness and applicability of the proposed method.     

A structure and technique for pseudorandom-based testing of sequential circuits

Presented is a register structure and generator design which enables non-scan sequential testing using parallel pseudorandom-based patterns applied to the circuit's primary inputs. The proposed register structure and register control strategy uses the circuit under test's (CUT's) natural sequential activity to periodically alter a register's output bias to a value near 0.5 (i.e. alter the spread of 1's in the output stream). Thus, over time, it is possible to introduce a larger spread circuit states than that normally reachable when parallel pseudorandom-based test patterns are applied to the input lines of a CUT. Using the register modification, a simple hardware generation system can be designed and is suitable for both on-chip and external testing. Experiments indicate that high fault coverage is attainable in a relatively short test time.