30 GHz transformer-coupled and reused injection-locked VCO/divider in 0.13 μm CMOS process

A 30 GHz VCO, using a transformer as the tank load and inter-stage coupling of the divider, is proposed such that the inductive load of the buffer between the VCO and the divider is eliminated and therefore chip area and power consumption can be reduced. The transformer is further reused by feedback to enhance the output swing of the VCO. Phase noise performance of the VCO can also be improved by the injection-lock mechanism from the reverse coupling of the divider. Measured results show that output phase noises of the VCO with (without) the divider are -125.1 (-118.6) dBc/Hz at 10 MHz offset frequencies from around 29.2 GHz carrier frequency. The power consumption of the VCO alone is 2.32 mW, while that of the VCO/divider increases only to 4.65 mW.     

Low-power and low NF V-band down-converter in 0.13 μm CMOS

A V-band down-converter integrating a LNA and mixer in 0.13 mm CMOS technology is presented. The LNA has a current re-use topology for low power consumption. The transistor size of the LNA is optimised by the substrate noise for the low noise figure (NF) and f_max for high gain performance. The new resistive mixer for low LO power operation is proposed. The NF of the down-converter is 4.7 dB. The conversion gain and input P_1dB are 0.67 dB and 212.5 dBm, respectively. The proposed circuit, consuming only 11.6 mW, shows the lowest NF and highest linearity among V-band down-converters.     

Power efficient Ka-band low phase noise VCO in 0.13 μm CMOS

A 27 GHz cross-coupled LC voltage controlled oscillator (VCO) using a standard 0.13 mum CMOS technology is presented. The VCO using a high-Q LC resonator with a micro-strip inductor (mu-strip L) provides a phase noise of -113 dBc/Hz at a 1 MHz offset frequency. The figure - of-merit (FoM) is -194.6 dBc/Hz. To obtain high output power, it also uses a common source amplifier as a buffer and it shows the output power of -3.5 dBm at an oscillation frequency of 26.89 GHz. This is believed to be the lowest phase noise and FoM with the highest output power of a millimetre-wave VCO in CMOS technology.     

A 40 GHz single-ended down-conversion mixer in 0.13 /spl mu/m SiGeC BiCMOS HBT

This work presents a single-ended active mixer realized with a 0.13 /spl mu/m BiCMOS SiGeC heterojunction bipolar transistor (HBT) technology. This mixer is designed to be integrated in a superheterodyne receiver for 40 GHz wireless communication systems. Local oscillator (LO) and RF signals are directly applied to the base of the HBT through two coupled lines. The mixer provides a down-conversion from 42 GHz to 2 GHz. The mixer exhibits a power conversion gain better than 2.4 dB and a measured double-sideband noise figure less than 8.3 dB for P/sub LO/=3 dBm (power of the local oscillator) under a global power consumption lower than 9.5 mW. This architecture exhibits good linearity performance with a measured IP/sub 1dB/ of about -7 dBm and an IIP3 of +4 dBm. The linear dynamic range for a 2 GHz system bandwidth is approximately 65 dB for P/sub LO/=+2 dBm and T/sub 0/=290 K. The third order spurious free dynamic range is calculated to be better than 52 dB.     

A 71–80 GHz Amplifier Using 0.13- μm CMOS Technology

A 71-80 GHz amplifier using 0.13-mum standard mixed signal/radio frequency complementary metal-oxide-semiconductor (CMOS) technology is presented in this letter. This four-stage cascade thin-film microstrip amplifier achieves the peak gain of 7.0 dB at 75 GHz. The 3-dB frequency bandwidth range is from 71 to 80 GHz. The amplifier demonstrates the highest amplification frequency and smallest chip size among previous published millimeter-wave (MMW) 0.13-mum CMOS amplifiers.     

Fully integrated 60-GHz single-ended resistive mixer in 90-nm CMOS technology

This letter presents the design and characterization of a fully integrated 60-GHz single-ended resistive mixer in a 90-nm CMOS technology. A conversion loss of 11.6dB, 1-dB compression point of 6dBm and IIP3 of 16.5dBm were measured with a local oscillator (LO) power of 4dBm and zero drain bias. The possibility of improvement in IIP3 with selective drain bias has been verified. A 3-dB improvement in IIP3 was obtained with 150-mV dc voltage applied at the drain. Microstrip transmission lines are used to realize matching and filtering at LO and radio frequency ports.     

26-34 GHz CMOS mixer

A 26-34 GHz fully integrated CMOS down mixer is presented. At 30 GHz RF frequency and 2.5 GHz IF frequency, 50 /spl Omega/ terminations, 5 dBm LO and 1.2 V/spl times/17 mA supply power, the circuit yields a conversion loss of 2.6 dB, an SSB NF of 13.5 dB and an IIP3 of 0.5 dBm.     

Design of UWB switched gain controlled LNA using 0.18 μm CMOS

A switched gain controlled low noise amplifier (LNA) for the 3.1- 4.8 GHz ultra-wideband system is presented. The LNA is fabricated with the 0.18 mum 1P6M standard CMOS process. Measurement of the LNA was performed using an RF probe station. In gain mode, measured results show a noise figure of 4.68-4.97 dB, gain of 12.5-13.9 dB, and input/output return loss higher than 10/8.2 dB. The input IP3 (IIP3) at 4.1 GHz is 1 dBm, and consumes 14.6 mW of power. In bypass mode, measured results show a gain of-7.0 to -8.7 dB, and input/output return loss higher than 10/6.3 dB. The input IP3 at 4.1 GHz is 9.2 dBm, and consumes 1 muW of power.     

Inductorless AGC amplifier for 10GBase-LX4 ethernet in 0.18 μm CMOS

A new differential automatic gain control post-amplifier for 10GBase-LX4 Ethernet realised in a 0.18 mum CMOS process is presented. Based on a very compact inductorless design, it comprises three cascaded digitally programmable gain stages followed by a bandwidth-enhancement buffer. Results show an overall -3 dB cutoff frequency above 3 GHz over a - 3 to 33 dB linear-in-dB controllable gain range in 6 dB steps with 55 mW power consumption from a 1.8 V single supply.     

Full range voltage-controlled ring oscillator in 0.18μm CMOS for low-voltage operation

A new differential delay cell with a complementary current control to increase the control voltage range as well as the operation frequency is proposed for low-voltage operation. The new differential delay cell is employed in a four-stage voltage-controlled ring oscillator (VCRO). The VCRO is implemented using 0.18 m 1P6M CMOS process and 1.8 V supply voltage. Measured results show that a wide operation frequency range from 5.36 to 3.03 GHz is achieved for the full range control voltage from 0 to 1.8 V. Measured phase noise is 107 dBc/Hz at 1 MHz offset from the 5.22 GHz centre frequency.     

A 2.5 GHz All-Digital Delay-Locked Loop in 0.13 μm CMOS Technology

A 2.5 GHz, 30 mW, 0.03 mm², all-digital delay-locked loop (ADDLL) in 0.13 mum CMOS technology is presented. The tri-state digital phase detector suppresses the dithering phenomenon and reduces the output peak-to-peak jitter for a counter-controlled digital DLL. The lattice delay unit has both a small delay step and a fixed intrinsic delay of two nand gates. A modified successive approximation register-controller reduces the locking time and allows the DLL to track the process, voltage, temperature, and load variations. This ADDLL locks in 24 cycles and has a closed-loop characteristic. The measured peak-to-peak jitter is 14 ps at 2.5 GHz.     

0.18 μm 3.1-10.6 GHz CMOS UWB LNA with 11.4±0.4 dB gain and 100.7± 17.4 ps group-delay

A3.1-10.6 GHz ultra-wideband low-noise amplifier (UWB LNA) with excellent phase linearity property (group-delay-variation is only plusmn17.4 ps across the whole band) using standard 0.18 mum CMOS technology is reported. To achieve high and flat gain and small group-delay-variation at the same time, the inductive peaking technique is adopted in the output stage for bandwidth enhancement. The UWB LNA dissipates 22.7 mW power and achieves input return loss (S₁₁) of -9.7 to -19.9 dB, output return loss (S22) of-8.4 to -22.5 dB, flat forward gain (S21) 11.4 plusmn0.4 dB, reverse isolation (S12) of -40 to -48 dB, and noise figure of 4.12-5.16 dB over the 3.1-10.6 GHz band of interest. A good 1 dB compression point (Pi dB) of -7.86 dBm and an input third-order intermodulation point (IIP3) of 0.72 dBm are achieved at 6.4 GHz. The chip area is only 681 x 657 mum excluding the test pads.     

70-90 GHz balanced resistive PHFET mixer MMIC

A balanced resistive GaAs high electron mobility transistor mixer monolithic microwave integrated circuit has been designed and fabricated in a production oriented technology. The design is based on a specialised large signal model for linear transistor operation. The conversion loss was 8-10 dB for 70-90 GHz and the noise figure at 100 kHz was 31 dB, which is 11 dB lower than that obtained with diode mixers     

A 9-50-GHz Gilbert-cell down-conversion mixer in 0.13-/spl mu/m CMOS technology

A broadband microwave/millimeter-wave (MMW) Gilbert-cellmixer using standard 1P8M 0.13-/spl mu/m complementary metal oxide semiconductor (CMOS) technology is presented in this letter. Two radio frequency (RF) transformer baluns are used in RF-and local oscillator (LO)-ports to convert single-ended signals to differential signals. Thin film microstrip line is employed for the matching networks and transformer design. This mixer has a conversion gain of better than 5dB from 9 to 50GHz. Between 5 and 50GHz,the RF- and LO-to-intermediate frequency (IF) isolations are better than 40dB. The RF-to-LO and LO-to-RF isolations are all better than 20dB. To the authors' knowledge, this is the first CMOS Gilbert-cell mixer operating to MMW frequency to date.     

Relative intensity noise measurements of 5 μm quantum cascade laser and 1.55 μm semiconductor laser

The magnitude of the relative intensity noise (RIN) of a 5 mum distributed-feedback quantum cascade laser (DFB-QCL) was compared with a conventional 1.55 mum DFB laser diode (LD). The RIN for the DFB-QCL at a frequency of 1 MHz was 157 dBm at 10 mW light output, about 5 dB higher than that of the DFB-LD, which could almost be fully explained by the semi-classical noise model. The resonant tunnelling induced noise, which might be a cause of the RIN degradation, was not observed.     

192 GHz push-push VCO in 0.13 /spl mu/m CMOS

A 192 GHz cross-coupled push-push voltage controlled oscillator (VCO) is fabricated using the UMC 0.13 /spl mu/m CMOS logic process. The VCO can be tuned from 191.4 to 192.7 GHz. The VCO provides output power of /spl sim/-20 dBm and phase noise of /spl sim/-100 dBc/Hz at 10 MHz offset, while consuming 11 mA from a 1.5 V supply.     

0.18 μm 21-27 GHz CMOS UWB LNA with 9.3 ± 1.3 dB gain and 103.9 ± 8.1 ps group delay

A 21-27 GHz CMOS ultra-wideband low-noise amplifier (UWB LNA) with state-of-the-art phase linearity property (group delay variation is only ± 8.1 ps across the whole band) is reported for the first time. To achieve high and flat gain (S₂₁) and small group delay variation at the same time, the inductive series peaking technique was adopted in the output of each stage for bandwidth enhancement. The LNA dissipated 27 mW power and achieved input return loss (S₁₁) of 213 to 220.1 dB, output return loss (S₂₂) of 28.2 to 230.2 dB, flat S21 of 9.3 ± 1.3 dB, reverse isolation (S₁₂) of 252.7 to 273.3 dB, and noise figure of 4.9?6.1 dB over the 21-27 GHz band of interest. The measured 1 dB compression point (P_1dB) and input third-order intermodulation point (IIP3) were 214 and 24 dBm, respectively, at 24 GHz.     

A K-band down-conversion mixer with 1.4-GHz bandwidth in 0.13-/spl mu/m CMOS technology

A low power and low voltage down conversion mixer working at K-band is designed and fabricated in a 0.13/spl mu/m CMOS logic process. The mixer down converts RF signals from 19GHz to 2.7GHz intermediate frequency. The mixer achieves a conversion gain of 1dB, a very low single side band noise figure of 9dB and third order intermodulation point of -2dBm, while consuming 6.9mW power from a 1.2V supply. The 3-dB conversion gain bandwidth is 1.4GHz, which is almost 50% of the IF. This mixer with small frequency re-tuning can be used for ultra-wide band radars operating in the 22-29GHz band.     

Miniature Four-Way and Two-Way 24 GHz Wilkinson Power Dividers in 0.13 μm CMOS

This letter presents 24 GHz four-way and two-way miniature Wilkinson power dividers (PDs) in a standard CMOS technology. The chip area is significantly reduced using a lumped-element design, and the effective areas of four-way and two-way Wilkinson dividers are 0.33 times 0.33 mm² and 0.12 times 0.29 mm², respectively. The four-way Wilkinson divider results in an insertion loss <2.4 dB, an input/output return loss better 15.5 dB, and a port-to-port isolation >24.7 dB from 22 to 26 GHz. The two-way Wilkinson divider results in an insertion loss <1.4 dB, an input/output return loss better 8.9 dB, and a port-to-port isolation >14.8 dB from 22 to 26 GHz. To the author's knowledge, this is the first demonstration of 24 GHz four-way Wilkinson PD in a standard CMOS technology.     

Mid-infrared GaSb-based EP-VCSELl emitting at 2.63 μm

Electrically-pumped GaSb-based vertical-cavity surface-emitting lasers emitting up to 2.63 μm at room temperature are reported. The whole structure was grown monolithically in one run by solid-source molecular beam epitaxy. This heterostructure is composed of two n-doped AlAsSb/GaSb DBRs, a type-I GaInAsSb/AlGaAsSb multiquantum- well active region and an InAsSb/GaSb tunnel junction. A quasi-CW (1 μs, 5 %) operation was obtained at room temperature for 35 μm-diameter devices with threshold current of 85 mA.