An Ultra-Wideband Distributed Active Mixer MMIC in 0.18-μm CMOS Technology

In this paper, a distributed circuit topology for active mixers suitable for ultra-wideband operations is presented. By employing nonuniform artificial transmission lines with the complementary transconductance stages in the Gilbert-cell multiplier, the proposed mixer demonstrates broadband characteristics at microwave frequencies while maintaining a high conversion gain (CG) with improved gain flatness. Using a 0.18-mum CMOS process, the proposed circuit is implemented, exhibiting a -3-dB bandwidth of 28 GHz. With a local-oscillator power of 3 dBm and an IF frequency of 10 MHz, the fabricated circuit has a CG of 12.5plusmn1 dB and an average input third-order intercept point (IIP₃) of 0 dBm within the entire frequency range. The fully integrated wideband mixer occupies a chip area of 0.87times0.82 mm² and consumes a dc power of 20 mW from a 2-V supply voltage     

An Active IF Balun for a Doubly Balanced Resistive Mixer

In this letter, we present a wideband active intermediate frequency (IF) balun for a doubly balanced resistive mixer implemented using a 0.5 mum GaAs pHEMT process. The 0.3 times 0.5 mm² IF balun was realized through a DC-coupled differential amplifier in order to extend IF frequency of the mixer to DC. The measured amplitude and phase imbalances were less than 1 dB and 5deg, respectively, from DC to 7 GHz. The output third order intercept (OIP3) and P1 dB of the IF balun were 18 dBm and 6 dBm, respectively at 1 GHz. The mixer with the IF balun is 1.7 times 1.8 mm² in size, has a conversion loss of 2 to 8 dB from 8 to 20 GHz RF frequency at a fixed IF of 1 kHz, which proves the mixer operates successfully at an IF frequency close to DC. The measured OIP3 were +10 to +15 dBm over the operating frequency with a DC power consumption of 370 mW.     

A 25–75 GHz Broadband Gilbert-Cell Mixer Using 90-nm CMOS Technology

A compact and broadband 25-75-GHz fully integrated double-balance Gilbert-cell mixer using 90-nm standard mixed-signal/radio frequency (RF) CMOS technology is presented in this letter. A broadband matching network, LC ladder, for Gilbert-cell mixer transconductance stage design is introduced to achieve the flatness of conversion gain and good RF port impedance match over broad bandwidth. This Gilbert-cell mixer exhibits 3plusmn2dB measured conversion gain (to 50-Omega load) from 25 to 75GHz with a compact chip size of 0.30mm². The OP_{1 dB} of the mixer is 1dBm and -4dBm at 40 and 60GHz, respectively. To the best of our knowledge, this monolithic microwave integrated circuit is the highest frequency CMOS Gilbert-cell mixer to date     

Low-Loss and Broadband Asymmetric Broadside-Coupled Balun for Mixer Design in 0.18-$mu{hbox {m}}$ CMOS Technology

This study presents an asymmetric broadside coupled balun with low-loss broadband characteristics for mixer designs. The correlation between balun impedance and a 3D multilayer CMOS structure are discussed and analyzed. Two asymmetric multilayer meander coupled lines are adopted to implement the baluns. Three balanced mixers that comprise three miniature asymmetric broadside coupled Marchand baluns are implemented to demonstrate the applicability to MOS technology. Both a single and dual balun occupy an area of only 0.06 mm². The balun achieves a measured bandwidth of over 120%, an insertion loss of better than 4.1 dB (3 dB for an ideal balun) at the center frequency, an amplitude imbalance of less than 1 dB, and a phase imbalance of less than 5deg from 10 to 60 GHz. The first demonstrated circuit is a Ku-band mixer, which is implemented with a miniaturized balun to reduce the chip area by 80%. This 17-GHz mixer yields a conversion loss of better than 6.8 dB with a chip size of 0.24 mm². The second circuit is a 15-60-GHz broadband single-balanced mixer, which achieves a conversion loss of better than 15 dB and occupies a chip area of 0.24 mm². A three-conductor miniaturized dual balun is then developed for use in the third mixer. This star mixer incorporates two miniature dual baluns to achieve a conversion loss of better than 15 dB from 27 to 54 GHz, and occupies a chip area of 0.34 mm².     

A 90-nm Wideband Merged CMOS LNA and Mixer Exploiting Noise Cancellation

This paper describes the design and implementation of a wideband merged LNA and mixer chip covering the frequency range from 0.1 to 3.85 GHz using 90-nm CMOS technology. Its high level of integration as well as its low power consumption makes it suitable for the rapidly growing software defined radio RF receivers. The chip performance achieves S11 below -10 dB along the entire band and a minimum single side band noise figure of 8.4 dB at IF frequency of 70 MHz. Power conversion gain is measured to be 12.1 dB while the input referred 1 dB compression point is measured to be -12.8 dBm. The chip core consumes only 9.8 mW from a 1.2 V supply with a die area, including the pads, of 0.88 mm²     

A 0.5–7.5 GHz Ultra Low-Voltage Low-Power Mixer Using Bulk-Injection Method by 0.18- μm CMOS Technology

A fully differential low-voltage low-power downconversion mixer using a TSMC 0.18-mum CMOS logic process is presented in this letter. The mixer was designed with a four-terminal MOS transistor, the radio-frequency (RF) and local-oscillator signals apply to the gate and bulk of the device, respectively while the intermediate frequency (IF) signals output was from the drain. The mixer features a maximum conversion gain of 5.7dB at 2.4 GHz, an ultra low dc power consumption of 0.48 mW, a noise figure of 15 dB, and an input IP of 5.7 dBm. Moreover, the chip area of the mixer core is only 0.18 times 0.2 mm². The measured 3-dB RF frequency bandwidth is from 0.5 to 7.5 GHz with an IF of 100 MHz, and it is greatly suitable for low-power in wireless communication.     

A K- to Ka-Band Broadband Doubly Balanced Monolithic Ring Mixer

A broadband doubly balanced monolithic ring mixer with a new intermediate frequency (IF) signal extraction method implemented by 0.15 mum pHEMT process is presented. The hybrid couplers of the proposed mixer consist of multiple coupled lines and fourfold coupled line Marchand baluns. The use of multiple coupled lines leads to a die size less than 1 times 1 mm² and improves the bandwidth of the mixer. The novel fourfold coupled line allows the extraction of the IF signal directly without any extra low pass filter circuits. The mixer exhibited 8-13 dB conversion loss, high radio frequency/local oscillation isolation of 35-50 dB over 16-40 GHz and an input 1-dB compression point of 14 dBm.     

A novel self-oscillating HEMT-HBT cascode VCO-mixer using an activetunable inductor

Here we describe a unique Ka-band self-oscillating HEMT-HBT cascode mixer design which integrates an active tunable resonator circuit. The VCO-mixer MMIC integrates GaAs HEMT's and HBT's using selective molecular beam epitaxy (MBE) technology. The HEMT-HBT cascode active mixer operates similarly to a dual-gate mixer. The HBT of the cascode is used to construct a VCO by presenting the base with an HEMT tunable active inductor. The VCO can be tuned from 28.5 to 29.3 GHz while providing ≈0 dBm of output power. Operated as an upconverter, the MMIC achieves 6-9 dB conversion loss over a 31-39 GHz output frequency band. Using these active approaches, both VCO and mixer functions were integrated into a compact 1.44×0.76 mm² chip area. The active RF integrated circuit (IC) techniques presented here have direct implications to future high complexity millimeter-wave monolithic integrated circuits (MIMICs) for ultrahigh-speed clock recovery and digital radio applications     

Low-noise Ku-band MMIC balanced P-HEMT upconverter

An enhanced design methodology for a low-noise Ku-band monolithic balanced high electron mobility transistor (HEMT) upconverter and its performance are presented in this paper. The mixer topology consists of a common source/common gate HEMT pair that performs the mixing and balun functions. A detailed study has been done to establish the role of the transistor model elements in the performance of the mixer. Based on this study, a new analysis is proposed to optimize the operating point of the mixer in order to get a tradeoff between conversion gain and port isolations. To combine the LO and intermediate-frequency (IF) signals, active circuits were used, as well as a high-pass filter in order to improve the isolations. The circuit size, including the filter and the combiners, is 3 mm². On-wafer measurements show a conversion gain over 2.5 dB, with only 3 dBm of LO power. A LO/RF isolation over 27 dB was measured in the whole LO band. The LO/IF isolation is over 27 dB thanks to the low reverse gain of the combiner HEMT's. A single sideband noise figure of 7.3 dB has been obtained     

A 5.4 mW/0.07 mm$^{2}$ 2.4 GHz Front-End Receiver in 90 nm CMOS for IEEE 802.15.4 WPAN Standard

An integrated 2.4 GHz CMOS receiver front-end according to the IEEE 802.15.4 standard is presented in this paper. It integrates the overall RF part, from the balun up to the first stage of the channel filter, as well as the cells for the LO signal conditioning. The proposed architecture is based on a 6 MHz low-IF topology, which uses an inductorless LNA and a new clocking scheme for driving a passive mixer. When integrated in a 90 nm CMOS technology, the receiver front-end exhibits an area of only 0.07 mm², or 0.23 mm² when including an input integrated balun. The overall chip consumes 4 mA from a single 1.35 V supply voltage and it achieves a 35 dB conversion gain from input power in dBm to output voltage in dBvpk, a 7.5 dB NF value, -10 dBm of IIP3 and more than 32 dB of image rejection.     

A Miniature Q-Band Balanced Sub-Harmonically Pumped Image Rejection Mixer

This work presents a miniature Q-band balanced single side-band sub-harmonically pumped image rejection diode mixer (SHIRM) using a compact Marchand dual balun design. The SHIRM is realized employing four anti-parallel diode pairs for frequency mixing, a Lange coupler for radio frequency (RF) signal input, and a reduced size three-conductor-line Marchand dual balun for local oscillator pumping. The length of three-conductor-line dual balun is reduced by 81% after shunting two lumped capacitors at the center conductor. The measured results exhibit a minimum conversion loss of 8.6 dB, a maximum image rejection ratio of 22 dB, all ports isolation better than 37 dB, and an input 1-dB compression point of 2.5 dBm at RF bandwidth of 40.5 to 43.5 GHz and fixed intermediate frequency of 2.4 GHz. The chip area is very compact, only 1 times 0.84mm²     

An Ultra-Broadband Doubly Balanced Monolithic Ring Mixer for Ku- to Ka-band Applications

A novel 12-40 GHz ultra-broadband doubly balanced monolithic ring mixer with a small chip size covering the Ku- to Ka-band applications implemented by a 0.15-mum pseudo- morphic high electron-mobility transistor process is presented. The proposed mixer consists of two spiral transformer baluns and a band-reject filter. The use of the spiral baluns leads to the achievement of a chip size less than 0.8 times 0.8 mm². The radio frequency (RF) spiral balun with a band-reject filter served by an L-C resonator is used to improve the bandwidth of the mixer and to provide an output port for the intermediate frequency (IF) extraction as well. The mixer exhibits a 6-12 dB conversion loss, high isolation over 12-40 GHz RF/local oscillation bandwidth, a DC-8 GHz IF bandwidth, and a 1-dB compression power of 14 dBm for both down- and up-converter applications.     

An Ultra-Wideband High-Linearity CMOS Mixer With New Wideband Active Baluns

A 2-11-GHz high linearity CMOS down-conversion mixer with wideband active baluns using 0.18-mum CMOS technology is demonstrated in this paper. The mixer employs a folded cascode Gilbert cell topology and on-chip broadband active baluns. The folded cascode approach is adopted to increase the output swing, and the linearity is enhanced by a harmonic distortion canceling technique derived from the harmonic balance analysis. The proposed configuration shows the highest IIP₃ and IP_{1 dB}, and exhibits more compact size than most published studies. A broadband active balun is used to generate wideband differential signals, together with the derivation of a closed-form expression for the phase imbalance. This single-ended wideband mixer has the conversion gain of 6.9plusmn1.5 dB, input 1-dB compression point (IP_{1 dB}) of - 3.5 dBm, single-sideband noise figure of 15.5 dB, and third-order input intercept point (IIP₃) of 6.5 dBm under the power consumption of 25.7 mW from a 1.8-V power supply. The chip area is 0.85 x 0.57 mm².     

A 900-MHz RF front-end with integrated discrete-time filtering

Discrete-time analog filters, rather than off-chip components, have been used to perform frequency selection and down conversion in the integrated front-end for a 900-MHz RF receiver. The first stage of frequency down conversion is implemented with a subsampling switched-capacitor sample-and-hold circuit clocked at 78 MHz. Subsequent stages of discrete-time filtering are realized using switched-capacitor biquadratic filters. An experimental prototype of the front-end had been integrated in a 0.6-μm BiCMOS technology. The circuit provides a system gain of 36 dB and 32 dB suppression of interfering channels over a 40 MHz bandwidth. Referred to the system input, the third-order intercept-point is -16 dBm, and the spot input-referred noise is -82 dBm over a 30 kHz bandwidth. The experimental circuit dissipates 90 mW from a 3.3-V supply and occupies an active area of 1.9×1.9 mm²      

A Low-Noise WLAN Mixer Using Switched Biasing Technique

A low-noise CMOS down-conversion mixer for WLAN applications is presented in this letter. The proposed mixer is based on the conventional Gilbert-type topology with switched biasing technique for a current source instead of static biasing, which lowers noise over a wide range of frequencies. Moreover, a dc level shifter is used for the symmetric switching operation in tail current transistors. A current bleeding technique is adopted to reduce the noise caused by the LO switching operation. The proposed mixer was fabricated using a 0.18 mum 1P6M CMOS process. Measurement results include a conversion gain of 7.5 dB, an IIP3 of -5 dBm, and noise figures of 10.9 dB at 1 MHz and 7.6 dB at 100 MHz. The mixer core consumes a current of 4.5 mA from a supply voltage of 1.8 V. The chip size, including pads for measurements, is 0.88 times 0.88 mm².     

A 23–37 GHz Miniature MMIC Subharmonic Mixer

A novel configuration of subharmonic mixer using an anti-parallel diode pair is presented for operating over the 23-37 GHz band. The monolithic microwave integrated circuit is implemented by GaAs 0.15 mum PHEMT technology with the compact size of 0.85 times 0.85 mm². This mixer employs a directional coupler, LC low-pass filter, and a short stub for isolating three ports corresponding to radio frequency (RF), local oscillation (LO) input, and intermediate frequency (IF) output ports. The directional coupler also provides impedance transformation between the diode pair, RF, and LO ports. This makes the subharmonic mixer more compact and flexible. The best conversion loss of the subharmonic mixer is 9.4 dB, and the LO-to-RF and LO-to-IF isolations are better than 22 and 31 dB, respectively.     

A Variable Conversion Gain Star Mixer for Ka-Band Applications

A variable conversion gain star mixer for Ka-band applications has been presented. This monolithic microwave integrated circuit was implemented on AlGaAs/InGaAs/GaAs pseudomorphic high-electron-mobility transistor process with a chip size of 1.7times1.7 mm². The mixer is modified from conventional star mixer to apply dc bias. The conversion gain of the mixer, controlled by the voltage of the diodes, could be applied to meet gain compensation requirements in communication systems. From the measured results, the circuit can provide 11.9 dB conversion gain and 9.3 dB gain adjustment by controlling voltage from 0 to 0.7 V at 30 GHz.     

A DC-11.5 GHz Low-Power, Wideband Amplifier Using Splitting-Load Inductive Peaking Technique

A DC-11.5 GHz low-power amplifier is developed in commercial 0.13 mum, CMOS technology. This amplifier design is based on a three-stage shunt-feedback inverter-configuration with splitting load inductive peaking technique. The peaking inductor is placed at the gate of the nMOS to compensate gain roll-off of the inverter stage and extend its operating bandwidth. This amplifier achieves a gain flatness of 13.21 dB from dc to 11.5 GHz with I/O return losses better than 17 dB at a power consumption of 9.1 mW. The measured noise figure is less than 5.6 dB between 1-11 GHz. The output P1 dB is 8 dBm and input third-order intercept point is 10 dBm. The total chip size is 0.34 mm² including all testing pads, with a core area of only 0.08 mm².     

A 10–35 GHz Low Power Bulk-DrivenMixer Using 0.13 $mu$m CMOS Process

10-35 GHz doubly balanced mixer using a 0.13-mum CMOS foundry process is presented in this letter. Using the bulk-driven topology, the number of transistors of the doubly balanced mixer is reduced; thus the mixer can achieve a low supply voltage and low power consumption. This bulk-driven mixer exhibits a measured conversion gain of -1 plusmn 2 dB from 10 to 35 GHz of radio frequency (RF) with a fixed intermediate frequency (IF) of 100 MHz. The measured local oscillation (LO) to IF and RF-IF isolations are better than 30 dB. The chip area of the mixer is 0.6 times 0.4 mm². The total power consumption included output buffer is only 6 mW.     

A 20 mW 3.24 mm2 Fully Integrated GPS Radio for Location Based Services

The challenges in the co-existence of a GPS receiver with cellular phones for location based services are addressed in this paper. A fully integrated GPS radio, realized in a 0.18 mum SiGe technology, demonstrates a 1 dB gain desensitization at 1.9 GHz of -8 dBm, a noise figure of 5 dB, with 20 mW power consumption. Chip area is 3.24 mm² . The receiver includes a highly selective LNA, key to minimize desensitization and reciprocal mixing due to the large cellphone leakage, a novel quadrature VCO topology capable of directly driving quadrature passive mixer with high swing and low power consumption, complex bandpass filter, variable gain amplifier, automatic gain control, 2-bit quantizer, and a fractional-N sigma-delta-based PLL that can lock to any crystal frequency