Multiple Missing Cell Defect Modeling for QCA Devices

Considering the limitations of CMOS technology, the Quantum-dot Cellular Automata (QCA) is emerging as one of the alternatives for Integrated Circuit (IC) Technology. A lot of work is being carried out for design, fabrication and testing of QCA circuits. In this paper, we have worked on defect analysis, fault models development and deriving various properties for QCA Majority Voter (MV) to effectively generate the test patterns for QCA circuits. It has been shown that unlike CMOS technology, single missing cell consideration is not enough for QCA technology. We have presented that the Multiple Missing Cell (MMC) defect, which is very natural at nanoscale, causes the sizable difference in functionality compared to Single Missing Cell consideration described in literature, and hence, must be considered while test generation. The proposed MMC is supported by exhaustive simulation results as well as kink energy based mathematical analysis. Further, Verilog fault models are proposed which can be used for the functional, timing verification and activation of faults caused by MMC defect. The effect of MMC on output is analyzed in stand-alone MV as well as when MV is a part of circuit. At the end, we have proposed the test properties of MV when being used as MV itself, as AND gate or OR gate. These properties may be further helpful in development of test generation algorithms.     

Analysis of missing and additional cell defects in sequential quantum-dot cellular automata

The defect characterization of sequential devices and circuits, implemented by molecular quantum-dot cellular automata (QCA), is analyzed in this paper. A RS-type flip–flop is first introduced; this flip–flop takes into account the timing issues associated with the adiabatic switching of this technology and its requirements. It is then shown that a D-type flip–flop can be constructed with an embedded QCA wire which extends over multiple clocking zones. The logic-level characterization of both flip–flop devices is provided. A single additional and missing cell defect model is assumed for molecular implementation. For sequential circuits, defect characterization is pursued. It is shown that defects affect the functionality of basic QCA devices, resulting mostly in unwanted inversion and majority voter acting as a wire at logic level. In this paper, it is shown that a device-level characterization of the defects and faults can be consistently extended to a circuit-level analysis.     

QCA电路的缺陷研究

针对量子元胞自动机电路中出现的元胞移位等元胞缺陷,介绍了基于QCADesigner的元胞缺陷分析,得出了特定结构的容错范围。对于制造过程出现的单电子故障,分析了不同输入时单电子故障对传输线和反相器的影响。对于制造过程中出现的漂移电荷缺陷,分析了这些缺陷对传输线的影响。通过改变元胞与传输线之间的距离,研究了QCA传输线之间的串扰问题,得出了其容错范围。最后对RS触发器中出现的元胞缺陷采用测试序列进行了分析研究,从而为进一步研究QCA电路的缺陷提供了依据和方向。     

量子元胞自动机器件和电路的研究进展

量子元胞自动机(QCA)是一种新颖的纳米技术,该技术不再通过电流或电压而是基于场相互作用进行信息的计算和传递。首先,综述了两种量子元胞自动机(EQCA和MQCA)器件的计算原理、基本逻辑门和时钟。指出了QCA元胞构成的不同线结构可在相同层交叉传递信号而不受影响。然后,进一步总结了制备QCA器件和功能阵列或电路的实验方法和材料,得出MQCA器件和分子EQCA器件的发展将使该器件逐步达到实际应用水平的结论。详细讨论了目前QCA器件和电路(尤其是存储单元结构)研究取得的重要进展以及面临的问题。提出了QCA器件未来理论和应用研究中的开放课题和方向。     

Reversible Gates and Testability of One Dimensional Arrays of Molecular QCA

An extensive literature exists on the mathematical characterization of reversible logic. However, the possible technological basis of this computing paradigm still remains unsolved. In this paper, quantum-dot cellular automata (QCA) is investigated for testable implementations of reversible logic. Two new reversible gates (referred to as QCA1 and QCA2) are proposed. These gates are compared (in terms of delay, area and logic synthesis) with other reversible gates (such as Toffoli and Fredkin) for QCA implementation. Due to the expected high error rates in nano-scale manufacturing, testing of nano devices, including QCA, has received considerable attention. The focus of this paper is on the testability of a one-dimensional array made of QCA reversible gates, because the bijective nature of reversible gates significantly facilitates testing of arrays. The investigation of testability relies on a fault model for molecular QCA that is based on a single missing/additional cell assumption. It is shown that C-testability of a 1D reversible QCA gate array can be guaranteed for single fault. Theory and circuit examples show that error masking can occur when multiple faults are considered.     

基于QCA可编程逻辑阵列单元的元胞缺陷研究

介绍了一种量子元胞自动机(QCA)可编程逻辑阵列结构,该结构可用于实现量子元胞自动机大规模可编程逻辑电路,采用QCADesigner仿真软件研究了元胞缺失、移位缺陷和未对准缺陷对可编程逻辑阵列单元逻辑功能的影响。得出了特定结构下,每个元胞移位缺陷和未对准缺陷的最大错位距离,以及导线模式中存在特定位置的8个可缺失元胞。这为缺陷单元的应用提供了一个具体的参数标准,提高了PLA阵列的单元利用率。     

On the Tolerance to Manufacturing Defects in Molecular QCA Tiles for Processing-by-wire

Among emerging technologies, Quantum-dot Cellular Automata (QCA) relies on innovative computational paradigms. For nano-scale implementation, the so-called processing-by-wire (PBW) paradigm in QCA is very effective as processing takes place, while signal communication is accomplished. This paper analyzes the defect tolerance properties of PBW for manufacturing tiles by molecular QCA cells. Based on a 3?×?3 grid and various input/output arrangements in QCA cells, different tiles are analyzed and simulated using a coherence vector engine. The functional characterization and polarization level of these tiles for undeposited cell defects are reported and detailed profiles are provided. It is shown that novel features of PBW are possible due to the spatial redundancy of the cells in the tiles that permits to retain at high probability the fault free function in the presence of defects. Moreover, it is shown that QCA tiles are robust and inherently tolerant to cell defects (by logic equivalence, also additional cell defects can be accommodated).     

A novel measurement technique to assess the effects of coronary brachytherapy in clinical trials

This paper presents a novel measurement technique to assess the effects of coronary brachytherapy. This new technique is based upon the conventional quantitative coronary analysis (QCA) technique, which is accepted worldwide as an accurate and reliable analysis tool for clinical trials. This paper provides the definitions and main issues important for correct brachytherapy analysis. Based on these definitions, this novel technique is implemented as an extension of conventional QCA software, as a multisegmental analysis tool. It allows to follow the influence of radiation on restenosis, and the mutual relation between intervention devices. A pilot interobserver study was performed to assess the reliability and reproducibility of the brachytherapy analysis tool, using 15 patient cases. The validation results show that the segment lengths, minimum lumen diameter, and reference diameters of the user-defined and derived (sub)segments can be assessed reproducible. However, these good results can only be obtained, when strict and extensive image acquisition and image analysis protocols are followed. From this pilot validation study presented in this paper and only based on a small number of patients, we may conclude that the software can be applied to clinical trials.     

Design and evaluation of an ultra-area-efficient fault-tolerant QCA full adder

Quantum-dot cellular automata (QCA) has been studied extensively as a promising switching technology at nanoscale level. Despite several potential advantages of QCA-based designs over conventional CMOS logic, some deposition defects are probable to occur in QCA-based systems which have necessitated fault-tolerant structures. Whereas binary adders are among the most frequently-used components in digital systems, this work targets designing a highly-optimized robust full adder in a QCA framework. Results demonstrate the superiority of the proposed full adder in terms of latency, complexity and area with respect to previous full adder designs. Further, the functionality and the defect tolerance of the proposed full adder in the presence of QCA deposition faults are studied. The functionality and correctness of our design is confirmed using high-level synthesis, which is followed by delineating its normal and faulty behavior using a Probabilistic Transfer Matrix (PTM) method. The related waveforms which verify the robustness of the proposed designs are discussed via generation using the QCADesigner simulation tool.     

A Test Generation Framework for Quantum Cellular Automata Circuits

In this paper, we present a test generation framework for quantum cellular automata (QCA) circuits. QCA is a nanotechnology that has attracted recent significant attention and shows promise as a viable future technology. This work is motivated by the fact that the stuck-at fault test set of a circuit is not guaranteed to detect all defects that can occur in its QCA implementation. We show how to generate additional test vectors to supplement the stuck-at fault test set to guarantee that all simulated defects in the QCA gates get detected. Since nanotechnologies will be dominated by interconnects, we also target bridging faults on QCA interconnects. The efficacy of our framework is established through its application to QCA implementations of MCNC and ISCAS'85 benchmarks that use majority gates as primitives     

Operation of a quantum-dot cellular automata (QCA) shift register and analysis of errors

Quantum-dot cellular automata (QCA) is a digital logic architecture that uses single electrons in arrays of quantum dots to perform binary operations. A QCA latch is an elementary building block which can be used to build shift registers and logic devices for clocked QCA architectures. We discuss the operation of a QCA latch and a shift register and present an analysis of the types and properties of errors encountered in their operation.     

基于双量子阱系统概率模型的传输线背景电荷分析

量化分析了背景电荷影响下量子元胞自动机的翻转特性。提出了一种新的时不变转换模型—双量子阱系统概率模型。与元胞间哈特里逼近法和全基矢量法相比,提出的模型降低了运算量。仿真证明,距QCA传输线186nm范围内若存在背景电荷将造成目标元胞的错误翻转。错误翻转的元胞处于两种新态。因此,双稳态模型在背景电荷的分析中不再适用。     

A hierarchical defect repair approach for hybrid nano/CMOS memory reliability enhancement

Due to the small size of nanoscale devices, they are highly prone to process disturbances which results in manufacturing defects. Some of the defects are randomly distributed throughout the nanodevice layer. Other disturbances tend to be local and lead to cluster defects caused by factors such as layer misalignments, line width variations and contamination particles. In this paper, initially a method is proposed for separately identifying cluster defects from random ones. Subsequently a hardware repair structure is presented to repair the cluster defects with rectangular window transfer vectors using a range-matching content addressable memory (RM-CAM) and random defects using defect aware triple-modular redundancy (DA-TMR) columns. It is shown that a combination of these two approaches is more effective for repairing defects at higher error rates with an acceptable overhead. The effectiveness of the technique is shown by examining defect recovery results for different fault distribution scenarios. Also the mapping circuit hardware performance parameters are presented for various memory sizes and the speed, power dissipation and overhead factors are reported.     

Design of reliable universal QCA logic in the presence of cell deposition defect

The emergence of Quantum-dot Cellular Automata (QCA) has resulted in being identified as a promising alternative to the currently prevailing techniques of very large scale integration. QCA can provide low-power nanocircuit with high device density. Keeping aside the profound acceptance of QCA, the challenge that it is facing can be quoted as susceptibility to high error rate. The work produced in this article aims towards the design of a reliable universal logic gate (r-ULG) in QCA (r-ULG along with the single clock zone and r-ULG-II along with multiple clock zones). The design would include hybrid orientation of cells that would realise majority and minority, functions and high fault tolerance simultaneously. The characterisation of the defective behaviour of r-ULGs under different kinds of cell deposition defects is investigated. The outcomes of the investigation provide an indication that the proposed r-ULG provides a fault tolerance of 75% under single clock zone and a fault tolerance of 100% under dual clock zones. The high functional aspects of r-ULGs in the implementation of different logic functions successfully under cell deposition defects are affirmed by the experimental results. The high-level logic around the multiplexer is synthesised, which helps to extend the design capability to the higher-level circuit synthesis.     

A unified yield model incorporating both defect and parametriceffects

A new approach to modeling yield is presented, which inherently includes both the effects of the conventional defect contributors and the parametric yield loss contributors often treated separately in existing yield models. These parametric yield losses are particularly important during the startup yield-improvement phase of new technology introduction, in many performance-sensitive products such as analog devices and high-speed digital devices, and in analyses of bin-split yields. By assuming a distribution in the size of defects, from point defects up to defects as large as or larger than a wafer, the parametric yield contributors can be viewed as simply rather large, design-dependent defects, which will render IC's unacceptable if any portion of the large defect overlaps the defect-sensitive area of a chip. In this way, the conventional Poisson model, or various extensions of the well-known Murphy model, can be augmented in a straightforward and general way to include parametric yield loss. It is shown that parametric yield losses introduce an additional die size dependence for yield that can help to account for the observed dependence of yield on die area. The model is compared to other models and to experimental yield data to illustrate both its utility in separating yield contributors and its close agreement with experimental yield data     

Efficient design of parity preserving logic in quantum-dot cellular automata targeting enhanced scalability in testing

Design of parity preserving logic based on emerging nanotechnology is very limited due to present technological limitation in tackling its high error rate. In this work, Quantum-dot cellular automata (QCA), a potential alternative to CMOS, is investigated for designing easily testable logic circuit. A novel self-testable logic structure referred to as the testable-QCA (t-QCA), using parity preserving logic, is proposed. Design flexibility of t-QCA then evaluated through synthesis of standard functions. The programmability feature of t-QCA is utilized to implement an ALU, realizing six important functions. Although the parity preservation property of t-QCA enables concurrent detection of permanent as well as the transient faults, an augmented test logic circuit (TC) using QCA primitives has been introduced to cover the cell defects in nanotechnology. Experimental results establish the efficiency of the proposed design that outperforms the existing technologies in terms of design cost and test overhead. The achievement of 100% stuck-at fault coverage and the 100% fault coverage for single missing/additional cell defects in QCA layout of the t-QCA gate, address the reliability issues of QCA nano-circuit design.     

Mound defect modeling in yield forecasts

Although the majority of defects found in manufacturing lines have predominantly two-dimensional effects, there are many situations in which 2-D defect models do not suffice, e.g., tall layer bulks, residual resist flakes, and extraneous materials embedded in the IC. In this paper a more general model based on mound defects is presented. Both catastrophic and soft effects of mound defects are investigated. The defect model is based on the geometrical properties that result from the interaction between IC and defect size in two coordinate spaces: x-y and z. The approach to model catastrophic effects is a natural extension to the concept of critical areas, namely, the extraction of critical volumes. The simplicity of the extraction method makes it suitable for inclusion in common layout editing tools. Through the course of this work hints to the origins of mound defects will be given, conditions to capture critical volumes will be developed, realistic layout results will be shown, and a yield model taking into account these new kind of defects will be presented     

量子元胞自动机共面五输入择多门结构的分析与设计

量子元胞自动机（Quantum-dot Cellular Automata,QCA）是一种具有新型计算范式的纳米器件,它是未来有望替代传统CMOS器件的有力竞争者之一.本文首先从QCA器件的功耗角度出发,对影响半径为41nm的QCA共面系统中元胞的耦合度进行建模,根据元胞之间的位置关系构造QCA门结构模型,据此对现有的共面五输入择多门进行分类,通过性能分析总结其结构特点,以此设计出一个新的低功耗五输入择多门,测试结果表明该结构功耗最低且其他性能也相对较优.另外,为验证所提出五输入择多门在电路中的性能,本文选择MR Azghadi全加器设计了一款共面QCA全加器,与同类加法器相比性能也最优.     

一位QCA数值比较器的可靠性研究

针对量子元胞自动机电路中存在的元胞移位、元胞未对准、元胞遗漏、元胞旋转等固有缺陷,采用概率转移矩阵方法建立了一位QCA数值比较器的可靠性模型,并对其可靠性进行了深入分析。对于不同的输入,分别比较了各组成元件在同样的故障概率水平下对整体可靠性(正确输出的概率)的不同影响。仿真结果表明,在所有的输入情况下传输线始终是影响其可靠性的主要因素,从而确定了传输线在该数值比较器中的重要性,进而为大规模QCA数值比较器的设计以及可靠性的提高提供了依据。     

适用SAW器件的ZnO/Ti/Si薄膜制备及缺陷分析

在Si(100)衬底和Ti/Si(100)衬底上分别制备了ZnO薄膜,探讨了Ti缓冲层对ZnO薄膜结构和缺陷的影响,利用X射线衍射(XRD)测试了ZnO薄膜的晶体结构及择优取向,利用原子力显微镜(AFM)观察ZnO薄膜的表面粗糙度(RMS),利用光致发光(PL)光谱检测了ZnO薄膜的缺陷,利用四探针法测试了ZnO薄膜的电阻率。结果表明,在Ti/Si(100)衬底上、衬底温度350℃的条件下,制备的ZnO薄膜表面光滑、缺陷少、电阻率高且具有高C轴取向。本文这一工作对于压电薄膜缺陷分析及高性能ZnO的声表面波(SAW)器件研制有重要意义。