A pulse position modulation transmission system for remote control of a TV set

A transmitter-receiver combination for remote control of a color TV set is described. The transmitter is a 1.6/spl times/1.9 mm/SUP 2/ chip in linear bipolar technology. It generates a 5-bit PPM code for transmission of 32 commands, requires only 5 external components and an 8/spl times/4 single-pole single-throw keyboard. Standby power is zero. The receiver is a 3.1/spl times/3.5 mm/SUP 2/ p-MOS chip and allows for a 20-channel selection. It has 3 D/A converters on chip to generate the analog control signals. It also controls the TV receivers AFC and on-screen display.     

A high-speed multiplier using a redundant binary adder tree

A 16-bit /spl times/ 16-bit multiplier for 2 two's-complement binary numbers based on a new algorithm is described. This multiplier has been fabricated on an LSI chip using a standard n-E/D MOS process technology with a 2.7-/spl mu/m design rule. This multiplier is characterized by use of a binary tree of redundant binary adders. In the new algorithm, n-bit multiplication is performed in a time proportional to log/SUB 2/ n and the physical design of the multiplier is constructed of a regular cellular array. This new algorithm has been proposed by N. Takagi et al. (1982, 1983). The 16-bit/spl times/16-bit multiplier chip size is 5.8 /spl times/ 6.3 mm/SUP 2/ using the new layout for a binary adder tree. The chip contains about 10600 transistors, and the longest logic path includes 46 gates. The multiplication time was measured as 120 ns. It is estimated that a 32-bit /spl times/ 32-bit multiplication time is about 140 ns.     

Time interleaved converter arrays

High-speed monolithic converters normally use a variation of the flash technique, which 2/SUP n/ comparators in parallel to obtain a fast n-bit conversion. Although this method allows for high converter bandwidth, it is not very area efficient, and results in large die sizes for even modest resolution converters. In the technique presented here, a number of small but area efficient converters are operated in a time-interleaved fashion to achieve the bandwidth of a flash circuit, but in a substantially smaller area. This technique is analyzed with respect to noise and distortion resulting from nonideal array characteristics, and is demonstrated by way of a four-way array test-chip. This chip consists of four time-interleaved 7-bit weighted-capacitor A/D converters fabricated in a 10 /spl mu/m metal-gate CMOS process. Full 7-bit linearity is maintained up to a 2.5 MHz conversion rate, with operation at reduced linearity continuing to approximately 4 MHz. The design of this chip, and anticipated characteristics if fabricated in a modern 4-5 /spl mu/m process are described.     

A fully parallel 10-bit A/D converter with video speed

Describes a 20 MHz conversion speed, fully parallel, analog-to-digital converter device which has been designed for use at video speed. Laser trimming technology has been adopted to improve nonlinearity errors brought about by reference voltage distortion to less than 1 mV to realize a /SUP 1///SUB 2/ LSB accuracy for the 10-bit A/D converter. The large number of comparator stages required by a parallel converter leads to a high number of components and large power dissipation. Therefore, a circuit with a reduced number of components and optimized power has been used. The process employed is a 3 /spl mu/m bipolar process, which integrates about 40000 elements onto a 9.2/spl times/9.8 mm chip.     

A 6-GSamples/s multi-level decision feedback equalizer embedded in a 4-bit time-interleaved pipeline A/D converter

A 4-bit 6-GS/s pipeline A/D converter with 10-way time-interleaving is demonstrated in a 0.18-/spl mu/m CMOS technology. The A/D converter is designed for a serial-link receiver and features an embedded adjustable single-tap DFE for channel equalization. The ISI subtraction of the DFE is performed at the output of each pipeline stage; hence the effective feedback delay requirement is relaxed by 6/spl times/. Code-overlapping of the 1.5-bit pipeline stage along with digital error correction is used to absorb and remove the remainder of the ISI. The measured A/D converter performance at 6-GSamples/s shows 22.5 dB of low-frequency input SNDR for the calibrated A/D converter with /spl plusmn/0.25 LSB and /spl plusmn/0.4 LSB of INL and DNL, respectively. The input capacitance is 170 fF for each A/D converter. The DFE tap coefficient is adjustable from 0 to 0.25 with 6-bits of programmable weight. With a DFE coefficient of 0.2, the measured DFE performance shows 2.5 dB of amplitude boosting for a 3-GHz input sinusoid. The 1.8/spl times/1.6 mm/sup 2/ chip consumes 780 mW of power from a 1.8-V power supply.     

A CMOS stereo 16-bit D/A converter for digital audio

A complete monolithic stereo 16-bit D/A converter primarily intended for use in compact-disc players and digital audio tape recorders is described. The D/A converter achieves 16-bit resolution by using a code-conversion technique based upon oversampling and noise shaping. The band-limiting filters required for waveform smoothing and out-of-band noise reduction are included. Owing to the oversampling principle most applications will require only a few components for an analog postfilter. The converter has a linear characteristic and linear phase response. The chip is processed in a 2-/spl mu/m CMOS process and the die size is 44 mm/SUP 2/. Only a single 5-V supply is needed.     

A 4160-bit C4D serial memory

A 4160-bit serial memory chip has been designed, fabricated, and tested using as the basic memory cell the conductively connected charge-coupled device (CCD) or C4D. The chip includes an inverting regenerator every 65 bits and a reading tap every 130 bits. Also on-chip is a recirculating amplifier which senses the charge packet as it reaches the end of the register and feeds it back to the input. This means that once data has been written onto the chip, it will be retained as long as the regenerator supply and the two clocks are on. The chip has two multiplexed halves to obtain a data rate of twice the clock frequency. The active area of the chip is 12 mm/SUP 2/ or 2900 /spl mu/m/SUP 2/ per bit. Operation was obtained for arbitrary data streams at clock rates of 1 kHz to 1.6 MHz (3.2 MHz data rate). Power dissipation varies linearly with frequency and is 16 /spl mu/W per bit at the highest frequency. Maximum read latency is 80 /spl mu/s at this frequency. This performance demonstrates the feasibility of the C4D as a component for a medium speed large-scale memory.     

An experimental 4-Mbit CMOS DRAM

A 4-Mb dynamic RAM has been designed and fabricated using 1.0-/spl mu/m twin-tub CMOS technology. The memory array consists of trenched n-channel depletion-type capacitor cells in a p-well. Very high /spl alpha/-particle immunity was achieved with this structure. One cell measures 3.0/spl times/5.8 /spl mu/m/SUP 2/ yielding a chip size of 7.84/spl times/17.48 mm/SUP 2/. An on-chip voltage converter circuit was implemented as a mask option to investigate a possible solution to the MOSFET reliability problem caused by hot carriers. An 8-bit parallel test mode was introduced to reduce the RAM test time. Metal mask options provide static-column-mode and fast-age-mode operation. The chip is usable as /spl times/1 or /spl times/4 organizations with a bonding option. Using an external 5-V power supply, the row-address-strobe access time is 80 ns at room temperature. The typical active current is 60 mA at a 220-ns cycle time with a standby current of 0.5 mA.     

A 4-Mbit DRAM with half-internal-voltage bit-line precharge

A single 5-V supply 4-Mb dynamic random access memory (DRAM) was developed by using a buried-storage-electrode memory cell, a half-internal-voltage bit-line precharge method combined with a constant voltage converter, and a high signal-to-noise ratio sensing scheme. The chip was designed in a double-polycide, single-Al, epitaxial substrate NMOS technology with a 0.8-/spl mu/m minimum design rule. As a result, a 4M word/spl times/1-bit DRAM with 95-ns typical access time and 99.2-mm/SUP 2/ chip area was attained by 10.58-/spl mu/m/SUP 2/ storage cells.     

A 40-GHz-bandwidth, 4-bit, time-interleaved A/D converter using photoconductive sampling

GaAs photoconductive switches have been integrated with two parallel 4-bit CMOS analog-to-digital (A/D) converter channels to demonstrate the time-interleaved sampling of wideband signals. The picosecond sampling aperture provided by low-temperature-grown-GaAs metal-semiconductor-metal switches, in combination with low-jitter short-pulse lasers, enables the optically-triggered sampling of electrical signals with tens of gigahertz bandwidth at low to medium resolution. A pair of parallel sampling paths, one for sampling and the second for feedthrough cancellation, generate a differential held signal that is quantized by a low-input capacitance, high-speed flash A/D converter. Dynamic offset averaging is employed to improve converter linearity. An experimental time-interleaved two-channel A/D converter provides about 3.5 effective bits of resolution for inputs up to 40 GHz when tested at an optically-triggered sampling rate of 160 MHz. The sampling rate was limited by the available optical source. Each A/D converter channel operates up to a 640-MHz conversion rate, dissipates 70 mW of power, and occupies an area of 150 /spl mu/m /spl times/ 450 /spl mu/m in a 2.5-V, 0.25-/spl mu/m CMOS technology.     

A 600-MS/s 5-bit pipeline A/D converter using digital reference calibration

The design of a 600-MS/s 5-bit analog-to-digital (A/D) converter for serial-link receivers has been investigated. The A/D converter uses a closed-loop pipeline architecture. The input capacitance is only 170 fF, making it suitable for interleaving. To maintain low power consumption and increase the sampling rate beyond the amplifier settling limit, the paper proposes a calibration technique that digitally adjusts the reference voltage of each pipeline stage. Differential input swing is 400 mV/sub p-p/ at 1.8-V supply. Measured performance includes 25.6 dB and 19 dB of SNDR for 0.3-GHz and 2.4-GHz input frequencies at 600 MS/s for the calibrated A/D converter. The suggested calibration method improves SNDR by 4.4 dB at 600 MS/s with /spl plusmn/0.35 LSB of DNL and /spl plusmn/0.15 LSB of INL. The 180 /spl times/ 1500 /spl mu/m/sup 2/ chip is fabricated in a 0.18-/spl mu/m standard CMOS technology and consumes 70 mW of power at 600 MS/s.     

A single chip radix-2 FFT butterfly architecture using parallel data distributed arithmetic

It is shown how distributed arithmetic techniques can be applied in parallel-data arithmetic computations to achieve highly regular and efficient VLSI structures on silicon. Two individual arithmetic processor chips are described as examples of the technique. The chips described, which are intended primarily for computation of the FFT butterfly, each contain the functional equivalence of two parallel pipelined multipliers. The first chip is an 8-bit prototype device which has been designed and fabricated on a standard 5-/spl mu/m silicon-gate n-channel MOS process. The second chip is a 16-bit CMOS-SOS design which uses a modified architecture to achieve higher clocking rates and improved versatility in systems use.     

A monolithic 14 bit/20 /spl mu/s dual channel A/D converter

A 14-bit monolithic coarse-fine integration A/D converter with 20-/spl mu/s conversion time is described. The IC has internal sample-and-integrate circuits and dual-channel A/D conversion capability. Overall performance, including sample-and-integrate circuits, is 0.01% distortion and 84-dB S/N ratio. All of the analog/digital circuits for dual-channel A/D conversion are integrated on a single chip by using an advanced nitride self-aligned (advanced-NSA) process.     

A 32-bit VLSI CPU chip

A fully integrated 32-bit VLSI CPU chip utilizing 1 /spl mu/m features is described. It is fabricated in an n-channel silicon gate, self-aligned technology. The chip contains about 450000 transistors and executes microinstructions at approximately one per 55 ns clock cycle. It can execute a 32-bit binary integer add in 55 ns, a 32-bit binary integer multiply in 1.8 /spl mu/s, and a 64-bit floating point multiply in 10.4 /spl mu/s. The instruction set provides the functions of an advanced mainframe CPU. Because the implementation of such a complex device poses an organizational as well as a technical challenge, the design philosophy that was adopted is summarized briefly. Careful attention was paid to designer productivity, and design flexibility and testability.     

A low-power, bipolar, two's complement serial pipeline multiplier chip

A 4-bit, general-purpose, two's complement serial pipeline multiplier chip has been designed and fabricated in the bipolar GIMIC-O process. The chip can provide the following functions in 24-pin dual-in-line packages: (1) two's complement/two's complement 4-bit serial pipeline multiplier with programmable coefficients, (2) sign magnitude/two's complement 4-bit serial pipeline multiplier with programmable coefficients, (3) 5-bit dynamically programmable adder/subtractor, (4) 2/SUP -K/ scaler; (5) overflow corrector. Packages can be cascaded to provide functions of length greater than 4 bits. Nonsaturating circuit techniques, emitter function logic combined with current-steering trees, are effectively utilized to make high-performance, low-power circuits using a simple bipolar technology. The multiplier circuitry is compatible at inputs and outputs with standard emitter coupled logic and uses a standard -5.2/spl plusmn/10 percent power supply. Fully programmable multiplication at clock rates greater than 20 MHz is achieved with a power consumption of 37.5 mW/bit.     

A low-power 22-bit incremental ADC

This paper describes a low-power 22-bit incremental ADC, including an on-chip digital filter and a low-noise/low-drift oscillator, realized in a 0.6-/spl mu/m CMOS process. It incorporates a novel offset-cancellation scheme based on fractal sequences, a novel high-accuracy gain control circuit, and a novel reduced-complexity realization for the on-chip sinc filter. The measured output noise was 0.25 ppm (2.5 /spl mu/V/sub RMS/), the DC offset 2 /spl mu/V, the gain error 2 ppm, and the INL 4 ppm. The chip operates with a single 2.7-5 V supply, and draws only 120 /spl mu/A current during conversion.     

A single-chip 80-bit floating point processor

A single-chip 80-bit floating point VLSI processor capable of performing 5.6 million floating point operations per second has been realized using 1.2-/spl mu/m n-well CMOS technology. The processor handles 80-bit double-extended floating point data conforming to IEEE standard 754. The chip has 128 microinstructions which are stored in an on-chip ROM. By programming microinstruction sequences in an external control storage, not only basic arithmetic operation but also special arithmetic functions can be performed. A composite design method supported by a hierarchical design automation system was used to quickly lay out 50K gates including a 64-/spl times/64-bit multiplier and 15 kb of memory on a chip with a die size of 10/spl times/10 mm/SUP 2/. Only 11 man-months were required for the effort.     

A 14-bit monotonic NMOS D/A converter

A new configuration of a 14-bit digital-to-analog (D/A) converter has been fabricated as an experimental monolithic NMOS chip. The concept utilizing two cascaded resistor strings delivers an inherent 14 bit monotonicity and a static voltage output signal. The small chip size of about 8.5 mm/SUP 2/ and the saving of external components make the converter applicable for low-cost high-resolution control loop systems. A modified test chip is also described which has been provided as a step into the field of accurate monolithic converters needed for digital audio systems. A voltage output settling time less than 10 /spl mu/s and a linearity at the 12 bit level have been achieved.     

A monolithic 14-bit D/A converter

A monolithic 14-bit D/A converter using `dynamic element matching' to obtain a high accuracy and good long-term stability is described. Over a temperature range from -50/spl deg/ to 70/spl deg/C the nonlinearity is less than one-half least significant bit (/SUP 1///SUB 2/LSB). Dynamic tests show a distortion at a level of about -90 dB with respect to the maximum sinewave output. Nearly no glitches are found, so the converter can be operated without a deglitcher circuit. The chip, with a size of 3.1/spl times/3.2 mm, contains all elements needed, except the output amplifier and digital input latches.