The Concept of Operational Rank Extractor

An operational rank extractor (ORE) is introduced in this paper as an operational amplifier having rank extractors at its inputs. This versatile building block can implement a variety of nonlinear transfer functions such as a dead-zone amplifier, a limiter, a full-wave rectifier, and a tri-state comparator (including hysteretic behavior). A 6-input circuit has been implemented in a 2 m CMOS process. The total silicon area is 460 × 100m², and the circuit dissipates 0.7 mW from a single 5 V supply. Various circuit configurations are analyzed theoretically, and experimental results are also provided.     

Current Mode Circuit Implementations of PWL Functions

Current-mode techniques have been used to realize improved basic building blocks of elementary piecewise linear (PWL) functions. These alternative circuit implementations, used for synthesis of precision PWL transfer characteristics, are described and compared in performance. In this paper, two optional topologies of the PWL function building blocks are proposed, based on the regulated cascode current mirror, current sources, Schottky prebiased diodes, and improved CMOS class AB prebiased diodes. The comparison of DC and high frequency performances is based on HSPICE simulation results and shows very good DC accuracy and transient time response of the proposed building blocks.     

Design and Analysis of Built-In Testers for CMOS Switched-Current Circuits

This paper presents the design and analysis of a built-in tester circuit for MOS switched-current circuits used in low-voltage/low-power mixed-signal circuits/systems. The use of the tester can reduce the test length significantly. The developed tester is comprised of a current comparator, a voltage window comparator, and a digital latch. The current comparator is required to have high-accuracy, low-power consumption, simple structure with small chip area, and moderate speed. Results show that the developed current comparator circuit is developed with a small offset current, 0.1 nA, low power consumption, 20 W, and a layout area of 0.01 mm², where the circuit is simulated with the MOSIS SCN 2 m CMOS process parameters and 2 V supply voltage.     

High-Speed High-Precision CMOS Current Conveyor

In this paper a new class-AB CMOS second generation current conveyor (CCII) based on a novel high-performance voltage follower topology is proposed. Post-layout simulation results from a 0.8 m design supplied at 3.3 V show very low resistance at node X (<50 ), high frequency operation (100 MHz), high precision in the voltage and current transference and reduced offset. As application examples, a V-I converter and a current feedback operational amplifier (CFOA) have been implemented. The latter presents slew-rate levels higher than ±100 V/s.     

A CMOS Voltage Comparator with Rail-to-Rail Input-Range

A simple new continuous-time CMOS comparator circuit with rail-to-rail input common-mode range and rail-to-rail output is presented. This design uses parallel complementary decision paths to accommodate power-supply-valued inputs. The 2 decision results are combined at a current summing node, converted to a voltage, and buffered to drive voltage loads. The circuit has been realized in an area of 416 m×221 m in a MOSIS 2-micron CMOS technology. Average delay of about 63 ns has been measured at 3 V (1.3 mA), and about 89 ns at 5 V (1.1 mA).     

CMOS Analog Implementation of a Discrete-Time 9-Tap FIR Filter with Circular Buffer Architecture

This paper presents the design and simulation of a 9-Tap CMOS Analog Discrete-Time Finite Impulse Response (FIR) Filter system. This unique design features a Circular Buffer Architecture which achieves high sampling rate that can be easily expanded to improve speed and extended to higher order filters. Novel area-efficient four quadrant CMOS analog adder and multiplier circuits are employed to respond for high frequency and wide linear range inputs. The layout for all circuits has been realized using the design tool MAGIC with a 1.2 m CMOS process. The performance for each circuit and the whole system are characterized using HSPICE simulation based on the extracted MAGIC netlist. The 9-tap filter was designed to achieve 5 MHz sampling rate. The implemented design requires a total chip area of 1690.9 m by 2134.2 m and ±5 volt power supply.     

A 70-MHz Continuous-Time CMOS Band-Pass ΣΔ Modulator for GSM Receivers

A 70-MHz continuous-time CMOS band-pass modulator for GSM receivers is presented. Impulse-invariant-transformation is used to transform a discrete-time loop-filter transfer function into continuous-time. The continuous-time loop-filter is implemented using a transconductor-capacitor (G _m -C) filter. A latched-type comparator and a true-single-phase-clock (TSPC) D flip-flop are used as the quantizer of the modulator. Implemented in a MOSIS HP 0.5-m CMOS technology, the chip area is 857 m × 420 m, and the total power consumption is 39 mW. At a supply voltage of 2.5 V, the maximum SNDR is measured to be 42 dB, which corresponds to a resolution of 7 bits.     

RF CMOS Cells for Wireless Applications

There is increasing interest in the use of CMOS circuits for high frequency highly integrated wireless telecommunications systems. This paper presents the results of on-going work into the development of a cell library that includes many of the circuit elements required for the high frequency sub-systems of communications integrated circuits. The cell library studied included an RF control element, single ended Class A amplifier, RF isolator, and Gilbert cell mixer circuit topologies. Circuit design criteria and measurement results are presented. All cells were fabricated using standard 2.0, 1.2, and 0.8 m CMOS integrated circuit fabrication processes with no post-processing performed. The results indicate that 2.0 m CMOS can be used successfully up to approximately 250 MHz with 0.8 m cells useful up to approximately 1000 MHz.     

Systematic Width-and-Length Dependent CMOS Transistor Mismatch Characterization and Simulation

This paper presents a methodology for characterizing the random component of transistor mismatch in CMOS technologies. The methodology is based on the design of a special purpose chip which allows automatic characterization of arrays of NMOS and PMOS transistors of different sizes. Up to 30 different transistor sizes were implemented in the same chip, with varying transistors width W and length L. A simple strong inversion large signal transistor model is considered, and a new five parameters MOS mismatch model is introduced. The current mismatch between two identical transistors is characterized by the mismatch in their respective current gain factors /, V _TO threshold voltages , bulk threshold parameters , and two components for the mobility degradation parameter mismatch ₀ and _e. These two components modulate the mismatch contribution differently, depending on whether the transistors are biased in ohmic or in saturation region. Using this five parameter mismatch model, an extraordinary fit between experimental and computed mismatch is obtained, including minimum length (1 m) transistors for both ohmic and saturation regions. Standard deviations for these five parameters are obtained as well as their respective correlation coefficients, and are fitted to two dimensional surfaces f(W, L) so that their values can be predicted as a function of transistor sizes. These functions are used in an electrical circuit simulator (Hspice) to predict transistor mismatch. Measured and simulated data are in excellent agreement.     

A 1.2 V Rail-to-Rail Analog CMOS Rank-Order Filter with k-WTA Capability

In this paper, we design a rank-order filter with k-WTA capability for 1.2 V supply voltage. The circuit can find a rank order among a set of input voltages by setting different binary signals. Moreover, without modifying the circuit, the k-WTA function can be easily configured. The circuit has been designed using a 0.5 m DPDM CMOS technology. Seven input voltages are used to verify the performance of the circuit. The results of HSPICE post-layout simulation show that the response time of the circuit is 10 s for each rank-order operation, the input dynamic range is rail-to-rail, and the resolution is 10 mV for 1.2 V supply voltage. An experimental chip has been fabricated, in which accuracy of the comparator is measured as 40 mV for low-voltage operation. The dynamic power dissipation of the chip is 550 W.     

Design of a New High Speed Amplifier Circuit for the Analog Subsystems

A high speed CMOS amplifier circuit with a new architecture especially suited for analog subsystems and a simple high speed CMOS comparator utilizing the proposed CMOS amplifier circuit are presented. The proposed circuit is simulated using 0.35 m process parameters. The configuration results in several performance improvements over a typical CMOS differential to single ended amplifier. Design details and simulation results show that the newly designed CMOS amplifier circuit and the high speed CMOS comparator are applicable to high speed analog subsystems, especially the flash A/D converter.     

Novel Architectures of Class AB CMOS Mirrors with Programmable Gain

Two schemes for power-efficient gain-programmable V-I conversion based on class AB CMOS mirrors are introduced. The proposed topologies also allow for high-speed gain-programmable precision rectification. Experimental results from a test chip prototype in 0.5- m CMOS technology with ±1 V supplies are shown that validate the proposed circuits.     

β-bit serial/parallel multipliers

A generalized -bit least-significant-digit (LSD) first, serial/parallel multiplier architecture is presented with 1n wheren is the operand size. The multiplier processes both the serial input operand and the double precision product -bits per clock cycle in an LSD first, synchronous fashion. The complete two's complement double precision product requires 2n/ clock cycles. This generalized architecture creates a continuum of multipliers between traditional bit-serial/parallel multipliers (=1) and fully-parallel multipliers (=n). -bit serial/parallel multipliers allow anoptimized integrated circuit arithmetic to be designed based on a particular application's area, power, throughput, latency, and numerical precision constraints.This project was pratically funded by the UCSD-NSF I/UCR Center on Ultra-High Speed Intergrated Circuits and Systems.     

A Continuous Time Auto-Zero Offset Compensated Switched Capacitor Integrator

A continous mode CMOS switched capacitor integrator with almost zero offset is presented. The offset is compensated using an auto-zero technique and proper circut elements have been used to attenuate disturbances due to charge injection and clock feedthrough. The circuit includes two parallel paths which operate alternately in order to integrate in one path while compensating the offset in the other path. The circuit is capable of removing the offset voltage and its integral, and many other spurious signals at the output. The designed integrator has an initial offset of about –250 V which raises to an amount of about –400 V after one second of integration.     

Low-Voltage Low-Power Integrated Phase-Shifter as Resistive Sensor Transducer

In this paper, we present a CMOSlow-voltage low-power phase shiftertopology, to be used as an integratedresistive sensor interface for portableapplications. The circuit furnishes an outputsquare wave whose time delay and shift arelinear with the value of the sensorresistance. Shifter non-idealities havebeen also considered. The circuit can be alsotransformed into an oscillator by a simpleterminal connection. In this case, theoscillation frequency is inverselyproportional to the same resistance. The proposed topology has been designed andfabricated in CMOS Mietec 0.5 technologyand can operate at supply voltages lowerthan 3 V. The minimum operating supplyvoltage is 1.2 V, the power consumptionbeing only 1 W for the shifter. Thecircuit shows good insensitivity to both thesupply voltage and temperature variations,so it can be applied as an alternativetopology for portable-system integratedinterfaces for typical resistive sensors ofM range.     

The dangers of simplistic delay models

The identification of sensitizable paths and the determination of path delays play key roles in many delay fault testing schemes. In this paper we examine a range of gate delay models with respect to their impact on identifying both sensitizable paths and maximum circuit delays in combinational logic circuits. We provide recommendations on the minimum acceptable model for identifying critical paths, and a minimum acceptable model for determining maximum circuit delays. In particular, we recommend against the use of delay models which fail to distinguish between rise and fall delays. Such models, including the commonly-used unit-delay model, are shown to significantly misrepresent circuit delay behaviour, particularly with respect to critical paths and long false paths.This research is supported by the Natural Sciences and Engineering Research Council of Canada.     

Low-Voltage Analog Circuits Based on Wideband Capacitive Coupling

A technique for wideband low-voltage analog circuit operation based on capacitive signal coupling is discussed. Circuits based on this technique do not show the GB degradation of other low-voltage approaches based on floating-gate transistors. The technique is validated with simulations of a new CMOS mixer and experimental results of a test chip in a 0.5 m CMOS technology.     

Factorizations in the elementary Abelian p-group and their cryptographic significance

Let G be a finite group and let A _i 1 i s, be subsets of G where ¦A _i ¦ 2, 1 i s and s 2. We say that (A₁, A₂,..., A₃) is a factorization of G if and only if for each g G there is exactly one way to express g = a ₁ a ₁ a ₂··· a ₃, where a _j A _i , 1 i s.The problem of finding factorizations of this type was first introduced by Hajos [3] in 1941. Since then a number of papers have appeared on the subject. More recently, Magliveras [6] has applied factorization of permutation groups to cryptography to obtain a private-key cryptosystem. Factorizations in the elementary abelian p-group were exploited (but not explicitly stated in these terms) by Webb [13] to produce a public-key cryptosystem conceptually similar to cryptosystems based on the knapsack problem.Using the result that certain types of factorizations in the elementary abelian p-group are necessarily transversal (a term introduced by Magliveras), this paper shows that the public-key system proposed by Webb is insecure.     

A CMOS Four Quadrant Current/Transconductance Multiplier

This paper describes a highly linear current four quadrant multiplier. The circuit is designed to operate in a fully differential way. It is based on the square-law characteristic of MOS transistors in saturation region. Experimental results for 2 m CMOS technology are provided.     

An Integrated Digital CMOS Time-to-Digital Converter with Sub-Gate-Delay Resolution

An integrated digital CMOS time-to-digital converter with sub-gate delay LSB width and 50 ps single-shot precision -value has been designed and implemented for a laser range-finding application. The measurement is based on a counter and a novel two-step parallel interpolation that uses only 32 delay elements to provide 128 LSBs in the interpolator within the reference clock cycle. The circuit was fabricated in the AMS 0.8 m CMOS process and the current consumption of the circuit is <20 mA from a single +5 V supply.