Implementing tactics and tacticals in a higher-order logic programming language

We argue that a logic programming language with a higher-order intuitionistic logic as its foundation can be used both to naturally specify and implement tactic-style theorem provers. The language extends traditional logic programming languages by replacing first-order terms with simply-typed -terms, replacing first-order unification with higher-order unification, and allowing implication and universal quantification in queries and the bodies of clauses. Inference rules for a variety of inference systems can be naturally specified in this language. The higher-order features of the language contribute to a concise specification of provisos concerning variable occurrences in formulas and the discharge of assumptions present in many inference systems. Tactics and tacticals, which provide a framework for high-level control over search for proofs, can be directly and naturally implemented in the extended language. This framework serves as a starting point for implementing theorem provers and proof systems that can integrate many diversified operations on formulas and proofs for a variety of logics. We present an extensive set of examples that have been implemented in the higher-order logic programming language Prolog.     

基于VMM方法学的系统级软硬件协同仿真验证

针对一款高性能复杂SoC芯片的设计,提出了一种新的软硬件协同仿真验证方案。通过比较仿真环境中软硬件间通信的各种实现方式,构建了一种新的符合VMM标准的验证平台。同时为加快覆盖率的收敛速度,给出了随机激励约束的优化方法。实践表明,新的约束和仿真方式使覆盖率收敛速度提高数倍,验证效率显著提高。     

Formal hardware verification methods: A survey

Growing advances in VLSI technology have led to an increased level of complexity in current hardware systems. Late detection of design errors typically results in higher costs due to the associated time delay as well as loss of production. Thus it is important that hardware designs be free of errors. Formal verification has become an increasingly important technique towards establishing the correctness of hardware designs. In this article we survey the research that has been done in this area, with an emphasis on more recent trends. We present a classification framework for the various methods, based on the forms of the specification, the implementation, and the proff method. This framework enables us to better highlight the relationships and interactions between seemingly different approaches.     

网络环境下计算机硬件的安全保障及维护策略

网络环境下计算机硬件面临新的安全问题,这需要提高对硬件安全保障及维护工作的重视度,提高计算机设备运行的安全质量。鉴于此,文章以网络环境为着手点,分析了硬件对计算机安全运行的影响及原理,总结了网络环境下计算机硬件面临的安全问题,并结合实际情况给出了做好硬件安全保障及维护的策略,希望进一步提高计算机设备运行的安全性。     

图形处理中投影变换的硬件设计与验证

描述了基于浮点处理单元的投影变换的硬件实现。以提高速度为设计目标,采用Verilog语言进行设计和实现,使用ISE进行逻辑综合,并用SystemVerilog进行建模验证。结果表明,本设计极大地提高了图形处理的速度。     

基于高阶逻辑的硬件验证方法

本文讨论了如何利用高阶逻辑描述硬件的行为及结构，提出了硬件验证的一般方法，高阶逻辑不仅可以作为一种描述语言用来描述硬件的行为及结构，而且可以作为证明系统用来验证硬件设计的正确性。文中给出的用以说明描述及验证的例子包括ＣＭＯＳ反相器、复位的奇偶校验器。     

局域网环境下如何做好硬件和网络安全维护工作

创造一个安全而稳定的互联网运行和发展环境是信息化时代对我们提出的一个新的要求。在局域网广泛应用于网络自动化办公、教育、信息交换的今天,其运行过程中的可靠性与稳定性开始引起人们的重视。本文就从硬件及网络安全维护这两方面入手,阐述如何更好地保障局域网的安全和稳定。     

Embedding and automating conditional logics in classical higher-order logic

A sound and complete embedding of conditional logics into classical higher-order logic is presented. This embedding enables the application of off-the-shelf higher-order automated theorem provers and model finders for reasoning within and about conditional logics.     

用高阶逻辑表达时态逻辑及其应用

硬件设计的形式化验证技术开辟了对复杂的超大规模集成电路设计进行验证的新途径。高阶逻辑和时态逻辑在形式化验证技术中均得到成功的应用。本文介绍用高阶逻辑表达线性时态逻辑和区间时态逻辑的方法，并以几个简单实例说明它在硬件设计验证中的应用。这种方法的优点是既利用高阶逻辑系统ＨＯＬ的机械化定理证明手段，又发挥了时态逻辑的表达硬件的动态性质的能力。     

A novel formal verification approach for RTL hardware IP cores

We present a promising formal verification methodology based on the inductive approach using the imPROVE-HDL tool. This methodology is dedicated for RTL IPs or IP-based digital/logic hardware designs to prove the correctness of their temporal properties related to the control-dominated architecture model. Each temporal property can be checked through the IP interface where all properties have to be proved or disproved. We developed a new methodology to generate the appropriate environment of the IP interface according to the design context (master, slave, arbiter and decoder) before starting the verification of all properties one by one. When all temporal properties are verified, we generate some test sequences that contain a complex scenario to check the compatibility between all properties. We implemented our methodology to generate the appropriate environment and applied the inductive approach to verify various properties of two real IP designs using the imPROVE-HDL tool developed by TNI-Valiosys. The first design is an RTL IP-based digital hardware dedicated for real time video processing, where the second one performs an AHB to AHB Bridge. On these designs, we successfully proved few properties and discovered a design violation.     

Combining and automating classical and non-classical logics in classical higher-order logics

Numerous classical and non-classical logics can be elegantly embedded in Church??s simple type theory, also known as classical higher-order logic. Examples include propositional and quantified multimodal logics, intuitionistic logics, logics for security, and logics for spatial reasoning. Furthermore, simple type theory is sufficiently expressive to model combinations of embedded logics and it has a well understood semantics. Off-the-shelf reasoning systems for simple type theory exist that can be uniformly employed for reasoning within and about embedded logics and logics combinations. In this article we focus on combinations of (quantified) epistemic and doxastic logics and study their application for modeling and automating the reasoning of rational agents. We present illustrating example problems and report on experiments with off-the-shelf higher-order automated theorem provers.     

Programs as proofs: a synopsis

Programs are like constructive proofs of their specifications. This analogy is a precise equivalence for certain classes of programs. The connection between formal logic and programs is a foundation for programming methodology superior to that usually adopted. Moreover this equivalence suggests programming languages which are far richer than all others currently in use. These claims are established in this paper introducing parts of the PL/CV programming logics as a source of precision and examples.     

An environment for formal verification based on symbolic computations

We present an environment for formally verifying hardware, based on symbolic computations. This includes a new concurrency model, called the combinational/sequential or C/S concurrency model which has close ties to hardware. We allow fairness constraints and describe methods for specifying them and for formally verifying in their presence. Properties are specified by either CTL formulae or edge-Rabin automata. We give algorithms, in the presence of fairness constraints, for model checking CTL or for checking that the language of our system is contained in the language of a property automation. Finally, techniques are given for hierarchical verification and for detecting errors quickly (early failure detection).     

Analog Circuit Verification: a State of an Art

Extending formal verification methodology toward analog circuits is a very challenging task that will occupy researchers for some time. To put this challenge in context we sketch some of the history of digital circuit verification as well as more recent attempts to adapt it to continnuous and hybrid systems.     

大型船舶操纵模拟器的硬件设计与应用

设计了大型船舶操纵模拟器操作台上常用的硬件设备,并对该硬件系统的总体架构以及设备的软硬件设计进行了详细介绍。该模拟器遵循STCW公约马尼拉修正案,满足中国海事局有关规定的性能标准,具有广泛的市场前景,并已投入到国内多家航海院校的教学培训中,取得了良好的效果。