A 16×16 nonvolatile programmable analog vector-matrixmultiplier

In this paper, we present a 16×16 analog vector-matrix multiplier with analog electrically erasable and programmable read-only memories (EEPROMs) used as nonvolatile storage for the weight matrix values. Each weight matrix value is stored in an EEPROM transistor as a change of the threshold voltage, and the same EEPROM transistor is used for the multiplication by utilizing the square-law characteristic of the metal-oxide-semiconductor field-effect transistor. This allows a very simple circuit for the multiplier array with a size of about 1×1 mm². The vector-matrix multiplier has been fabricated in a 1,5-μm single-poly complementary metal-oxide-semiconductor/EEPROM technology and successfully tested     

A nonvolatile analog programmable voltage source using the VIPMOSEEPROM structure

A programmable voltage source using the vertical injection punchthrough based MOS (VIPMOS) EEPROM structure is presented. The circuit operates at a single 5-V supply and the output voltage is continuously available even during programming. The effect of programming is linearly dependent on the programming time. During programming no crosstalk from the enable pulses and only a little crosstalk from the program current are observed. If a decreasing program current is used, the output of the circuit can be set to its desired value without the need of an iterative program process     

An SRAM cell with nonvolatile memory for programmable logicapplications

A memory cell has been developed and fabricated that during normal operation acts as an SRAM cell. The state of the cell can be “saved,” and at power up, the cell can be put back into that state     

Voltage-readable nonvolatile memory cell with programmable ferroelectric multistates in organic inverter configuration

We demonstrate a voltage-readable nonvolatile memory cell with programmable ferroelectric multistates in an organic inverter configuration. The intermediate memory states of a ferroelectric gate insulator, varying with the magnitude of the programming voltage, allow the multilevels of the drain current at zero gate-source voltage in a ferroelectric organic field-effect transistor (OFET). The current output from the ferroelectric memory is directly converted into the voltage-readable output in a zero-gate load inverter configuration where both a driving paraelectric OFET having a paraelectric buffer layer and a load ferroelectric OFET are monolithically integrated in a single substrate. The multilevel voltage-readable output characteristics are obtained from the ferroelectric multistates as a function of the programming voltage.     

Power IC with EEPROM programmable switch mode regulators

A power IC is described with an EEPROM programmable trim for precision regulation of two switch-mode regulators and a high accuracy oscillator. In-the-package voltage adjustment to 1% and an oscillator trim of 1.5% are achieved with the internal trim capability. The IC also features an “H” bridge for DC motor control and eight low-side drivers for driving unipolar stepper motors. A modified 44 pin plastic leaded chip carrier gives 30°C/W performance     

Optical switch emulation in programmable software router testbed

A programmable optical router is a key enabler for dynamic service provisioning in Future Internet scenarios. It is equipped with optical switching hardware to forward information at hundreds of Gigabits/s rates and above, controlled and managed through modular and flexible procedures according to emerging standards. The possibility to test such costly optical architectures in terms of logical and physical performance, without implementing complex and expensive testbeds, is crucial to speed-up the development process of high-performance routers. To this purpose, this paper introduces the software-based emulation testbed of a programmable optical router, which is here developed and applied to test optical switching fabrics. Accurate characterization of the optical devices and physical layer aspects is implemented with the Click software router environment. Power loss and optical signal-to-noise-ratio evaluation are provided through accurate software representation of the physical characteristics of the optical devices employed. The scalability of the proposed emulation testbed is also assessed on standard PC hardware. All the obtained results prove the effectiveness of the proposed tool to emulate an optical router at different levels of granularity.     

智能存储交换机中的高速可编程数据通道处理

概述 我们正经历着包括电信、互联网和企业环境在内的数字世界的大融合。这种融合的复杂性决定了在实现通信通用的标准协议或方式之前还有很多事情需要处理。例如,在存储网络方面,各个公司都正在探索新一代的智能存储网络交换机,它把存储区域网络（SAN）和网络附属存储（NAS）的功能和优势     

MEMS开关宽频程控步进衰减器设计与实现

提出了一种基于MEMS开关的射频衰减器设计方案。首先对整体电路的基础结构进行了设计,选择以CPW（共面波导）为传输线,接触式MEMS开关作控制器件,同时以开关中的电容作为断路时的平衡电容进行Q值匹配;其次,通过理论推导与计算得到了波导的截面尺寸;然后按所需衰减量计算T型网络各个电阻的阻值大小。再按照计算值在CST微波工作室中建模仿真,对比单级衰减和展频二级衰减的S参数,可以发现,在Q值匹配后的电路中,射频信号可以在更宽的频段内保持稳定衰减。最后通过UV-LIGA技术结合氧化钽电阻工艺对衰减器进行了样片试制与结果测试。结果表明,通过Q值匹配可以扩展衰减器的工作频段,为高频信号的稳定衰减提出了一种可行性方案。     

可编程无线电遥控多路开关系统设计

设计了一种新的可编程无线电遥控多路开关系统。该系统以Si4010为核心发射单元,以Si4313和C8051F920单片机为核心接收控制单元,实现对多路开关的无线电遥控。详细阐述了系统的工作原理,给出了硬件电路及软件流程图,并对其进行了实验验证。结果证明,该设计成本低、体积小、功耗低,同时具有抗干扰能力强、遥控距离远、可靠性高等特点。     

Low-voltage programmable/erasable high performance flexible organic transistor nonvolatile memory based on a tetratetracontane passivated ferroelectric terpolymer

Future flexible electronic systems require memory devices combining low power consumption and mechanical bendability. However, high programming/erasing (P/E) voltages, which are universally required to switch the storage states in previously reported ferroelectric organic field-effect transistor (Fe-OFET) nonvolatile memories (NVMs), severely prevent their practical applications. In this work, we develop a novel route to achieve a low-voltage programmable/erasable flexible Fe-OFET NVM. Ferroelectric terpolymer poly(vinylidene-fluoride-trifluoroethylene-chlorotrifluoroethylene) [P(VDF-TrFE-CTFE)], rather than the conventional ferroelectric copolymer poly(vinylidene-fluoride-trifluoroethylene) [P(VDF-TrFE)], is used as the gate dielectric. The low coercive field of P(VDF-TrFE-CTFE) is the main contribution to the low-voltage operation in the Fe-OFET NVM, even with a relative thick ferroelectric gate dielectric layer. By depositing a long-chain alkane molecule Tetratetracontane (TTC) as the passivation layer on the surface of P(VDF-TrFE-CTFE) film, the layer-by-layer growth mode of semiconductor pentacene is obtained, which results in a large crystalline grain and good interface morphology at the channel/dielectric. Therefore, the mobility of Fe-OFET NVMs is greatly improved. As a result, a high performance flexible Fe-OFET NVM is achieved, with a low P/E voltage of ±15 V, high mobility up to 0.5 cm² V⁻¹ s⁻¹, reliable P/E endurance property over 1000 cycles, stable data storage retention capability over 6000 s, and excellent mechanical bending durability without visible degradation after 2000 repetitive tensile bending cycles at a small curvature radius of 4.0 mm.     

A nonvolatile memory circuit-a novel approach

A nonvolatile memory circuit using conventionally available components (transistors and magnetic switching cores) operates on the principle of the two distinct impedance levels of a switching core in the irreversible and reversible regions. It has the property of nondestructive read-out and requires no sensing amplifiers. It is believed that the circuit is useful for systems that require low memory capacity, such as from a few bits to a hundred of bits of information.     

A programmable artificial retina

An artificial retina is a device that intimately associates an imager with processing facilities on a monolithic circuit. Yet, except for simple environments and applications, analog hardware will not suffice to process and compact the raw image flow from the photosensitive array. To solve this output problem, an on-chip array of bare Boolean processors with halftoning facilities is proposed, with versatility provided by programmability. For a pixel memory size of 3 b, the authors demonstrate both the technological practicality and the computational efficiency of this programmable Boolean retina concept. Using semistatic shifting structures together with some interaction circuitry, a minimal retina Boolean processor can be built with less than 30 transistors and controlled by as few as six global clock signals. The successful design, integration, and test of a 65×76 Boolean retina on a 50-mm² CMOS 2-μm circuit are described     

A new phase in nonvolatile memory?

This paper describes recent advances in techniques to develop phase-change memories. These include a new way to facilitate low-voltage phase changes with the use of a tiny strip of amorphous semiconductor compound of germanium, antimony, and tellurium on a layer of silicon dioxide, which is connected to lateral contacts connected to current sources. This configuration allows better control of heat dissipation and use of smaller voltages to change phase. Another development is a device made with a phase-change material based on antimony-tellurium material doped with one or more of the elements of germanium, indium, silver or gallium. This doped material changes phase significantly faster than the germanium-antimony-tellurium compounds in other experiments. Efforts are also underway to create arrays containing memory cells.     

A 16-kbit nonvolatile charge addressed memory

A 16-kbit nonvolatile charge addressed memory (NOVCAM) is described. A unique cell design allows a high-density memory array layout without reduced line widths or spacings. A cell size of 0.5 square mils is produced by a seven mask process with 6-/spl mu/m polysilicon gates, 10-/spl mu/m aluminum gates, and 10-/spl mu/m minimum spacing on all mask levels. Charge addressed write and read operations are implemented with a very simple interface between the memory array and a two-phase dynamic shift register. The memory is organized as 256 columns by 64 rows. Two 64-bit shift registers provide data access to the memory array via a 2:1 column decoder. With single polysilicon processing the memory array is 50/spl times/161 mils; the 16-kbit chip is 131/spl times/200 mils.     

固体电解质双功能气体传感器的研制

以sol-gel法合成的NASICON为基体导电层材料,以掺杂C的Cr2O3和ZnO-TiO2分别作为对氨和甲苯敏感的电极材料,制备了一种能同时检测氨和甲苯的新型管式结构固体电解质双功能气体传感器。当工作温度为250~400℃时,传感器对浓度为(50~500)×10–6的氨和(5~50)×10–6的甲苯具有较好的气敏性能,其电动势E值与氨和甲苯浓度的对数呈线性关系,在350℃时,对氨和甲苯的灵敏度分别为–91mV/decade和–60mV/decade。并有较快的响应恢复时间和较好的选择性。     

A programmable architecture for OFDM-CDMA

Combining multicarrier (OFDM) and CDMA technologies is attractive for future wireless broadband communications and software radio realization. Based on the unified framework known as OFCDMA, we develop a programmable structure for OFDM-CDMA transceivers in spite of three different scenarios to combine OFDM and CDMA. By adjusting system parameters without changing the fundamental hardware and software architecture, various system scenarios can be implemented, which might serve as the foundation to design software radio     

A multiple-state micro-mechanical programmable memory

This paper reports a multiple-state micro-mechanical memory. The tip displacements of a 350 μm long VO₂-coated micro-mechanical silicon cantilever were programmed to absolute displacements ranging from −19 to −7 m. Ten non-uniform mechanical states were programmed using controlled linearly increasing laser pulses. The uniformity of the mechanical states was improved by using non-linearly increasing laser pulses. The programmed states are reset by driving the VO₂ outside the hysteretic region.     

A CCD programmable signal processor

A generic large-coupled device (CCD) signal processor that performs 2.8-billion computations per second with a 10-MHz clock rate is described. The device's concept, design, operation, performance, and applications are reviewed. A dynamic range greater than 42 dB has been demonstrated by the device. This processor can be used as a one-dimensional correlator, a two-dimensional matched filter or a two-layer neural net device. The device demonstrates the flexibility and computational power that is possible using CCD technology     

A real-time programmable switched-capacitor filter

Four independent real-time programmable switched-capacitor filters have been fabricated on a single NMOS chip. The filters are second-order sections with digitally programmable Q and center frequency. Either low-pass or bandpass functions are available by selecting the appropriate input. The device is microprocessor compatible and includes permanent programming capability as well as an on-chip oscillator. The circuit implementation, programming capability, and operation are described.