新世纪电子器件封装技术展望

扼要分析了电子器件封装技术迅速发展的成因，预测了电子封装新技术的发展方向，深入阐述了引脚布置方式的突破，BGA技术的发展，BGA和倒装芯片结合的优势，CSP产业化的关键，在晶圆片上进行CSP封装的新工艺，以及倒装芯片和CSP封装的综合比校。     

微波芯片倒装金凸点热疲劳可靠性分析及优化

为了满足射频系统小型化的需求,提出了一种基于硅基板的微波芯片倒装封装结构,解决了微波芯片倒装背金接地的问题.使用球栅阵列(BGA)封装分布为周边型排列的GaAs微波芯片建立了三维有限元封装模型,研究了微波芯片倒装封装结构在-55～125℃热循环加载下金凸点上的等效总应变分布规律,同时研究了封装尺寸因素对于金凸点可靠性的影响.通过正交试验设计,研究了凸点高度、凸点直径以及焊料片厚度对凸点可靠性的影响程度.结果表明:金凸点离芯片中心越近,其可靠性越差.上述各结构尺寸因素对凸点可靠性影响程度的主次顺序为:焊料片厚度＞金凸点直径＞金凸点高度.因此,在进行微波芯片倒装封装结构设计时,应尽可能选择较薄的共晶焊料片来保证金凸点的热疲劳可靠性.     

电子器件封装工艺技术新进展

该文扼要分析了电子器件封装技术迅速发展的成因，预测了电子封装新技术的发展方向，深入阐述了引脚布置方式的突破，BGA技术的发展，GBA和倒装芯片结合的优势，CSP产业化的关键，在晶圆片上进行CSP封装的新工艺，以及倒装芯片和CSP封装的综合比较。     

Ultra CSP晶片级封装

取得专利的低成本小型封装随着市场对更小、更快和不太昂贵器件需要的增长，工业上正在寻找一种使产品从导线焊接封装转到直接进行芯片连接（DCA）的解决方案。在近几年间，芯片大小的封装（CSP）已经显现出在球栅阵列（BGA）和倒装片的空隙之间架起的桥梁。由于许多设计预先考虑向DCA转移，所以已经把倒装片引入到他们的CSP或BGA封装里了。Kulicke＆Soffa工业股份有限公司的K＆S倒装片分部已经超出了传统的封装和CSP封装的范围，而转到向Ultra CSP技术发展。这种UltraCSP技术是一种晶片级（Wafer Level）CSP方案，是利用一…     

BGA封装技术

本文简述了BGA封装产品的特点、结构以及一些BGA产品的封装工艺流程,对BGA封装中芯片和基板两种互连方法——引线键合/倒装焊键合进行了比较以及对几种常规BGA封装的成本/性能的比较,并介绍了BGA产品的可靠性。另外,还对开发我国BGA封装技术提出了建议。     

BGA／CSP和倒装焊芯片面积阵列封装技术

随着表面安装技术的迅速发展,新的封装技术不断出现,面积阵列封装技术成了现代封装的热门话题,而BGA／CSP和倒装焊芯片（F1iPChip）是面积阵列封装主流类型。BGA／CSP和倒装焊芯片的出现,适应了表面安装技术的需要,解决了高密度、高性能、多功能及高I／O数应用的封装难题。本文介绍了BGA／CSP和倒装焊芯片的封装理论和技术优势及制造流程,并阐述了植球机的基本构成和工作原理。     

高密度封装技术现状及发展趋势

综述了对半导体集成电路发展有深刻影响的微电子封装技术的现状 ,指出了适用于高密度封装的载带封装 (TCP)、球栅阵列封装 (BGA)、倒装片 (FCT)、芯片规模封装 (CSP)、多芯片组件 (MCM)、三维封装等关键技术及其发展趋势     

CSP组装底部填充工艺

CSP即芯片规模封装,是在BGA的基础上进一步缩小了封装尺寸。CSP可提供裸芯片与倒装芯片的性能与小型的优势,可设计成比芯片模面积或周长大1.2～1.5倍的封装。并为回流焊装配工艺提供与线路印刷板焊盘冶金兼容的锡球和引脚。 CSP比QFP和BGA提供了更短的互连,改善了电气性能和热性能,提高了可     

一种基于倒装芯片的超宽带BGA封装差分传输结构

随着高速数字电路和射频微波电路对时钟频率和带宽的要求越来越高，差分传输结构因其优良的噪声抑制和抗干扰性能而受到越来越多的重视。提出了一种基于倒装芯片的超宽带球栅阵列(BGA)封装差分传输结构。整体传输结构包括采用陶瓷材料制作的倒装芯片用基板、BGA封装焊球和印制电路板(PCB)。主要分析了差分垂直传输结构的尺寸参数对阻抗和截止频率的影响，并利用阶梯过孔减小阻抗不连续性。整体结构的传输性能通过矢量网络分析仪测试的散射参数来表征。测试与仿真结果具有较好的一致性，在DC～60 GHz频段，差分传输结构的回波损耗≤-15 dB,插入损耗优于-1 dB,为超宽带倒装芯片的封装设计提供参考。     

底部填充技术的SMT应用研究

如BGA、CSP等倒装芯片的SMT应用越来越普遍,底部填充胶水可以有效提高倒装芯片焊点的机械强度,以避免因热循环应力疲劳或机械冲击力而产生的失效。本文详细描述了底部填充技术的SMT应用细节,包括底部填充胶水介绍、PCB DFM设计、涂胶前准备、涂胶过程和注意事项、涂胶设备介绍等。     

Exposed Die-Top Encapsulation Molding for an Improved High- Performance Flip Chip BGA Package

The recent advancement in high- performance semiconductor packages has been driven by the need for higher pin count and superior heat dissipation. A one-piece cavity lid flip chip ball grid array (BGA) package with high pin count and targeted reliability has emerged as a popular choice. The flip chip technology can accommodate an I/O count of more than five hundreds500, and the die junction temperature can be reduced to a minimum level by a metal heat spreader attachment. None the less, greater expectations on these high-performance packages arose such as better substrate real estate utilization for multiple chips, ease in handling for thinner core substrates, and improved board- level solder joint reliability. A new design of the flip chip BGA package has been looked into for meeting such requirements. By encapsulating the flip chip with molding compound leaving the die top exposed, a planar top surface can be formed. A, and a flat lid can then be mounted on the planar mold/die top surface. In this manner the direct interaction of the metal lid with the substrate can be removed. The new package is thus less rigid under thermal loading and solder joint reliability enhancement is expected. This paper discusses the process development of the new package and its advantages for improved solder joint fatigue life, and being a multichip package and thin core substrate options. Finite-element simulations have been employed for the study of its structural integrity, thermal, and electrical performances. Detailed package and board-level reliability test results will also be reported     

A novel approach for flip chip solder joint quality inspection:laser ultrasound and interferometric system

A novel, noncontact, nondestructive approach for flip chip solder joint quality inspection is presented. In this technique, a pulsed laser generates ultrasound on the chip's surface, exciting the whole chip into a vibration motion. An interferometer was used to measure the vibration displacement of the chip's surface. Because changes in solder joint quality produce a different vibration response, a value, "error ratio," is used to measure the difference between a good chip and a chip with defects. An automatic signal-processing algorithm to calculate the error ratio was developed and implemented, as well as a frequency analysis algorithm. The inspection system was characterized, and results are presented for two cases of flip chips with missing solder balls. Results indicate that a laser ultrasonic/interferometeric system offers great promise for solder bump inspection in flip chip, BGA, chip scale, and micro BGA packages     

Low cost bumping by stencil printing: process qualification for 200 μm pitch

Area array packages (flip chip, CSP (Chip scale packages) and BGA) require the formation of bumps for the board assembly. Since the established bumping methods need expensive equipment and/or are limited by the throughput, minimal pitch and yield, the industry is currently searching for new and lower cost bumping approaches. The experimental work of stencil printing to create solder bumps for flip chip devices is described in detail in this article. In the first part of this article, a low cost wafer bumping process for flip chip applications will be studied in particular. The process is based on an electroless nickel under bump metallization and solder bumping by stencil printing. The experimental results for this technology will be presented, and the limits concerning pitch, stencil design, reproducibility and bump height will be discussed in detail. In the second part, a comparison of measured standard deviations of bump heights as well as the quality demands for ultrafine pitch flip chip assembly are shown.     

Die stress characterization in flip chip on laminate assemblies

Minimizing device side die stresses is especially important when multiple copper/low-k interconnect redistribution layers are present. Mechanical stress distributions in packaged silicon die resulting during assembly or environmental testing can be accurately characterized using test chips incorporating integral piezoresistive sensors. In this paper, measurements of thermally induced stresses in flip chip on laminate assemblies are presented. Transient die stress measurements have been made during underfill cure, and the room temperature die stresses in final cured assemblies have been compared for several different underfill encapsulants. In addition, stress variations have been monitored in the assembled flip chip die as the test boards were subjected to slow temperature changes from -40 to +150/spl deg/C. Using these measurements and ongoing numerical simulations, valuable insight has been gained on the effects of assembly variables and underfill material properties on the reliability of flip chip packages.     

Growth prediction of tin/copper intermetallics formed between 63/37 Sn/Pb and OSP coated copper solder pads for a flip chip application

This study quantifies the effect of temperature and time on the growth of Cu-Sn intermetallics, specifically for flip chip/ball grid array packaging technology. The activation energy and the growth rates were determined for solid state diffusion, after the initial assembly reflow(s). Three different types of solder joints were investigated. 1) BGA 63/37 solder joints which were formed by a standard convection oven attach of 30 mil (760 /spl mu/m)diameter solder spheres to OSP protected, Cu plated ball pads of an organic flip chip substrate. The ball pads are solder mask defined and of 0.635 mm nominal diameter. 2) Flip chip bump pad solder joint consisting of 63/37 eutectic solder bumped die attached to a nonsolder mask defined, OSP protected, Cu plated pad of the flip chip substrate. The flip chip bumps on the die are created by screen printing solder paste on the die pads and subsequent reflow attach, by a standard convection oven to the die under bump metallurgy (UBM). The nominal die UBM pad diameter is 0.085 mm. 3) Solder joint formed on a coupon which involved the reflow of the balls randomly placed on a Cu plated layer with no solder mask coating. The investigation was performed by first establishing the intermetallic growth rate at six different temperatures, ranging from 85/spl deg/C to 150/spl deg/C. The relationship between intermetallic growth and time was shown to essentially follow the common parabolic diffusion relationship to temperature especially above 100/spl deg/C. The activation energy (E/sub a/) and the growth constant (k/sub 0/) were then calculated from this data. The results showed that the E. for the total intermetallic thickness was essentially similar for the three solder joint configurations of the ball, bump and the coupon described above. E. varied from 0.31 eV to 0.32 eV, while the k/sub 0/ varied from 18.0 /spl mu/m/s/sup 1/2 / to 24.2 /spl mu/m/s/sup 1/2 /.     

对表面贴装设备带来影响的BGA器件

BGA技术的出现给制造业带来了压力,迫使人们要用一种新的眼光来寻找装配工艺方法。为了能够满足产品小型化的要求,能够降低引脚针间距的芯片规模封装和倒装芯片技术,将永无止境地向前发展,精确贴装的能力将继续是一个非常重要的因素。     

Measurement of water absorption in ball grid array package

The plastic ball grid array (BGA) package has poor resistance to popcorn cracking, which occurs when high temperatures involved in soldering cause water vapor to expand rapidly. Popcorn cracking occurs at die attach paste, and therefore water absorption and desorption occurring in the vicinity of die attach paste must be studied. We examine the mechanism of popcorn cracking in a BGA, particularly from the aspect of water absorption distribution. Water absorption was simulated by use of deuterium oxide, because the absorption performance of deuterium oxide approximates that of water. Deuterium oxide absorption distribution was measured by time of flight secondary ion mass spectroscopy (ToF-SIMS). We found that the water is absorbed mainly through the upper side of molded portion of the BGA package, and that absorption through the substrate is small. A BGA substrate has a laminated structure, and therefore water cannot penetrate the substrate first. On the basis of the results obtained in our study, we designed a BGA package system that is not prone to popcorn cracking     

Bump formation for flip chip and CSP by solder paste printing

Area array packages (flip chip, CSP and BGA) require the formation of bumps for the board assembly. Since the established bumping methods need expensive equipment or are limited by the throughput, minimal pitch and yield the industry is currently searching for new and lower cost bumping approaches. In this paper the experimental work of stencil printing to create solder bumps for flip chip and wafer level CSP (CSP-WL) is described in detail.This paper is divided into two parts. In the first part of the paper a low cost wafer bumping process for flip chip applications will be studied in particular. The process is based on an electroless Nickel under bump metallization and solder bumping by stencil printing. The experimental results for this technology will be presented and the limits concerning pitch, reproducibility and bump height will be discussed in detail. The second part of the paper is focused on solder paste printing for wafer-level CSPs. In order to achieve large bumps an optimized printing method will be presented. Additionally advanced stencil design will be shown and the achieved results will be compared with conventional methods.