Sensing behavior and mechanism of titanium dioxide-based MOS hydrogen sensor

A Pd/TiO₂/Si MOS sensor (Pdtisin sensor) is proposed for the detection of hydrogen gas. The sensor is fabricated on a p-type 1 1 1 silicon wafer having resistivity of 3–6 Ω cm. The thickness of TiO₂ in this structure is about 600 nm. The capacitance–voltage (C–V) and conductance–voltage (G–V) characteristics of the device is observed on the exposure of hydrogen gas at room temperature. The mechanism of hydrogen sensing of titanium dioxide-based MOS sensor (MOS capacitor) has been investigated by evaluating the change in flat-band voltage (V_FB) and fixed surface state density of the device in presence of hydrogen gas. The device exhibits very large parallel shift in C–V as well in G–V characteristics. The possible mechanism on Pd/TiO₂ and TiO₂/Si surface in presence of hydrogen gas has been proposed. The response and recovery time of the device is also measured at room temperature.     

Interface characteristics of Ge3N4-(n-type) GaAs MIS devices

Passivation of GaAs surfaces was achieved by the deposition of Ge₃N₄ dielectric films at low temperatures. Electrical characteristics of MIS devices were measured to determine the interface parameters. From C-V-f and G-V-f measurements, density of interface states has been obtained as (4–6)×10¹¹ cm⁻² eV⁻¹ at the semiconductor mid-gap. Some inversion charge buildup was seen in the C-V plot although the strong inversion regime is absent. Thermally stimulated current measurements indicate a trap density of 5×10¹⁸−10¹⁹ cm⁻³ in the dielectric film, with their energy level at 0.59 eV.     

Optoelectronic properties of Zn0.52Se0.48/Si Schottky diodes

Zn_0.52Se_0.48/Si Schottky diodes are fabricated by depositing zinc selenide (Zn_0.52Se_0.48) thin films onto Si(1 0 0) substrates by vacuum evaporation technique. Rutherford backscattering spectrometry (RBS) analysis shows that the deposited films are nearly stoichiometric in nature. X-ray diffractogram of the films reveals the preferential orientation of the films along (1 1 1) direction. Structural parameters such as crystallite size (D), dislocation density (δ), strain (ε), and the lattice parameter are calculated as 29.13 nm, 1.187 × 10⁻¹⁵ lin/m², 1.354 × 10⁻³ lin⁻² m⁻⁴ and 5.676 × 10⁻¹⁰ m respectively. From the I–V measurements on the Zn_0.52Se_0.48/p-Si Schottky diodes, ideality and diode rectification factors are evaluated, as 1.749 (305 K) and 1.04 × 10⁴ (305 K) respectively. The built-in potential, effective carrier concentration (N_A) and barrier height were also evaluated from C–V measurement, which are found to be 1.02 V, 5.907 × 10¹⁵ cm⁻³ and 1.359 eV respectively.     

Frequency dependence of of MOS capacitors

The frequency dependence of ΔV/Δ(C⁻²) of an MOS capacitor, which plays an important role in determining the semiconductor doping profile, is studied theoretically and experimentally. Useful expressions relating the measurable quantities to the doping profile are derived systematically. It is shown how interface states and majority carriers influence the frequency dependence of ΔV/Δ(C⁻²) and give rise to errors in profile determinations. The techniques of measuring the various types of the frequency dependence of ΔV/Δ(C⁻²) are also described.     

On the effect of non-degenerate doping of polysilicon gate in thin oxide MOS-devices—Analytical modeling

A one-dimensional model of the polysilicon-gate-oxide-bulk structure is presented in order to analyze the implanted gate MOS-devices. The influence of the ionized impurity concentration in the polysilicon-gate near the oxide and the charge at the polysilicon-oxide interface on the flat-band voltage, threshold voltage, inversion layer charge and the quasi-static C–V characteristic is quantitatively studied. The calculations show a considerable degradation of the inversion layer charge due to the voltage drop in the gate, especially in thin oxide devices. The calculated quasi-static C–V curves agree with the recently published data of implanted gate devices.     

C-t analysis of MOS capacitors under constant current stress

The effect of high oxide field stress is studied using capacitance-time (C-t) measurements of MOS capacitors. The stress results in parallel shifts of the C-t curve along the time axis. The flatband voltage shift ΔV_FB obtained from the initial deep depletion capacitance C(t=0⁺) follows the same trend as that from the high-frequency C-V characteristics. However, the discrepancy between the two flatband voltages becomes larger as the stress increases due to the effect of interface charges on C-t characteristics. The flatband voltage difference is converted to interface trap density, showing a steady increase of interface trap density with stress, similar to that from low-frequency C-V measurements     

A silicon flexode an adaptive p−n junction device

The lithium flexode, a p−n junction device whose I–V characteristic is reversibly adjustable and which heretofore has been made only with germanium, has now been made with silicon. The silicon flexode was batch fabricated by doping a silicon wafer with lithium to about 8 × 10¹⁷ atoms/cm³ and then forming a shallow p−n alloy junction using aluminum.

Experimentally, the silicon flexode was evaluated primarily as a bistable switch operating between a rectifying or diode-state (D) and a conducting-state (C)). Electrical signals only (with their attendant Joulean heating) were used to obtain I–V adjustment. The largest change in back resistance obtained in the silicon flexode was about five orders of magnitude. Switching from the D- to C-states ordinarily took about 1 sec. However, the inverse C to D switching process required the input of substantial power (about 1 W) and usually took several minutes, although a switching time as low as 20 sec was measured. In addition, it was found that the silicon flexode can be switched in either direction to intermediate states which remain stable at room-temperature.

Lithium precipitation, after cooling from the diffusion temperature, was not observed in our experiments with both quartz-crucible and floating-zone silicon. This is at variance with previously published findings. The difference is probably related to an effect, perhaps lattice strain, introduced by our diffusion technique.     

A novel linearly tunable butterfly-shape MEMS capacitor

A new MEMS tunable capacitor with linear capacitance–voltage (C–V) response is introduced. The design is developed based on a parallel-plate configuration and uses the structural lumped flexibility and geometry optimization to obtain a linear response. The moving electrode is divided into two segments connected to one another by a torsional spring. There are extra beams located between the two plates, which constrain the displacement of the moving plate. The resulting nonlinear structural rigidity provides the design with higher tunability than the parallel-plate ones. Furthermore, because the plate's displacement is controlled, the shape of C–V curve changes in such a way that high linearity is achieved. The proposed design can be fabricated by a three-structural-layer process such as PolyMUMPs. The results of analytical solution and experimental measurements verify that the new capacitor can produce tunability of over 100% with high linearity. The introduced design methodology can further be extended to flexible plates and beams to obtain smooth C–V curves.     

Electrical properties of high permittivity ZrO2 gate dielectrics on strained-Si

Deposition and electrical properties of high dielectric constant (high-k) ultrathin ZrO₂ films on tensilely strained silicon (strained-Si) substrate are reported. ZrO₂ thin films have been deposited using a microwave plasma enhanced chemical vapor deposition technique at a low temperature (150 °C). Metal insulator semiconductor (MIS) structures are used for high frequency capacitance–voltage (C–V), current–voltage (I–V), and conductance–voltage (G–V) characterization. Using MIS capacitor structures, the reliability and the leakage current characteristics have been studied both at room and high temperature. Schottky conduction mechanism is found to dominate the current conduction at a high temperature. Observed good electrical and reliability properties suggest the suitability of deposited ZrO₂ thin films as an alternative as gate dielectrics. Compatibility of ZrO₂ as a gate dielectric on strained-Si is shown.     

High quality SiO2/Si interfaces of poly-crystallinesilicon thin film transistors by annealing in wet atmosphere

A new post-metallization annealing technique was developed to improve the quality of metal-oxide-semiconductor (MOS) devices using SiO ₂ films formed by a parallel-plate remote plasma chemical vapor deposition as gate insulators. The quality of the interface between SiO₂ and crystalline Si was investigated by capacitance-voltage (C-V) measurements. An H₂O vapor annealing at 270°C for 30 min efficiently decreased the interface trap density to 2.0×10¹⁰ cm^-2 eV^-1, and the effective oxide charge density from 1×10 ¹² to 5×10⁹ cm^-2. This annealing process was also applied to the fabrication of Al-gate polycrystalline silicon thin film transistors (poly-Si TFT's) at 270°C. In p-channel poly-Si TFT's, the carrier mobility increased from 60-400 cm² V^-1 s^-1 and the threshold voltage decreased from -5.5 to -1.7 V     

New aspects and mechanism of kink effect in static back-gatetransconductance characteristics in fully-depleted SOI MOSFETs onhigh-dose SIMOX wafers

An extraordinary kink phenomenon in static back-gate transconductance characteristics of fully-depleted SOI MOSFETs has been experimentally investigated and characterized for the first time. This kink phenomenon has been observed in both NMOS and PMOS on high-dose SIMOX wafers under steady-state conditions at room temperature. It was also found that the back-gate characteristics for both NMOS and PMOS show anomalous shift phenomenon in drain current-back gate voltage (I _D-V_G2) curve at the back-gate voltage corresponding to the kink phenomenon. This kink phenomenon has been attributed to the presence of energetically-localized trap states at SOI/BOX interface. In order to clarify the energy level of the trap states at SOI/BOX interface corresponding to the kink, we have developed a new formula of surface potential in thin-film SOI MOS devices, in which the potential drop across semiconductor-substrate is taken into account. By using this new formula, me have demonstrated that high-dose SIMOX wafers have donor-like electron trap states at ~0.33 eV above the Si midgap with the density of ~N6.0~10¹² cm^-2 eV ^-1 and donor-like hole trap states at ~0.35 eV below the Si midgap with density of ~1.5×10¹² cm^-2 eV^-1 at SOI/BOX interface     

Profiling interface traps in MOS transistors by the DCcurrent-voltage method

Position profiling the interface trap density along the channel length of metal-oxide-silicon transistors by the Direct-Current Current-Voltage method is illustrated for five density variations: zero, peaked in drain junction space-charge layer, constant in channel, nonconstant in channel, and peaked in drain junction space-charge layer and nonconstant in channel. The interface trap densities were monitored by MOS transistor's d.c. body current and the density profiles were obtained from the body-drain and body-source differential conductance versus drain or source bias voltage. An experimental demonstration is given for a 1.6 μm n-channel Si MOS transistor with about 10¹¹ traps/cm² generated by channel hot electron stress     

A complete analytical model of GaN MESFET for microwave frequency applications

A simple physics-based analytical model for a non-self-aligned GaN MESFET suitable for microwave frequency applications is presented. The model includes the effect of parasitic source/drain resistances and the gate length modulation. The model is then extended to evaluate I–V and C–V characteristics, transconductance, cut-off frequency, transit time, RC time constant, optimum noise figure and maximum power density. The transconductance of about 21 mS/mm is obtained for GaN MESFET using the present theory in comparison to 23 mS/mm of the reported data. The cut-off frequency of more than 1 GHz, optimum noise figure of 6 dB and maximum output power density of more than 1 W/mm are predicted.     

Noise studies in internal field emission diodes

The breakdown process of a zener diode in reverse direction is governed by internal field emission at low voltage and by impact ionization at higher voltage. For breakdown voltage in the transition range between 3 and 6 V, both physical processes appear in combination. Measuring the I–V characteristic and the noise current fluctuations spectral density it is possible to show the zener current multiplication by the multiplication effect described by Tager. In addition the I–V characteristic can be written empirically I = Vⁿ.     

Density of States-Based DC $I$– $V$ Model of Amorphous Gallium–Indium–Zinc-Oxide Thin-Film Transistors

The density of states (DOS)-based DC I-V model of an amorphous gallium-indium-zinc oxide (a-GIZO) thin-film transistor (TFT) is proposed and demonstrated with self-consistent methodologies for extracting parameters. By combining the optical charge-pumping technique and the nonlinear relation between the surface potential (phiS) and gate voltage (V _GS), it is verified that the proposed DC model reproduces well both the measured V _GS-dependent mobility and the I _DS-V _GS characteristics. Finally, the extracted DOS parameters are N _TA = 4.4 times 10¹⁷ cm^-3 middot eV^-1, N _DA = 3 times 10¹⁵ cm^-3 middot eV^-1, kT _TA = 0.023 eV, kT _DGA = 1.5 eV, and EO = 1.8 eV, with the formulas of exponential tail states and Gaussian deep states.     

Design and fabrication of multiple-valued multiplexer using negative differential resistance circuits and standard SiGe process

The design of a four-valued multiplexer using the negative differential resistance (NDR) circuit is demonstrated. The NDR circuit used in this work is made of the Si-based metal–oxide–semiconductor field-effect-transistor (MOS) and the SiGe-based heterojunction bipolar transistor (HBT). However we can obtain the NDR characteristic in its combined I–V curve by suitably arranging the MOS parameters. This novel multiplexer is made of MOS–HBT–NDR-based decoders and inverters. The fabrication is based on the standard 0.35 μm SiGe BiCMOS process.     

Analysis of I–V measurements on PtSi-Si Schottky structures in a wide temperature range

I–V Measurements on PtSi-Si Schottky structures in a wide temperature range from 90 to 350 K were carried out. The contributions of thermionic-emission current and various other current-transport mechanisms were assumed when evaluating the Schottky barrier height Φ₀. Thus the generation-recombination, tunneling and leak currents caused by inhomogeneities and defects at the metal-semiconductor interface were taken into account.

Taking the above-mentioned mechanisms and their temperature dependence into consideration in the Schottky diode model, an outstanding agreement between theory and experiment was achieved in a wide temperature range.

Excluding the secondary current-transport mechanisms from the total current, a more exact value of the thermionic-emission saturation current I_te and thus a more accurate value ofΦ_b was reached.

The barrier height Φ_b and the modified Richardson constant A^** were calculated from the plot of thermionic-emission saturation current I_te as a function of temperature too. The proposed method of finding Φ_b is independent of the exact values of the metal-semiconductor contact area A and of the modified Richardson constant A^**. This fact can be used for determination of Φ_b in new Schottky structures based on multicomponent semiconductor materials.

Using the experimentally evaluated value A^** = 1.796 × 10⁶ Am⁻²K⁻² for the barrier height determination from I–V characteristics the value of Φ_b = 0.881 ± 0.002 eV was reached independent of temperature.

The more exact value of barrier height Φ_b is a relevant input parameter for Schottky diode computer-aided modeling and simulation, which provided a closer correlation between the experimental and theoretical characteristics.     

Metal-insulator-semiconductor structures of InSb/SiO2with very low interface trap density

MIS structures fabricated using InSb and silicon dioxide with an interface trap density as low as 4×10¹⁰ cm^-2 eV^-1 have been achieved. This is about one order of magnitude less than any other reported figure for the InSb MIS system. Both capacitance/voltage and conductance techniques have been employed to study the interface properties of InSb/SiO₂. A low state density of <10¹⁰ cm^-2 was observed and the dielectric breakdown field of the oxide was greater than 4 mV cm^-1      

A study of noise in surface and buried channel SiGe MOSFETs with gate oxide grown by low temperature plasma anodization

A study is made of noise in p- and n-channel transistors incorporating SiGe surface and buried channels, over the frequency range f=1 Hz–100 kHz. The gate oxide is grown by low temperature plasma oxidation. Surface n-channel devices are found to exhibit two noise components namely 1/f and generation–recombination (GR) noise. It is shown that the 1/f noise component is due to fluctuations of charge in slow oxide traps whilst bulk centers located in a thin layer of the semiconductor close to the channel, give rise to the GR noise component. The analysis of the noise data gives values for the density D_ot of the oxide traps in the SiGe and Si nMOSFETs of the order 1.8×10¹² and 2.5×10¹⁰ cm⁻² (eV)⁻¹, respectively. The density D_GR of the bulk GR centres is equal to 3×10¹⁰ cm⁻² in both the SiGe and Si devices. The electron and hole capture cross-sections for these centres as well as their energy level and their depth below the oxide/semiconductor interface are also the same in the devices of both types. This suggests that those GR centers are of the same nature in all devices studied. p-Channel devices show different behaviour with only a 1/f noise component apparent in the data over the same frequency range. Buried SiGe channel and Si control devices exhibit quite low and similar slow state densities of the order low to mid 10¹⁰ cm⁻² (eV)⁻¹ whereas surface p-channel devices show even higher slow state densities than n-channel counterparts. The Hooge noise characterized by the Hooge coefficient _H=2×10⁻⁵ is also detected in some buried p-channel SiGe devices.     

Trap density of silicon chlorine oxides

By measuring the ramp voltage I–V characteristics, we obtained the oxide trap density and capture cross-section for (O₂ + HCl) dry oxidized samples in the temperature range 900–1100°C. It was found that the oxide trap density increases with an increase in the oxidation temperature. The activation energy of oxide trap incorporation is of the order of 4 eV. The capture cross-section determined for the oxide traps is of the order of 10⁻¹⁴ cm².