Benchmarking semiconductor manufacturing

We are studying the manufacturing performance of semiconductor wafer fabrication plants in the US, Asia, and Europe. There are great similarities in production equipment, manufacturing processes, and products produced at these plants. Nevertheless, data reported here show that important quantitative measures of productivity vary by factors of 3 to as much as 5 across an international sample of 16 plants. We conducted on-site interviews with manufacturing personnel to better understand reasons for the observed wide variations in productivity. We have identified factors in the areas of information systems, organizational practices, process and technology improvements, and production control that correlate strongly with productivity     

Creating and using equipment models in semiconductor manufacturing

As integrated circuit cost and performance specifications grow more demanding, several aspects of classical manufacturing science are finding their way into the cleanroom. This presentation focuses on the definition, development and application of production worthy equipment models. The concepts of model development and characterization are illustrated with examples drawn from modeling low pressure chemical vapor deposition (LPCVD), plasma etch and lithography. Applications in recipe generation and model-based control and diagnosis are also discussed.     

半导体制造中颗粒污染的控制方法研究

首先分析了半导体制造中颗粒污染的来源,然后介绍了用C控制图进行颗粒污染控制的方法及其不足,进而提出了用多元回归分析进行颗粒污染控制的方法及实施.     

Two-dimensional semiconductor analysis using finite-element method

Two-dimensional simulation of semiconductor devices using a finite-element formulation is described. In the present analysis, Poisson's equation is solved by a finite-element method, based on the variational principle, and current continuity equations are solved by a method of weighted residuals. The advantage of this method is mentioned. In order to demonstrate the validity of this method, a bipolar n-p-n transistor is analyzed, considering the generation-recombination term. Not only voltage-current characteristic, but also junction capacitance and cutoff frequency are calculated. Then transistor behavior under inverse mode by using the n-type buried layer as a common emitter is discussed.     

Real-time statistical process control using tool data[semiconductor manufacturing]

A process monitoring scheme that takes advantage of real-time information in order to generate malfunction alarms is described. This is accomplished with the application of time-series filtering and multivariate statistical process control. This scheme is capable of generating alarms on a true real-time basis, while the wafer is still in the processing chamber. Several examples are presented with tool data collected from the SECSII port of single-wafer plasma etchers     

Enterprise-wide semiconductor manufacturing resource planning

We develop a model for global logistics and resource optimization in a typical semiconductor manufacturing operation. The model is designed to aid in resource allocation and strategic decisions for long term planning in the semiconductor industry. Decisions include where to make products, whether or not to open new facilities, whether or not to add new tools, and whether or not to subcontract.     

半导体制造车间设施规划浅析

在半导体制造业中,由于其设备的昂贵性、敏感性和制造过程的复杂性,工厂的布局一般不可以轻易更改。设计不周的不良布局将会导致庞大的物料搬运成本,无效的生产以及重新布局时所需要的大量成本。因此,工厂的设施规划已经成为半导体制造商们最关心的问题之一。本文依据设施规划的原则对半导体车间的最新布局方式作了系统的阐述。     

Theoretical performance of multigigabit-per-second lightwavesystems using injection-locked semiconductor lasers

The locking conditions for multigigabit-per-second modulation are examined, and the dependence of the receiver sensitivity on the fiber dispersion coefficient-length product is investigated. With a 4.8-Gb/s NRZ (nonreturn-to-zero) modulation, a 1-dB penalty in receiver sensitivity occurs for a transmission distance of 68 km. The injected power is 0.4 mW and the frequency detuning is -35 GHz. With 10-Gb/s NRZ modulation, the allowable transmission distance is 12.5 km for an injected power of 1.0 mW and a frequency detuning of -35 GHz. These results represent increases in the transmission distances obtained with a solitary laser by factors of 3.7 at 4.8 Gb/s and 2.7 at 10 Gb/s     

Test wafer management for semiconductor manufacturing

Test wafers (TWs) are used for equipment qualification purposes in semiconductor manufacturing. TW management is unique because of the possibility of downgrading a TW to test lower class processes. Since the yearly TW costs add up to several million dollars for a typical semiconductor fab, effective TW management can substantially reduce costs by identifying the right quantity of TWs to purchase, to downgrade, and to hold in the inventory. While the current industry practice is to use suboptimal rules to manage TWs, this paper develops a network-based formulation named TW Inventory Network (TWIN) to eliminate this suboptimality. Several special cases are analized here, and a numerical analysis is provided to shed further operational insights on the TW problem.     

Statistical process control in semiconductor manufacturing

This paper summarizes the basic concepts and tools of Statistical Process Control as used today in semiconductor manufacturing. After their introduction, important concepts are illustrated with the help of application examples drawn from the area of yield control, photolithography and plasma etching. Time series modeling and the impact of computer integrated manufacturing will also be discussed.     

半导体生产规划中的优化决策方法:线性规划

半导体制造是一个流程高度复杂,资金高度密集的加工过程,相对于其它制造业来说,其产品种类繁多,工序复杂,对设备的利用率要求较高,因而生产优化也较为复杂.本文利用线性规划(linear programming,LP),对半导体制造的封装和测试过程进行数学建模,并构建一套决策支持系统.与电子表格手工计算相比,该系统大大缩短了生产计划响应时间,并提高了瓶颈设备利用率.     

Statistical process control in semiconductor manufacturing

The author presents a brief survey of standard SPC (statistical process control) schemes, and illustrates them through examples taken from the semiconductor industry. These methods range from contamination control to the monitoring of continuous process parameters. It is noted that, even as SPC is transforming IC production, the peculiarities of semiconductor manufacturing technology are transforming SPC. Therefore, the author describes novel SPC applications which are now emerging in semiconductor production. These methods are being developed to monitor the short production runs that are characteristic of flexible manufacturing. Additional SPC techniques suitable for in situ multivariate sensor readings are also discussed     

Challenges of integration in semiconductor manufacturing firms

Manufacturing efforts to reduce time to market often adopt a concurrent engineering approach that focuses on coordination and integration among engineering, production and marketing functions. Technological complexity in the semiconductor industry requires an extension of this paradigm to include multiple engineering groups and a strong production maintenance department. Through interviews with employees drawn from engineering, production, maintenance, marketing and other departments at three semiconductor plants, organizational problems are uncovered that inhibit successful integration within firms in this industry. Ideas for overcoming these problems are given with suggestions for future research     

Methods for job configuration in semiconductor manufacturing

Job configuration in semiconductor manufacturing refers to the process of configuring silicon wafers in terms of chip types and volumes, organizing collections of wafers into jobs, and determining the volume of jobs to be released into the production line. The difficulties of job configuration lie in the random yield loss, the numerous technological constraints, and the rigid set serviceability requirement (i.e., demand must be met in terms of all chip types). Motivated by the configuration problems in the “early-user hardware” development programs at some IBM plants, we develop here a systematic approach to job configuration. The centerpiece of the approach is a careful treatment of the set serviceability constraint, in terms of both probability and expectation. It solves the job configuration problem as separable convex programs using marginal allocation algorithms. Through numerical examples, we demonstrate that by allowing diversity of chip types at either the job- or the wafer-level, higher serviceability can be achieved using fewer wafers     

A queueing network model for semiconductor manufacturing

We develop an open queueing network model for rapid performance analysis of semiconductor manufacturing facilities. While the use of queueing models for performance evaluation of manufacturing systems is not new, our approach differs from others in the detailed ways in which we model the different tool groups found in semiconductor wafer fabrication, as well as the way in which we characterize the effect of rework and scrap on wafer lot sizes. As an application of the model, we describe a method for performing tool planning for semiconductor lines. The method is based on a marginal allocation procedure which uses performance estimates from the queueing network model to determine the number of tools needed to achieve a target cycle time, with the objective being to minimize overall equipment cost     

A planner and scheduler for semiconductor manufacturing

The Microelectronics Manufacturing Science & Technology ((MMST) project includes two closely related CIM subsystems for planning and scheduling wafer production. The MMST Planner plans all work release into a factory so as to meet stated goals, and predicts work completion dates. The MMST Scheduler operates in real-time to determine the sequence of lot movements and machine loadings that will be performed on the fab floor. Both the Planner and the Scheduler continually maintain plans which are up to date with the factory status by incrementally replanning for unexpected events. The MMST Planner can be used as a decision support tool to rapidly analyze the consequences of various manufacturing decisions. Planning is performed using a modified beam search algorithm, and is based on a time-phased capacity model of the factory. Fuzzy arithmetic is used to model the uncertainty inherent in cycle time data. The MMST Planner is fully distributed, allowing simultaneous users in different parts of the factory. The MMST Scheduler uses a heuristic method called Score Tables to develop schedules of future events. The Scheduler evaluates event prerequisites to determine when to initiate lot transfers and machine loadings, and responds to any failures of execution     

Optimal preventive maintenance scheduling in semiconductor manufacturing

Preventive maintenance (PM) scheduling is a very challenging task in semiconductor manufacturing due to the complexity of highly integrated fab tools and systems, the interdependence between PM tasks, and the balancing of work-in-process (WIP) with demand/throughput requirements. In this paper, we propose a two-level hierarchical modeling framework. At the higher level is a model for long-term planning, and at the lower level is a model for short-term PM scheduling. Solving the lower level problem is the focus of this paper. We develop mixed-integer programming (MIP) models for scheduling all due PM tasks for a group of tools, over a planning horizon. Interdependence among different PM tasks, production planning data such as projected WIP levels, manpower constraints, and associated PM time windows and costs, are incorporated in the model. Results of a simulation study comparing the performance of the model-based PM schedule with that of a baseline reference schedule are also presented.     

Diagnosis of semiconductor manufacturing equipment and processes

This paper describes part of the research performed during the Microelectronic Manufacturing Science and Technology (MMST) program on techniques for the diagnosis of equipment malfunctions and misprocessing during semiconductor manufacturing. The main motivation of this work was to investigate techniques for rapid diagnosis. Towards this goal, a number of equipment-level diagnosis techniques are described. These techniques use equipment models to diagnose equipment malfunctions at a given process step. The results obtained by applying these diagnosis approaches are very encouraging. The various approaches were able to diagnose a number of faults that were deliberately introduced to test the algorithms and the equipment faults that developed during the final demonstration of the MMST program. These techniques were applied to a TI-built Advanced Vacuum Processor (AVP) and an Applied Materials Precision reactor AMT 5000     

Resource conservation of buffered HF in semiconductor manufacturing

With buffered hydrogen fluoride (BHF) treatment, the etch rate of thermal oxide gradually increases over time. Thus, the old BHF must be frequently changed to new BHF in order to maintain the etch rate. As a result, considerable BHF and other chemicals to treat waste BHF are consumed and considerable waste such as sludge and wastewater is discharged. We have developed a new method to maintain the etch rate by supplying ammonia and water evaporated from BHF. The amount depends on the amount of NH/sub 4/F/HF in BHF. Since the method can extend the usable lifetime of BHF, it will help to reduce BHF used and the chemicals required to treat waste BHF and decrease the discharge of wastewater and sludge.     

The impact of single-wafer processing on semiconductor manufacturing

In this paper, we have described the importance of single-wafer processing (SWP) in semiconductor manufacturing. As compared to batch processing, reduced cycle time, better control of surface and interface properties, and reduced defect densities are some of the attractive features of SWP. We have provided the example of new SWP tools that have the answers to address virtually all process integration issues in dealing with new materials as well as conventional materials in ultra small dimensions. Driven by reduced I/O pitches, and emergence of system-on-chip, system-in-package or system-on-package as the driver of semiconductor growth, SWP tools have started to play an important role in the surface cleaning in IC assembly and packaging. Global acceptance of SWP in manufacturing can address the supply chain problem of the semiconductor industry.