Deep submicrometer super self-aligned Si bipolar technology with25.4 ps ECL

A new deep submicron double-poly self-aligned Si bipolar technology has been developed using a 0.3-μm design rule, a collector polysilicon trench electrode, and oxide-filled trench isolation. This technology is called “High-Performance Super Self-Aligned Process Technology” or HSST. 0.3-μm minimum patterning is achieved by electron-beam direct writing technology. The HSST bipolar transistor is 2.5 times smaller than the previous 1-μm SST-1B. Owing to its horizontal reduction and an f_T of 22.3 GHz at V_ce=1 V, the ECL gate attains 25.4 ps/G at 1.58 mA, which is a 30% improvement on the SST-1B. By including parasitic capacitances of the base polyelectrode and polyresistors, the ECL delay time is accurately simulated for low-power operation. It is shown that the HSST is a very promising technology for the development of future high-speed communication systems     

A novel technology to form self-aligned emitter ledge for heterojunction bipolar transistors

We have proposed and successfully demonstrated a novel and simple process to fabricate self-aligned emitter passivation ledges for heterojunction bipolar transistors (HBTs) without using additional dielectric etch masks or dual etch-stop layers in the emitter. In this new ledge formation process, the emitter ledges are fabricated by the formation of photoresist sidewall spacers followed by a wet-chemical etch process. The effectiveness of this new ledge formation technology has been confirmed in AlGaAs/GaAs HBTs. Since the proposed ledge technology is very simple and without using any etch-stop layers (thus independent of material systems), it appears to be very promising for HBT fabrication.     

A nonrecessed-base, self-aligned bipolar structure with selectivelydeposited polysilicon emitter

A self-aligned bipolar structure, which features a nonrecessed base and a selectively deposited polysilicon emitter, is proposed. The in situ surface cleaning process prior to the selective-polysilicon deposition minimizes the residual native oxide in the emitter window. Both high-quality selective-polysilicon film and well-behaved submicrometer bipolar device characteristics have been obtained for bipolar or BiCMOS VLSI applications. The effects of the nonrecessed-base device structure on the bipolar device parameter distribution and bipolar hot-carrier immunity are also discussed     

Physics, technology, and modeling of polysilicon emitter contacts for VLSI bipolar transistors

The physics of minority-carrier injection into polysilicon-contacted emitters has been studied through a series of experiments correlating the base current of the transistor to the structure of the polysilicon/single-crystal silicon interface. Most of the relevant material and processing parameters have been examined. In addition, a novel approach has been taken in the modeling of transport in these emitters to quantify the minority-carrier blocking properties of the polysilicon contacts. Experimental results show that extremely low values of base current can be obtained for devices etched in HF prior to the polysilicon deposition, i.e., devices with only a remnant "native" oxide layer at the polysilicon/single-crystal silicon interface. For these devices, the base current is mainly determined by the recombination and blocking of minority carriers at the polysilicon/monosilicon interface. A number of competing mechanisms exist in several domains of doping, temperature, and time which influence the properties of this interface. One of these mechanisms is the blocking of minority carriers by the native oxide layer itself. The uniformity and, consequently, the blocking characteristics of this layer were found to be strongly affected by the polysilicon doping level and thermal treatment.     

An advanced high-performance trench-isolated self-aligned bipolar technology

This paper describes the extension of "double-poly" self-aligned bipolar technology to include a silicon-filled trench with self-aligned cap oxide isolation, a p{^+} polysilicon defined epi-base lateral p-n-p, a p{^+} polysilicon defined self-aligned guard-ring Schottky-barrier diode, and p{^+} polysilicon resistors. Experimental circuits designed with 1.2-µm design rules have shown switching delays of as small as 73 ps for ECL circuits with FI = FO = 1. ISL circuits built with the same process on the same chip as the ECL circuits exhibit a sub-400-ps switching delay. The performance of the technology has also been demonstrated by a 5-kbit ECL SRAM with a 760-µm²Schottky-clamped multi-emitter cell and 1.0-ns access time.     

High-gain bipolar transistors with polysilicon tunnel junction emitter contacts

Experimental measurements of the dc gain as a function of temperature and of emitter-base and collector-base current-voltage characteristics for bipolar transistors with polysilicon contacts to the emitter are reported, dc gains as high as 2000 have been measured in devices for which a thin insulating layer was encouraged to grow between the monocrystalline silicon emitter and the polycrystalline silicon contact layer. This gain is 20 times larger than that for devices in which the insulating film growth was inhibited. It is suggested that, for these particular devices, the polysilicon layer contributes to a contact which is very similar to that of a metal-insulator-semiconductor tunnel junction contact. A model based on this hypothesis is developed and shown to give a good fit to all the experimental data.     

A comprehensive analytical and numerical model of polysilicon emitter contacts in bipolar transistors

A comprehensive model-both analytical and numerical-is proposed as a tool to analyze heavily doped emitters of transistors with polycrystalline silicon (polysilicon) contacts. The grains and grain boundaries of polysilicon, the interfacial oxide-like layer between polycrystalline and monocrystalline silicon are lumped respectively into "boxes" in which the drift minority current component is neglected. The mobility reduction of carriers in polysilicon on the whole is explicitly attributed to the additional scattering due to the lattice disorder in the grain boundaries and the carrier tunneling through the interface. The effect of the poly-contacts on transistors can be modeled as a reduced surface recombination velocity for minority carriers in combination with a series emitter resistance for majority carriers. Furthermore, by characterizing the monocrystalline emitter with an effective recombination velocity, the effect of the polysilicon layer on the current gain can be analyzed analytically. Computer simulation is used to verify the assumptions of the model formulation. Using published data [1], the analytical and numerical approaches are compared and it is shown that for these devices a unique combination of physical parameters are needed for the model to fit the data.     

An advanced bipolar transistor with self-aligned ion-planted baseand W/poly emitter

The fabrication, device profile, and electrical characteristics of an advanced bipolar transistor with an LDD-like self-aligned lateral profile are discussed. An ion-implanted extrinsic base with a low sheet resistance of 55 Ω/square and a junction depth of 0.35 μm is obtained using rapid thermal annealing. The extrinsic base and emitter are separated by a temporary submicrometer sidewall spacer, which is subsequently removed to maintain a planar surface during the emitter-active-base formation process. The emitter is contacted by a W-TiN-n⁺ polysilicon stack with a sheet resistance of 1 Ω/square. As a result of the planarity of the surface during the profile formation for the active region and the decoupling of the structural process from the thin base process, an active base width of 105 nm is obtained     

Characterization of non-ohmic behavior of emitter contacts of bipolar transistors

Emitter contacts of bipolar transistors, with silicide or polysilicon contacts, are electrically characterized by analyzing the deviation of the base current at high currents from its ideal exponential behavior. A simple theory is presented that explains the deviation of the series voltage drop from ohmic behavior, observed in some of the devices with polysilicon emitter contact, in terms of an interface with tunneling properties.     

A fine emitter transistor fabricated by electron-beam lithography for high-speed bipolar LSI's

A highly stable, high-performance bipolar transistor with a 1/4-µm emitter is developed. This is accomplished by using advanced electron-beam (EB) lithography and polysilicon reactive ion etching (RIE). Results show that the minimum emitter width is only 0.2 µm and the emitter width accuracy is ±0.06 µm. In addition, the gate delay is reduced from 190 to 100 ps/gate for 25-stage, three-input ECL circuits. The effects of an ultra-narrow emitter on transistor characteristics are also studied.     

A 30-ps Si bipolar IC using super self-aligned process technology

A new 30-ps Si bipolar IC technology has been developed by scaling down a bipolar transistor's lateral geometry and forming shallow junctions. The n-p-n transistor has a 0.35-µm-wide emitter and a 1.57-µm-wide base region fabricated using super self-aligned process technology (SST) with 1-µm rule optical lithography. The fTvalues achieved for this device are 13.7 GHz at a collector-emitter voltage of 1 V and 17.1 GHz at 3 V. Propagation delay times (fan-in = fan-out = 1) of 30 ps/gate at 1.48 mW/gate for nonthreshold logic and 50 ps/ gate at 1.46 mW/gate for low-level current mode logic have been achieved.     

Gigabit logic bipolar technology: advanced super self-aligned process technology

A practical bipolar logic circuit, a three-stage frequency divider, has been made with advanced super self-aligned process technology (a halfmicron bipolar technology), which has been operated at clock frequencies up to 5.5 GHz.     

GaAs/(GaAl)As heterojunction bipolar transistors using a self-aligned substitutional emitter process

This paper describes the first self-aligned heterojunction bipolar transistor (HBT) process which includes ion implantation to reduce the base resistance. With this substitutional emitter technique, the base implant and the emitter contact patterns are defined with the same mask. Arbitrary contact materials can be used allowing optimization of the contact resistances. Transistors with emitter width down to 1.5 µm have been fabricated. Nonthreshold logic (NTL) ring oscillators made with these transistors had propagation delay times down to 27.2 ps. This is the lowest reported to date for bipolar transistors.     

Analysis and minimization of small-geometry effects on the currentgain of self-aligned `etched-polysilicon' emitter bipolar transistors

The authors report on a detailed analysis of small-geometry effects on the current gain of advanced self-aligned etched-polysilicon emitter bipolar transistors. By studying the dependence of collector and base currents on device geometry and process parameters, they have been able to identify the critical fabrication steps and physical mechanisms involved. The narrow emitter effect is caused by the butting of the emitter-base junction to the field oxide, and is mainly controlled by the gate oxide removal step prior to polysilicon deposition. Short emitter effects are associated with phenomena taking place in the spacer region of the device perimeter during polysilicon patterning, spacer pedestal thermal oxidation, link base implantation, and final rapid thermal anneal. Proper adjustment of all process parameters is shown to allow good control of the narrow-emitter effect and complete compensation of short-emitter effects, showing promise for the future of this CMOS-compatible bipolar transistor structure     

Gigahertz-band analogue switch using bipolar super self-aligned process technology

A novel bipolar analogue switch has been developed using super self-aligned process technology (SST). The switch with three emitter-coupled pairs achieved high net isolation of 40 dB and low third-order intermodulation of less than ?40 dB below the input level of ?7 dBm at 1 GHz.     

A 9-GHz frequency divider using Si bipolar super self-aligned process technology

A very high-speed 1/8 frequency divider is fabricated, using Si bipolar super self-aligned process technology (SST), and tested. The circuit consists of three T-connected D-type master-slave flip-flops and buffers. A low voltage swing (225 mV) differential circuit technique is adopted for the first stage T-type flip-flop. The divider is capable of operating at up to 9 GHz with a power dissipation of 554 mW.     

A tunneling emitter bipolar transistor

We propose a new device-a Tunneling Emitter Bipolar Transistor (TEBT)-where the enhancement of the emitter injection efficiency is achieved by utilizing a very large difference in the tunneling probabilities for electrons and holes in a thin doped graded AlGaAs layer. This layer is inserted between the n-type GaAs emitter and p-type GaAs base. This device should have a high emitter efficiency and low parasitic resistances.     

In situ phosphorus-doped polysilicon emitter technology for veryhigh-speed, small emitter bipolar transistors

In situ phosphorus-doped polysilicon emitter (IDP) technology for very high-speed, small-emitter bipolar transistors is studied. The device characteristics of IDP transistors are evaluated and compared with those of conventional ion-implanted polysilicon emitter transistors. IDP technology is used to fabricate double polysilicon self-aligned bipolar transistors and the I-V characteristics, current gain, transconductance, emitter resistance, and cut-off frequency are measured. In conventional transistors, these device characteristics degrade when the emitter is small because of the emitter-peripheral-thick-polysilicon effect. In IDP transistors, the peripheral effect is completely suppressed and large-grain, high-mobility polysilicon can be used. The device characteristics, therefore, are not degraded in sub-0.2-μm emitter transistors. In addition, large-grain, high-mobility, and high phosphorus concentration IDP films increase current gain and lower emitter resistance. The use of IDP technology to build very small emitter transistors is evaluated and discussed     

A depletion load self-aligned technology

Based on an accurate large signal MOSFET model, a computer aided design of the elementary NOR gate using a P channel depletion enhancement self-aligned technology has been done so as to minimize power-speed product. Threshold adjustment and gate self-registration are achieved by ion implantation. Measurements of main electrical and technological parameters are given. Computer aided design results are compared with measured performances on a 99 gates ring oscillator. For a 5 V supply voltage power-speed products as low as 1 pJ are obtained.