Thermally robust TaTb/sub x/N metal gate electrode for n-MOSFETs applications

In this letter, we study Terbium (Tb)-incorporated TaN (TaTb/sub x/N) as a thermally robust N-type metal gate electrode for the first time. The work function of the Ta/sub 0.94/Tb/sub 0.06/N/sub y/ metal gate is determined to be /spl sim/4.23 eV after rapid thermal anneal at 1000/spl deg/C for 30 s, and can be further tuned by varying the Tb concentration. Moreover, the TaTb/sub x/N-SiO/sub 2/ gate stack exhibits excellent thermal stability up to 1000/spl deg/C with no degradation to the equivalent oxide thickness, gate leakage, and time-dependent dielectric breakdown (TDDB) characteristics. These results suggest that Tb-incorporated TaN (TaTb/sub x/N) could be a promising metal gate candidate for n-MOSFET in a dual-metal gate Si CMOS process.     

Fermi-level pinning induced thermal instability in the effective work function of TaN in TaN/SiO/sub 2/ gate stack

In this letter, we demonstrate for the first time that the Fermi-level pinning caused by the formation of Ta(N)-Si bonds at the TaN/SiO/sub 2/ interface is responsible for the thermal instability of the effective work function of TaN in TaN/SiO/sub 2/ devices after high temperature rapid thermal annealing (RTA). Because of weak charge transfer between Hf and Ta(N) and hence negligible pinning effect at the TaN/HfO/sub 2/ interface, the effective work function of TaN is significantly more thermally stable on HfO/sub 2/ than on SiO/sub 2/ dielectric during RTA. This finding provides a guideline for the work function tuning and the integration of metal gate with high-/spl kappa/ dielectric for advanced CMOS devices.     

Effect of the composition on the electrical properties of TaSi/sub x/N/sub y/ metal gate electrodes

In this letter, the effect of silicon and nitrogen on the electrical properties of TaSi/sub x/N/sub y/ gate electrode were investigated. The TaSi/sub x/N/sub y/ films were deposited on SiO/sub 2/ using reactive cosputtering of Ta and Si target in Ar and N/sub 2/ ambient. The thermal stability of TaSi/sub x/N/sub y//SiO/sub 2//p-type Si stacks was evaluated by measuring the flatband voltage and equivalent oxide thickness at 400/spl deg/C and 900/spl deg/C in Ar. It was found that under high temperature anneals, Si-rich TaSi/sub x/N/sub y/ films increased and this was attributed to the formation of a reaction layer at the electrode-dielectric interface. Reducing the Si content alone did not prevent the formation of this reaction layer while removing Si completely by utilizing TaN resulted in work functions that were too high. The presence of both Si and N was deemed necessary and their content was critical in obtaining optimized TaSi/sub x/N/sub y/ gates that are suitable for NMOS devices.     

Effects of interstitial oxygen defects at HfO/sub x/N/sub y//Si interface on electrical characteristics of MOS devices

Effects of the defects at high-/spl kappa/ dielectric/Si interface on the electrical characteristics of MOS devices are important issues. To study these issues, a low defect (denuded zone) at Si surface was formed by a high-temperature annealing in hydrogen atmosphere in this paper. Our results reveal that HfO/sub x/N/sub y/ demonstrates significant improvement on the electrical properties of MOS devices due to its low amount of the interstitial oxygen [O/sub i/] and the crystal-originated particles defects as well as small surface roughness at HfO/sub x/N/sub y//Si interface. The current-conduction mechanism of the HfO/sub x/N/sub y/ film at the low- and high-electrical field and high-temperature (T>100/spl deg/C) is dominated by Schottky emission and Frenkel-Poole (FP) emission, respectively. The trap energy level involved in FP conduction was estimated to be around 0.5eV. Reduced gate leakage current, stress-induced leakage current and defect generation rate, attributable to the reduction of defects at HfO/sub x/N/sub y//Si interface, were observed for devices with denuded zone. The variable rise and fall time bipolar-pulse-induced current technique was used to determine the energy distribution of interface trap density (D/sub it/). The results exhibit that relatively low D/sub it/ can be attributed to the reduction of defects at Si surface. By using denuded zone at the Si surface, HfO/sub x/N/sub y/ has demonstrated significant improvement on electrical properties as compared to SiO/sub x/N/sub y/.     

Novel dual-metal gate technology using Mo-MoSi/sub x/ combination

A novel dual-metal gate technology that uses a combination of Mo-MoSi/sub x/ gate electrodes is proposed. An amorphous-Si/Mo stack was fabricated as a gate electrode for the n-channel device. It was thermally annealed to form MoSi/sub x/. Pure Mo served as the gate electrode for the p-channel device. The work functions of MoSi/sub x/ and pure Mo gates on SiO/sub 2/ are 4.38 and 4.94 eV, respectively, which are appropriate for devices with advanced transistor structures. The small increase in the work function (< 20 meV) and the negligible equivalent oxide thickness variation (< 0.08 nm) after rapid thermal annealing at 950 /spl deg/C for 30 s also demonstrate the excellent thermal stabilities of Mo and MoSi/sub x/ on SiO/sub 2/. Additional arsenic ion implantation prior to silicidation was demonstrated further to lower the work function of MoSi/sub x/ to 4.07 eV. This approach for modulating the work function makes the proposed combination of Mo-MoSi/sub x/ gate electrodes appropriate for conventional bulk devices. The developed dual-metal-gate technology on HfO/sub 2/ gate dielectric was also evaluated. The effective work functions of pure Mo and undoped MoSi/sub x/ gates on HfO/sub 2/ are 4.89 and 4.34 eV, respectively. A considerable work-function shift was observed on the high-/spl kappa/ gate dielectric. The effect of arsenic preimplantation upon the work function of the metal silicide on HfO/sub 2/ was also demonstrated, even though the range of modulation was a little reduced.     

A dual-metal gate integration process for CMOS with sub-1-nm EOT HfO/sub 2/ by using HfN replacement gate

A replacement gate process employing a HfN dummy gate and sub-1-nm equivalent oxide thickness (EOT) HfO/sub 2/ gate dielectric is demonstrated. The excellent thermal stability of the HfN-HfO/sub 2/ gate stack enables its use in high temperature CMOS processes. The replacement of HfN with other metal gate materials with work functions adequate for n- and pMOS is facilitated by a high etch selectivity of HfN with respect to HfO/sub 2/, without any degradation to the EOT, gate leakage, or time-dependent dielectric breakdown characteristics of HfO/sub 2/. By replacing the HfN dummy gate with Ta and Ni in nMOS and pMOS devices, respectively, a work function difference of /spl sim/0.8 eV between nMOS and pMOS gate electrodes is achieved. This process could be applicable to sub-50-nm CMOS technology employing ultrathin HfO/sub 2/ gate dielectric.     

Atomic layer deposition of high-/spl kappa/ dielectric for germanium MOS applications - substrate

In this letter, we present the use of atomic layer deposition (ALD) for high-/spl kappa/ gate dielectric formation in Ge MOS devices. Different Ge surface cleaning methods prior to high-/spl kappa/ ALD have been evaluated together with the effects on inserting a Ge oxynitride (GeO/sub x/N/sub y/) interlayer between the high-/spl kappa/ layer and the Ge substrate. By incorporating a thin GeO/sub x/N/sub y/ interlayer, we have demonstrated excellent MOS capacitors with very small capacitance-voltage hysteresis and low gate leakage. Physical characterization has also been done to further investigate the quality of the oxynitride interlayer.     

Robust high-quality HfN-HfO/sub 2/ gate stack for advanced MOS device applications

In this letter, a thermally stable and high-quality HfN-HfO/sub 2/ gate stack for advanced MOS applications is reported for the first time. Negligible changes in both equivalent oxide thickness (EOT) and work function of HfN-HfO/sub 2/ gate stack are demonstrated even after 1000/spl deg/C postmetal annealing (PMA), which is attributed to the superior oxygen diffusion barrier property of HfN as well as the thermal stability of the HfN-HfO/sub 2/ interface. Therefore, even without surface nitridation prior to HfO/sub 2/ deposition, the EOT of HfN-HfO/sub 2/ gate stack can be successfully scaled down to less than 10 /spl Aring/ after 1000/spl deg/C PMA with excellent leakage and long-term reliability.     

Physical and electrical characteristics of HfN gate electrode for advanced MOS devices

In this letter, the physical and electrical properties of physical vapor deposited (PVD) hafnium nitride (HfN) is studied for the first time as the metal gate electrode for advanced MOS devices applications. It is found that HfN possesses a midgap work function in tantalum nitride (TaN)/HfN/SiO/sub 2//Si MOS structures. TaN/HfN stacked metal-gated MOS capacitors exhibit negligible variations on equivalent oxide thickness (EOT), leakage current, and work function upon high-temperature treatments (up to 1000 /spl deg/C), demonstrating the excellent thermal stability of HfN metal gate on SiO/sub 2/. Our results suggest that HfN metal electrode is an ideal candidate for the fully depleted SOI and/or symmetric double gate MOS devices application.     

ScN/sub x/ gate on atomic layer deposited HfO/sub 2/ and effect of high-pressure wet post deposition annealing

For nMOS devices with HfO/sub 2/, a metal gate with a very low workfunction is necessary. In this letter, the effective workfunction (/spl Phi//sub m,eff/) values of ScN/sub x/ gates on both SiO/sub 2/ and atomic layer deposited (ALD) HfO/sub 2/ are evaluated. The ScN/sub x//SiO/sub 2/ samples have a wide range of /spl Phi//sub m,eff/ values from /spl sim/ 3.9 to /spl sim/ 4.7 eV, and nMOS-compatible /spl Phi//sub m,eff/ values can be obtained. However, the ScN/sub x/ gates on conventional post deposition-annealed HfO/sub 2/ show a relatively narrow range of /spl Phi//sub m,eff/ values from /spl sim/ 4.5 to /spl sim/ 4.8 eV, and nMOS-compatible /spl Phi//sub m,eff/ values cannot be obtained due to the Fermi-level pinning (FLP) effect. Using high-pressure wet post deposition annealing, we could dramatically reduce the extrinsic FLP. The /spl Phi//sub m,eff/ value of /spl sim/ 4.2 eV was obtained for the ScN/sub x/ gate on the wet-treated HfO/sub 2/. Therefore, ScN/sub x/ metal gate is a good candidate for nMOS devices with ALD HfO/sub 2/.     

Fully silicided NiSi:Hf-LaAlO/sub 3//SG-GOI n-MOSFETs with high electron mobility

We have integrated the low work function NiSi:Hf gate on high-/spl kappa/ LaAlO/sub 3/ and on smart-cut Ge-on-insulator (SC-GOI) n-MOSFETs. At 1.4-nm equivalent oxide thickness, the NiSi:Hf-LaAlO/sub 3//SC-GOI n-MOSFET has comparable gate leakage current with the control Al gate on LaAlO/sub 3/-Si MOSFETs that is /spl sim/5 orders of magnitude lower than SiO/sub 2/. In addition, the LaAlO/sub 3//SC-GOI n-MOSFET with a metal-like fully NiSi:Hf gate has high peak electron mobility of 398 cm/sup 2//Vs and 1.7 times higher than LaAlO/sub 3/-Si devices.     

Physically based quantum-mechanical compact model of MOS devices substrate-injected tunneling current through ultrathin (EOT /spl sim/ 1 nm) SiO/sub 2/ and high-/spl kappa/ gate stacks

Building on a previously presented compact gate capacitance (C/sub g/-V/sub g/) model, a computationally efficient and accurate physically based compact model of gate substrate-injected tunneling current (I/sub g/-V/sub g/) is provided for both ultrathin SiO/sub 2/ and high-dielectric constant (high-/spl kappa/) gate stacks of equivalent oxide thickness (EOT) down to /spl sim/ 1 nm. Direct and Fowler-Nordheim tunneling from multiple discrete subbands in the strong inversion layer are addressed. Subband energies in the presence of wave function penetration into the gate dielectric, charge distributions among the subbands subject to Fermi-Dirac statistics, and the barrier potential are provided from the compact C/sub g/-V/sub g/ model. A modified version of the conventional Wentzel-Kramer-Brillouin approximation allows for the effects of the abrupt material interfaces and nonparabolicities in complex band structures of the individual dielectrics on the tunneling current. This compact model produces simulation results comparable to those obtained via computationally intense self-consistent Poisson-Schro/spl uml/dinger simulators with the same MOS devices structures and material parameters for 1-nm EOTs of SiO/sub 2/ and high-/spl kappa//SiO/sub 2/ gate stacks on (100) Si, respectively. Comparisons to experimental data for MOS devices with metal and polysilicon gates, ultrathin dielectrics of SiO/sub 2/, Si/sub 3/N/sub 4/, and high-/spl kappa/ (e.g., HfO/sub 2/) gate stacks on (100) Si with EOTs down to /spl sim/ 1-nm show excellent agreement.     

Electrical properties of RuO/sub 2/ gate electrodes for dual metal gate Si-CMOS

The rutile stoichiometric phase of RuO/sub 2/, deposited via reactive sputtering, was evaluated as a gate electrode for Si-PMOS devices. Thermal and chemical stability of the electrodes was studied at annealing temperatures of 400/spl deg/C and 600/spl deg/C in N/sub 2/. X-ray diffraction patterns were measured to study grain structure and interface reactions. Very low resistivity values were observed and were found to be a strong function of temperature. Electrical properties were evaluated on MOS capacitors, which indicated that the workfunction of RuO/sub 2/ was compatible with PMOS devices. Excellent stability of oxide thickness, flatband voltage and gate current as a function of temperature was also found. Breakdown fields were also measured for the samples before and after annealing.     

Thermally robust HfN metal as a promising gate electrode for advanced MOS device applications

A systematic study of thermally robust HfN metal gate on conventional SiO/sub 2/ and HfO/sub 2/ high-/spl kappa/ dielectrics for advanced CMOS applications is presented. Both HfN-SiO/sub 2/ and HfN-HfO/sub 2/ gate stacks demonstrates robust resistance against high-temperature rapid thermal annealing (RTA) treatments (up to 1000/spl deg/C), in terms of thermal stability of equivalent oxide thickness (EOT), work function, and leakage current. This excellent property is attributed to the superior oxygen diffusion barrier of HfN as well as the chemical stability of HfN-HfO/sub 2/ and HfN-SiO/sub 2/ interfaces. For both gate dielectrics, HfN metal shows an effective mid-gap work function. Furthermore, the EOT of HfN-HfO/sub 2/ gate stack has been successfully scaled down to less than 10 /spl Aring/ with excellent leakage, boron penetration immunity, and long-term reliability even after 1000/spl deg/C annealing, without using surface nitridation prior to HfO/sub 2/ deposition. As a result, the mobility is improved significantly in MOSFETs with HfN-HfO/sub 2/ gate stack. These results suggest that HfN metal electrode is an ideal candidate for ultrathin body fully depleted silicon-on-insulator (SOI) and symmetric double-gate MOS devices.     

Three-Layer laminated metal gate electrodes with tunable work functions for CMOS applications

This letter presents a novel technique for tuning the work function of a metal gate electrode. Laminated metal gate electrodes consisting of three ultrathin (/spl sim/1-nm) layers, with metal nitrides (HfN, TiN, or TaN) as the bottom and top layers and element metals (Hf, Ti, or Ta) as the middle layer, were sequentially deposited on SiO/sub 2/, followed by rapid thermal annealing annealing. Annealing of the laminated metal gate stacks at high temperatures (800/spl deg/C-1000/spl deg/C) drastically increased their work functions (as much as 1 eV for HfN-Ti-TaN at 1000/spl deg/C). On the contrary, the bulk metal gate electrodes (HfN, TiN and TaN) exhibited consistent midgap work functions with only slight variation under identical annealing conditions. The work function change of the laminated metal electrodes is attributed to the crystallization and the grain boundary effect of the laminated structures after annealing. This change is stable and not affected by subsequent high-temperature process. The three-layer laminated metal gate technique provides PMOS-compatible work functions and excellent thermal stability even after annealing at 1000/spl deg/C.     

Turn-on voltage investigation of GaAs-based bipolar transistors with Ga/sub 1-x/In/sub x/As/sub 1-y/N/sub y/ base layers

The fundamental lower limit on the turn on voltage of GaAs-based bipolar transistors is first established, then reduced with the use of a novel low energy-gap base material, Ga/sub 1-x/In/sub x/As/sub 1-y/N/sub y/. InGaP/GaInAsN DHBTs (x/spl sim/3y/spl sim/0.01) with high p-type doping levels (/spl sim/3/spl times/10/sup 19/ cm/sup -3/) and dc current gain (/spl beta//sub max//spl sim/68 at 234 /spl Omega///spl square/) are demonstrated. A reduction in the turn-on voltage over a wide range of practical base sheet resistance values (100 to 400 /spl Omega///spl square/) is established relative to both GaAs BJTs and conventional InGaP/GaAs HBTs with optimized base-emitter interfaces-over 25 mV in heavily doped, high dc current gain samples. The potential to engineer turn-on voltages comparable to Si- or InP-based bipolar devices on a GaAs platform is enabled by the use of lattice matched Ga/sub 1-x/In/sub x/As/sub 1-y/N/sub y/ alloys, which can simultaneously reduce the energy-gap and balance the lattice constant of the base layer when x/spl sim/3y.     

Continuous and precise work function adjustment for integratable dual metal gate CMOS technology using Hf-Mo binary alloys

We demonstrate for the first time a continuous and almost linear work function adjustment between 3.93 and 4.93eV using Hf/sub x/Mo/sub (1-x)/ binary alloys deposited by co-sputtering. In view of the process integration, dual work function metal gate technology using Mo and Hf/sub x/Mo/sub (1-x)/ formed by metal intermixing was proposed. Work function values were verified to be a function of the thickness ratio and accurate work function adjustment can be possible. Furthermore, one can be allowed to get around the thermal stability issue by choosing an appropriate total metal thickness corresponding to the thermal budget subsequent to gate deposition, since the thermal budget required for metal intermixing depends on the total metal thickness.     

Radiation hardness comparison of MOS capacitors using tungsten polycide and cobalt polycideas gate electrode materials

In this letter, we investigate the radiation hardness of metal-oxide-semiconductor (MOS) capacitors with tungsten polycide (WSi/sub x/) and those with cobalt polycide (CoSi/sub 2/) as gate electrode materials. CoSi/sub 2/ has been considered as a gate/contact material for MOS devices in 0.18 /spl mu/m integrated circuit fabrication due to its low resistivity and good thermal stability. However, we found that MOS capacitors with a CoSi/sub 2/ gate electrode exhibited an increase in radiation-induced interface trap density shift of more than one order of magnitude, and more than eighteen times larger in radiation-induced flatband voltage shifts compared with those with the WSi/sub x/ gate electrode, after 1 Mrad Co/sup 60/ /spl gamma/-ray irradiation under no applied bias.     

Electrical and reliability characteristics of an ultrathin TaO/sub x/N/sub y/ gate dielectric prepared by ND/sub 3/ annealing of Ta/sub 2/O/sub 5/

This letter describes a unique process for the preparation of high quality tantalum oxynitride (TaO/sub x/N/sub y/) via the ND/sub 3/ annealing of Ta/sub 2/O/sub 5/, for use in gate dielectric applications. Compared with tantalum oxide (Ta/sub 2/O/sub 5/), a significant improvement in the dielectric constant was obtained by the ammonia treatment followed by light reoxidation in a wet ambient. We were able to confirm nitrogen incorporation in the tantalum oxynitride (TaO/sub x/N/sub y/) by Auger electron spectroscopy. Compared with NH/sub 3/ nitridation, tantalum oxynitride prepared by nitridation in ND/sub 3/ shows less charge trapping and larger charge-to-breakdown characteristics.     

MOS Compatibility of High-Conductivity TaSi/sub 2//n+ Poly-Si Gates

The MOS-VLSI parameters and process compatibility of a high-conductivity refractory silicide gate with a sheet resistance of -2 Omega//spl square/ have been evaluated. The gate metallization typically consisted of 2.5 k/spl Aring/ TaSi/sub 2//2.5 k/spl Aring/ poly-Si, which was sintered prior to patterning with a CF/sub 4//O/sub 2/ plasma etch. Measurements were made to determine the metal work function, oxide freed charge, surface-states density, dielectric strength, oxide defect density, lifetime, current leakage, and the flat-band voltage stability with respect to mobile charge contamination, slow trapping, and hot-electron trapping. On IGFET's (500-/spl Aring/ SiO/sub 2/, As-implanted source/drain), V/sub T/ and Beta measurements were made as a function of the back-gate bias and the channel length as small as 2 µm. The MOS and IGFET parameters are nearly ideal and correspond to those expected of n+ poly-Si gates. Static and dynamic bias-temperature aging stability of the V/sub FB/ is excellent. These characteristics are preserved through subsequent standard VLSI process steps. However, certain process and structure limitations do exist and these have been defined.