微纳米级键合强度分析(英文)

本文主要研究了微米/纳米尺度的键合技术和键合强度,给出并发展了基于MEMS技术的微米/纳米键合分析模型.为提取微米/纳米键合面积的最大剪应力和压应力,设计、制备和测试了一系列单晶硅悬臂梁结构.并使用理论公式和ANSYS有限元模拟对实验结果进行了分析.键合强度可以分为扭转和剪压表征两部分.根据测试值可得,最大抗扭强度为1.9×109μN.μm,最大压应力为68.3 MPa.     

低温非晶硅/金圆片键合技术(英文)

本文研究了低温非晶硅/金圆片键合技术.具有不同金硅比的键合片在400℃键合温度和1 MPa键合压力下维持30 min,其键合成功区域均高于94%,平均剪切强度均大于10.1 MPa.键合强度测试结果表明键合成品率与金硅比大小无关,平均剪切强度在10～20 MPa范围内.微观结构分析表明键合后单晶硅颗粒随机分布在键合层内,而金则充满其他区域,形成了一个无空洞的键合层.无空洞键合层确保不同金硅比非晶硅/金键合片均具有较高的键合强度,可实现非晶硅/金键合技术在圆片键合领域的应用.     

一种用电晕放电仪实现PDMS改性与键合方法

聚二甲基硅氧烷(PDMS)的表面改性与键合是微流控芯片制作中的关键技术之一。本文比较分析了PDMS常用表面改性方法的优缺点,利用电晕放电仪在常温环境下产生的氧等离子体实现了对PDMS表面改性及不可逆键合,优化了电晕放电仪的表面处理参数,重点测试了PDMS分别与PDMS和PMMA之间的键合强度。并与紫外照射、表面活化剂等表面改性方法得到的键合进行了强度比较。键合强度测试结果表明:常温下氧等离子体表面改性效果略逊于真空环境中的氧等离子体表面处理,但是其键合强度达到700KPa,高于其它表面改性方法的键合强度。     

基于正交试验分析的阳极键合强度研究

采用抗拉强度作为键合质量评价的指标,对硅-玻璃阳极键合的键合温度、冷却速度、退火温度和时间等四个参数的三个位级下的键合效果进行了分析。通过采用正交试验分析法,将81组试验减少为9组并进行了试验。采用自制的抗拉强度测试机对强度进行了测试,结果发现,阳极键合后的冷却速度对强度的影响最为显著,冷却速度越低,强度越高。最后对断裂面进行了SEM分析并对试验结果进行了讨论。     

面向超高温压力传感器的SiC-SiC键合方法

为了实现耐高温压力传感器SiC腔体的制作,分别利用高性能陶瓷胶、旋涂玻璃和金属Ni等3种材料作为键合层,研究了SiC-SiC键合工艺.扫描电子显微镜和键合拉伸强度实验结果表明,这3种材料的键合层均可以成功应用于SiC-SiC键合,其中高性能陶瓷胶键合层厚度为20~30μm,键合强度可达4 MPa;旋涂玻璃键合层厚度为2μm左右,键合强度约1.5 MPa;金属Ni键合层厚度为1μm,键合强度约为0.5 MPa.     

InP/GaAs低温键合的新方法

通过对 InP/GaAs 异质键合实验方法的研究,提出了包括表面活化处理、真空预键合和退火热处理的三步法,在350℃低温下实现了InP/GaAs异质材料的键合。界面电流 电压(I V)特性的研究表明,350℃样品的界面过渡层极薄,电子主要以隧穿方式通过界面,而450℃的扩散使得过渡层增厚,界面电流 电压特性可视为双肖特基二极管的反向串联。同时,对键合样品也进行了拉力测试,实验结果表明 450℃样品的键合强度优于350℃样品。最后,对InP/GaAs异质材料的键合机理进行了探讨。     

晶圆直接键合及室温键合技术研究进展

晶圆直接键合技术可以使经过抛光的半导体晶圆,在不使用粘结剂的情况下结合在一起,该技术在微电子制造、微机电系统封装、多功能芯片集成以及其他新兴领域具有广泛的应用。对于一些温度敏感器件或者热膨胀系数差异较大的材料进行键合时,传统的高温键合方法已经不再适用。如何在较低退火温度甚至无需加热的室温条件下,实现牢固的键合是晶圆键合领域的一项挑战。本文以晶圆直接键合为主题,简单介绍了硅熔键合、超高真空键合、表面活化键合和等离子体活化键合的基本原理、技术特点和研究现状。除此之外,以含氟等离子体活化键合方法为例,介绍了近年来在室温键合方面的最新进展,并探讨了晶圆键合技术的未来发展趋势。     

基于中间硅片厚度可控的三层阳极键合技术

三层键合Glass-Silicon-Glass(GSG)结构在光MEMS、微惯性器件、微流体芯片、射频MEMS以及低成本圆片级封装技术领域里是一项重要技术.基于MEMS精密研磨抛光工艺和阳极键合,结合新型玻璃通孔的腐蚀工艺,开展了中间硅片厚度可控的三层阳极键合工艺研究,成功制备了带有通孔的GSG微流体器件.总厚度1360μm,中间硅片厚度60μm,通孔直径100μm,孔间距(圆孔的中心距离)200μm,孔内边缘圆滑无侧蚀.三层结构的键合几率为90%,为探索多层键合技术打下坚实基础.     

直接键合硅片的三步亲水处理法及界面电特性

亲水处理是硅片能否直接键合成功的关键。基于亲水处理的微观机理分析和不同清洗要水处理的过程及效果,本文提出了独特的三步亲水处理法。这一方法既能顺利完成室温预键合,又能减少界面上非定形大尺寸ＳｉＯｘ体的生成,避免了界面对电输运的势垒障碍,结果获得了理想的键合界面。     

硅玻璃阳极键合绝压压阻式压力传感器中的残余应力

硅玻璃阳极键合技术因键合强度高,工艺简单而成为低成本绝压压力传感器的主要封装技术.但由于常规的硅玻璃阳极键合需要在相对较高的温度下进行且材料之间不可避免的热膨胀系数失配将产生较大的残余应力.实验采用有限元方法对硅玻璃阳极键合进行了系统的力学分析以减小残余应力对器件性能的影响.实验中采用硅玻璃阳极键合技术制备了不同压敏膜厚度和尺寸的传感器并测试其曲率与零点以对残余应力进行分析验证.     

玻璃浆料低温气密封装MEMS器件研究

系统地研究了玻璃浆料在低温下气密封装MEMS器件的过程。采用该工艺（预烧结温度400℃,烧结温度500℃,外加压强3kPa）形成的封装结构具有较高的封接强度（剪切力〉15kg）及良好的气密性（气密检测合格率达到85％）,测得的漏率符合相关标准。     

Solidification and interfacial interactions in gold–tin system during eutectic or thermo-compression bonding for 200 mm MEMS wafer level hermetic packaging

In this work, Au–Sn eutectic bonding and Au–Sn thermo-compression bonding are studied for applications in hermetic packaging at wafer level. Eutectic bonding experiments were performed under vacuum or pure nitrogen at temperatures between 300 and 350 °C while thermo-compression bonding experiments were performed under vacuum at 270 °C. During these experiments, the solidification of electrodeposited Au–Sn alloy as well as the interaction of this alloy with W₂N layers are studied. Some supplementary specific brazing experiments were performed using commercial sheets of eutectic Au–Sn alloy in order to understand the mechanisms of interactions between the Au–Sn alloy and the W₂N layer and of solidification of the Au–Sn eutectic alloy. The melting and solidification process of eutectic Au–Sn alloy were studied by differential scanning calorimetry under different geometrical configurations such as commercial eutectic Au–Sn sheets alone, brazing joints performed by commercial eutectic Au–Sn alloy and samples made by thermo-compression bonding. Bonded wafers with good mechanical properties were characterized by cross-section scanning electron microscopy using energy dispersive X-ray mode. Some samples were characterized by transmission electron microscopy. The mechanical strength of the seal was checked by shear tests.     

Low-temperature sol-gel intermediate layer wafer bonding

Silicon-to-silicon wafer bonding has been successfully performed using sol-gel intermediate layer, which is deposited by spinning acid-catalyzed tetraethylthosilicate solution on the surfaces of two silicon wafers to be bonded. The bond strength is up to 35 MPa at a bonding temperature of 100 °C, which is near to the fractured strength of bulk silicon. To investigate the effects of the press parameters, Draper-Lin small composite design is used, as it requires the minimum number of runs in the design of experiments. Statistic analysis shows that the bonding temperature is the dominant factor for the bond quality, while the interaction between bonding temperature and concentration is significant on bond strength. The physical mechanisms of the observed significant effects are discussed. The improvement of the wafer bonding using annealed sol-gel intermediate layer is also proposed.     

Influence of microwave annealing on direct bonded silicon wafers

Strong and nearly void free bonding was achieved using direct bonding followed by microwave annealing. Silicon wafers were cleaned, O₂ plasma surface activated, and bonded at room temperature. After microwave annealing at 400 °C, the bond strength of hydrophilic wafers was found to be in the range between 0.2 and 1.6 J/m². Additional heating of bonded wafers was done at elevated temperatures and for prolonged times using either rapid thermal annealing or microwave annealing. In either case, additional annealing showed no impact on wafer separation area, void, or bond strength. Thus, the initial microwave anneal dictated the ultimate bond strength regardless of subsequent annealing method. The mechanism for wafers bonded in this work involved dipole-dipole bonding and, hydrogen bonding. The initial microwave anneals typically required times less than 60 min. As a result, microwave annealing was shown to be a promising low temperature alternative for wafer bonding when compared to the currently used mechanical furnace anneals.     

Void-free strong bonding of surface activated silicon wafers from room temperature to annealing at 600 °C

In order to investigate the high temperature application of surface activated silicon/silicon wafer bonding, the wafers were bonded at room temperature and annealed up to 600 °C followed by optical, electrical, mechanical and nanostructure characterization of the interface. Void-free interface with high bonding strength was observed that was independent of the annealing temperature. The bonding strength was as high as 20 MPa. The normalized interfacial current density was increased with the increase in the annealing temperature. A thin interfacial amorphous layer with a thickness of 8.3 nm was found before annealing, which was diminished at 600 °C. A correlation between the current density and nanostructure of the interface was observed as a function of the annealing temperature. The high quality silicon/silicon bonding indicates its potential use not only in low temperature microelectronic applications, but also in high temperature harsh environments.     

Surface-mount sapphire interferometric temperature sensor

A fiber-optic high-temperature sensor is demonstrated by bonding a 45 degrees -polished single-crystal sapphire fiber on the surface of a sapphire wafer, whose optical thickness is temperature dependent and measured by white-light interferometry. A novel adhesive-free coupling between the silica and sapphire fibers is achieved by fusion splicing, and its performance is characterized. The sensor's interference signal is investigated for its dependence on angular alignment between the fiber and the wafer. A prototype sensor is tested to 1,170 degrees C with a resolution of 0.4 degrees C, demonstrating excellent potential for high-temperature measurement.     

圆片级气密封装及通孔垂直互连研究

提出了一种新颖的圆片级气密封装结构.其中芯片互连采用了通孔垂直互连技术:KOH腐蚀和DRIE相结合的薄硅晶片通孔刻蚀技术、由下向上铜电镀的通孔金属化技术、纯Sn焊料气密键合和凸点制备相结合的通孔互连技术.整个工艺过程与IC工艺相匹配,并在圆片级的基础上完成,可实现互连密度200/cm2的垂直通孔密度.该结构在降低封装成本,提高封装密度的同时可有效地保护MEMS器件不受损伤.实验还对结构的键合强度和气密性进行了研究.初步实验表明,该结构能够满足MIL-STD对封装结构气密性的要求,同时其焊层键合强度可达8MPa以上.本工作初步在工艺方面实现了该封装结构,为进一步的实用化研究奠定了基础.