A 75 GHz regenerative dynamic frequency divider with active transformer using InGaAs/InP HBT technology

This letter presents a high speed 2:1 regenerative dynamic frequency divider with an active transformer fabricated in 0.7 μm InP DHBT technology with f_T of 165 GHz and f_max of 230 GHz. The circuit includes a two-stage active transformer, input buffer, divider core and output buffer. The core part of the frequency divider is composed of a double-balanced active mixer (widely known as the Gilbert cell) and a regenerative feedback loop. The active transformer with two stages can contribute to positive gain and greatly improve phase difference. Instead of the passive transformer, the active one occupies a much smaller chip area. The area of the chip is only 469×414 μm² and it entirely consumes a total DC power of only 94.6 mW from a single -4.8 V DC supply. The measured results present that the divider achieves an operating frequency bandwidth from 75 to 80 GHz, and performs a -23 dBm maximum output power at 37.5 GHz with a 0 dBm input signal of 75 GHz.     

A 3 mW 54.6 GHz Divide-by-3 Injection Locked Frequency Divider With Resistive Harmonic Enhancement

A 54.6 GHz divide-by-3 injection locked frequency divider with low power consumption is presented. A resistive feedback is implemented to achieve a stable dc input and higher injection efficiency. Compared with the conventional design, it exhibits a better supply voltage rejection and wider locking range while a small silicon area is maintained. Fabricated in a TSMC 65 nm bulk CMOS process, this divider operates from 48.8 to 54.6 GHz and consumes 3 mW from a 0.9 V supply.      

A harmonic injection-locked frequency divider in 0.18-/spl mu/m SiGe BiCMOS

A harmonic injection-locked frequency divider for high-speed applications is presented in this letter. In order to enhance the bandwidth of the high-order frequency division, a positive feedback is employed in the design of the subharmonic mixer loop. The proposed circuit is implemented in a 0.18-/spl mu/m SiGe BiCMOS process. With a singled-ended super-harmonic input injection of 0dBm, the frequency divider exhibits a locking range of 350MHz (from 59.77 to 60.12GHz) for the divide-by-four frequency division while maintaining an output power of -16.6/spl plusmn/ 0.5dBm within the entire frequency range. The frequency divider core consumes a dc power of 50mW from a 3.6-V supply voltage.     

22 GHz 1/4 frequency divider using AlGaAs/GaAs HBTs

A divide-by-four frequency divider using AIGaAs/GaAs HBTs with GalnAs/GaAs emitter cap layers was designed and fabricated. A maximum toggle frequency of 22.15 GHz was obtained at a power supply voltage of 9 V and a total power dissipation of 712 mW. The minimum input signal power was under 0dBm and the free-running frequency was as high as 20 GHz.     

Colpitts Injection-Locked Frequency Divider Implemented With a 3-D Helical Transformer

This letter proposes a wide locking range and low power complementary Colpitts injection-locked frequency divider (ILFD) employing a 3-D helical transformer. The proposed ILFD consists of two single-ended complementary Colpitts oscillators coupled by a 3-D transformer to form a differential oscillator. The aim of using the 3-D transformer is to reduce chip size. The divide-by-2 LC-tank ILFD is implemented by adding an injection nMOS between the differential outputs of the voltage controlled oscillator. The measurement results show that at the supply voltage of 1.8 V, the divider free-running frequency is tunable from 4.24 to 4.8 GHz. At the incident power of 0 dBm, vtune=0.9 V, and V _DD=1.5 V, the locking range is about 2.4 GHz (26.9%), from the incident frequency 7.7 to 10.1 GHz. The core power consumption is 3.9 mW. The die area is 0.548times 0.656 mm².     

A 1-V transformer-feedback low-noise amplifier for 5-GHz wireless LAN in 0.18-/spl mu/m CMOS

A low-noise amplifier (LNA) uses low-loss monolithic transformer feedback to neutralize the gate-drain overlap capacitance of a field-effect transistor (FET). A differential implementation in 0.18-/spl mu/m CMOS technology, designed for 5-GHz wireless local-area networks (LANs), achieves a measured power gain of 14.2 dB, noise figure (NF, 50 /spl Omega/) of 0.9 dB, and third-order input intercept point (IIP3) of +0.9 dBm at 5.75 GHz, while consuming 16 mW from a 1-V supply. The feedback design is benchmarked to a 5.75-GHz cascode LNA fabricated in the same technology that realizes 14.1-dB gain, 1.8-dB NF, and IIP3 of +4.2 dBm, while dissipating 21.6 mW at 1.8 V.     

30 GHz transformer-coupled and reused injection-locked VCO/divider in 0.13 μm CMOS process

A 30 GHz VCO, using a transformer as the tank load and inter-stage coupling of the divider, is proposed such that the inductive load of the buffer between the VCO and the divider is eliminated and therefore chip area and power consumption can be reduced. The transformer is further reused by feedback to enhance the output swing of the VCO. Phase noise performance of the VCO can also be improved by the injection-lock mechanism from the reverse coupling of the divider. Measured results show that output phase noises of the VCO with (without) the divider are -125.1 (-118.6) dBc/Hz at 10 MHz offset frequencies from around 29.2 GHz carrier frequency. The power consumption of the VCO alone is 2.32 mW, while that of the VCO/divider increases only to 4.65 mW.     

Low-power wide-locking-range injection-locked frequency divider for OFDM UWB systems

This paper describes a divide-by-two injection-locked frequency divider (ILFD) for frequency synthesizers as used in multiband orthogonal frequency division multiplexing (OFDM) ultra-wideband (UWB) systems. By means of dual-injection technique and other conventional tuning techniques, such as DCCA and varactor tuning, the divider demonstrates a wide locking range while consuming much less power. The chip was fabricated in the Jazz 0.18 μm RF CMOS process. The measurement results show that the divider achieves a locking range of 4.85 GHz (6.23 to 11.08 GHz) at an input power of 8 dBm. The core circuit without the test buffer consumes only 3.7 mA from a 1.8 V power supply and has a die area of 0.38 × 0.28 mm2. The wide locking range combined with low power consumption makes the ILFD suitable for its application in UWB systems.     

An ultralow power CMOS/SIMOX programmable counter LSI

We designed and fabricated an extremely low-power CMOS/SIMOX programmable counter large scale integrated circuits (LSI) for high-speed phase-locked loop (PLL) frequency synthesizer applications. This was to verify the potential usefulness of ultrathin-film 0.24-μm-gate CMOS/SIMOX process technology for creating an extremely low-power LSI containing high-speed circuits operating at frequencies of at least 1 GHz and at low supply voltages. While operating at up to 2.2 GHz and consuming only 4.5 mW at 1.5 V, it is capable of 4-GHz performance with power consumption of 19 mW at 2.5 V. Even at a low supply voltage of 1.5 V, high input-sensitivity was also achieved in the 1- to 2-GHz frequency range. These low-power and high input-sensitivity characteristics outperform those of state-of-the-art BiCMOS PLL LSIs     

Superharmonic injection-locked frequency dividers

Injection-locked oscillators (ILOs) are investigated in a new theoretical approach. A first-order differential equation is derived for the noise dynamics of ILOs. A single-ended injection-locked frequency divider (SILFD) is designed in a 0.5-μm CMOS technology operating at 1.8 GHz with more than 190 MHz locking range while consuming 3 mW of power. A differential injection-locked frequency divider (DILFD) is designed in a 0.5-μm CMOS technology operating at 3 GHz and consuming 0.45 mW, with a 190 MHz locking range. A locking range of 370 MHz is achieved for the DILFD when the power consumption is increased to 1.2 mW     

Low-power static frequency divider using an InP-based monolithic RTD/HBT technology

A low-power static frequency divider using an RTD/HBT MOnostable-BIstable transition Logic Element (MOBILE) scheme is proposed for the first time and operation of the circuit is demonstrated up to 20 GHz. The divided-by-two static frequency divider has been successfully implemented in an InP-based monolithic RTD/HBT IC technology. The number of devices used in the static frequency divider has been significantly reduced by using the proposed MOBILE scheme. The fabricated frequency divider operates at a clock frequency up to 20 GHz and dissipates d.c. power of 51 mW at a power supply of 3.3 V     

A Low Voltage 0.35$mu$m CMOS FrequencyDivider With the Body Injection Technique

This letter proposes a new CMOS injection locked frequency divider (ILFD) fabricated in a 0.35 mum CMOS process. The ILFD circuit is realized with a cross-coupled CMOS LC-tank oscillator, and the injecticon is carried out through the bodies of cross- coupled transistors. The self-oscillating ILFD is injection-locked by second-(third-) harmonic input to obtain the division order of two (three). Measurement results show that at the supply voltage of 1.5 V and at the incident power of 10 dBm, the locking range is from the incident frequency 6.94 to 8.41 GHz in the divide-by-3 mode and the operation range is from the incident frequency 4.56 to 5.59 GHz in the divide-by-2 mode.     

1.3 V supply voltage 38 GHz static frequency divider

An ultra-low supply voltage and low power dissipation fully static frequency InP SHBT divider operating at up to 38 GHz is reported. The fully differential parallel current switched configuration of D-latch maintains the speed advantages of CML circuits while allowing full functionality at a very low supply voltage. The frequency divider operates at up to 38 GHz at a single-ended input power of 0 dBm. The power dissipation of the toggled D-flip-flop is 8 mW at a power supply voltage of 1.3 V. The authors believe this is the lowest supply voltage for static frequency dividers around this frequency in any technology. This low power configuration is suitable for any digital integrated circuit.     

A 0.8 V low power low phase-noise PLL

A low power and low phase noise phase-locked loop(PLL) design for low voltage(0.8 V) applications is presented.The voltage controlled oscillator(VCO) operates from a 0.5 V voltage supply,while the other blocks operate from a 0.8 V supply.A differential NMOS-only topology is adopted for the oscillator,a modified precharge topology is applied in the phase-frequency detector(PFD),and a new feedback structure is utilized in the charge pump(CP) for ultra-low voltage applications.The divider adopts the extende...     

A Wide Locking Range Differential Colpitts Injection Locked Frequency Divider

This letter proposes a new wideband Colpitts injection locked frequency divider (ILFD) and describes the operation principle of the ILFD. The circuit consists of a differential CMOS LC-tank oscillator and a direct injection topology. The divide-by-two ILFD can provide wide locking range, and the measurement results show that at the supply voltage of 2.4 V, the tuning range of the free running ILFD is from 4.46 to 5.6 GHz, about 1.14 GHz, and the locking range of the ILFD is from 8.03 to 11.63 GHz, about 3.6 GHz, at the injection signal power of 0 dBm. The ILFD dissipates 19.92 mW at a supply voltage of 2.4 V and was fabricated in 1P6M 0.18 mum CMOS process. At the tuning voltage of 1.2 V, the measured phase noise of the free running ILFD is -110.8 dBc/Hz at 1 MHz offset frequency from 4.94 GHz and the phase noise of the locked ILFD is -135.4 dBc/Hz, while the input signal power is -4 dBm.     

A Fully Differential Low-Power Divide-by-8 Injection-Locked Frequency Divider Up to 18 GHz

A low power divide-by-8 injection-locked frequency divider is presented. The frequency divider consists of four current-mode logic (CML) D-latches connected in the form of a four-stage ring with the differential input signal injected into the clock terminals of the latches. The output signals can be taken from the data terminals of any of the four latches. The proposed frequency divider has higher operating frequency and lower power dissipation compared with conventional static frequency dividers. Compared with existing injection-locked frequency dividers, the proposed fully differential frequency divider presents wider locking range with the center frequency independent of injection amplitude. The frequency divider is implemented in TSMC 0.18 mum CMOS technology. It consumes around 3.6 mW power with 1.8 V supply. The operating frequency can be tuned from 4 GHz to 18 GHz. The ratio of the locking range over the center frequency is up to 50% depending on the operating frequency and biasing conditions     

A 40-GHz frequency divider in 0.18-/spl mu/m CMOS technology

An analysis of regenerative dividers predicts the required phase shift or selectivity for proper operation. A divider topology is introduced that employs resonance techniques by means of on-chip spiral inductors to tune out the device capacitances. Configured as two cascaded /spl divide/2 stages, the circuit achieves a frequency range of 2.3 GHz at 40 GHz while consuming 31 mW from a 2.5-V supply.     

Design of 24-GHz 0.8-V 1.51-mW Coupling Current-Mode Injection-Locked Frequency Divider With Wide Locking Range

A 0.8-V CMOS coupling current-mode injection-locked frequency divider (CCMILFD) with 19.5% locking range and a current-injection current-mode logic (CICML) frequency divider have been designed and fabricated using 0.13-$mu{hbox{m}}$ 1p8m CMOS technology. In the proposed CCMILFD, the current-mode technique to minimize the loss of input signals and the coupling circuit to enlarge the phase response have been designed to increase the locking range. The locking range of the fabricated CCMILFD is 4.1 GHz with a power consumption of 1.51 mW from a power supply of 0.8 V. In the proposed CICML frequency divider, the current-injection interface is applied to the current inputs to make the circuit operated at a higher frequency with low power consumption under a low voltage supply. The operation frequency of the fabricated CICML frequency divider can divide the frequency range from CCMILFD and consume 1.89 mW from a 0.8-V voltage supply. The chip core areas of the CCMILFD and CICML frequency divider without pads are 0.23 and 0.015 $ {hbox{mm}}^{2}$, respectively. The proposed circuits can be operated in a low supply voltage with the advantages of a wider locking range, a higher operation frequency, and lower power consumption.      

A novel wideband low phase noise 2:1 frequency divider

This paper describes a novel low-power wideband low-phase noise divide-by-two frequency divider.Hereby,a new D-latch topology is introduced.By means of conventional dynamic source-coupled logic techniques,the divider demonstrates a wideband with low phase noise by adding a switch transistor between the clock port and the couple node of the input NMOS pair in the D latch.The chip was fabricated in the 90-nm CMOS process of IBM.The measurement results show that the frequency divider has an input frequency range from 0.05 to 10 GHz and the phase noise is-159.8 dBc/Hz at 1 MHz offset from the carrier.Working at 10 GHz,the frequency divider dissipates a total power of 9.12 mW from a 1.2 V supply while occupying only 0.008 mm2 of the core die area.     

A low-power 72.8-GHz static frequency divider in AlInAs/InGaAs HBTtechnology

We report a 72.8-GHz fully static frequency divider in AlInAs/InGaAs HBT IC technology. The CML divider operates with a 350-mV logic swing at less than 0-dBm input power up to a maximum clock rate of 63 GHz and requires 8.6 dBm of input power at the maximum clock rate of 72.8 GHz. Power dissipation per flip-flop is 55 mW with a 3.1-V power supply. To our knowledge, this is the highest frequency of operation for a static divider in any technology. The power-delay product of 94 fJ/gate is the lowest power-delay product for a circuit operating above 50 GHz in any technology. A low-power divider on the same substrate operates at 36 GHz with 6.9 mW of dissipated power per flip-flop with a 3.1-V supply. The power delay of 24 fJ/gate is, to our knowledge, the lowest power-delay product for a static divider operating above 30 GHz in any technology. We briefly review the requirements for benchmarking a logic family and examine the historical trend of maximum clock rate in high-speed circuit technology