高温偏压对混合集成电路中环氧粘接性能的影响

本文针对混合集成电路组装过程中，某些热导率较高的环氧粘接剂在高温加电老化条件下出现的局部变色现象开展实验研究，对选购的粘接剂设计特定测试样品，通过加速高温加电老化实验，研究局部变色“电迁移”现象与样品类型（添加物成分）和几何、温度等因素的关系。采用微观分析方法证明局部变色现象与Fe、Ni等杂质离子迁移有关。本研究工作为后续粘接剂的选型及使用提供指导及实验依据。     

利用新型合成仪器解决系统级测试难题

当今世界电子元件及产品正在加速发展，在大多数商业应用中，从设计到生产的周期现已缩短为只有六个月。而且，设备的内容及拓朴结构已经从单一功能元件迁移到多功能元件，进而还会迁移到整个子系统和系统中，在迁移时通常采用单个组件方案的形式（例如，用于智能电话和iPhone之类的设备）。现在，对于多载波功率放大器（MCPA）和软件定义的无线电（SDR）而言，直接软件控制和设备配置已司空见惯。例如RFIC之类的设备只能在混合信号环境中及实时条件下操作和测试。     

电迁移测试中模型参数估计方法的比较

电迁移（Electro—Migration,EM）是集成电路可靠性研究的重要项目之一。本文基于JESD63,基于最小二乘法（LSE）和基于极大似然估计（MLE）来研究不同的统计方法对电迁移的样本估计（t50,σ）和模型参数估计（Ea,n）的影响,并列举了不同统计方法在不同情况下的应用。为电迁移的数据分析提供了更多更灵活的处理方法,此外,对TDDB（Time Dependent Dielectric Breakdown）的参数估计同样适用。     

长电科技向Eagle Test Systems购买多种测试平台用于扩大生产

Eagle Test Systems,Inc.面向半导体行业设计、生产、销售和维修高性能的自动化测试设备。7月19日宣布,半导体封装测试服务的全球供应商及中国境内领先的转包合同制造商江苏长电科技股份有限公司（简称“长电科技”）造商江苏长电科技股份有限公司（简称“长电科技”）（上海股票交易所股票代码：600584）已为其新的生产厂购买了多台Eagle ETS-200和ETS-364模拟和混合信号测试仪，该新厂位于上海以西约150公里处的江阴市。     

北京博电借助Xilinx FPGA炙什最新智能电网测试设备

AllProgrammable技术和器件的全球领先企业赛灵思公司（NASDAQ：XLNX）近日宣布北京博电新力电气股份有限公司（PONOVOPOWERCO．，LTD简称北京博电）通过采用赛灵思Virtex-6和Spartan-6FPGA，以创纪录的速度成功向市场交付了其最新系列高端智能继电保护测试仪——PNF800系列和便携数字测试设备——PNS600系列。PNF800的研制成功不但提升了保护测试领域内的技术水平，同时也引领了整个行业的技术发展趋势，使得北京博电继在行业内首次提出”智能测试”的概念之后，率先把概念变成了现实，把国内的测试仪设备一举从光数字测试时代引入了智能测试时代。     

MTBF预计值用于定时截尾试验方案的选择

提出选择定时截尾可靠性鉴定试验方案性，引入平均故障间隔时间（MTBF）预计值θp，通过计算定时截尾试验方案的接收概率，并结合试验时间和试验经费，科学，合理地选定定时截尾可靠性鉴定试验方案。     

离子迁移的机理、危害和对策

概述了在印制板中“离子迁移”（CAF）漏电的机理、危害和对策。明确提出PCB走向高密度化和信号传输高频化的条件下,“离子迁移”漏电将走向严重化,要求进行CAF的测试与管控的重要性。     

VLSI的电迁移及其微测试技术

本文叙述了VLSI的性质,讨论了电迁移的微测试技术,包括噪声测试快速评估电迁移.标准晶片级电迁移加速试验,互连接触孔的电迁移检测以及应用标准测试结构控制金属膜的电迁移.     

指数分布阶段增长模型

在对产品作m个阶段的可靠性增长试验中，设产品在第i阶段发生的故障数为Zi，试验时间为，；即有（Zi,τi）i=1，2……m。若产品在各阶段的寿命都服从指数分布，且满足阶段顺序约束条件，即其平均寿命满足：或失效率λi满足：则可以采取如下的Bayes方法，对产品的平均寿命或失效率进行增长的区间估计。（1）检验阶段增长条件对于时间截尾，计算统计量对于故障截尾，计算统计量若（时间截尾）或（故障截尾），则认为从1到2阶段有显著的可靠性增长，否则将两个阶段的数据合并。对于多阶段（m＞2）的情况可依次类推。这里是自由度为f1，f2的F…     

基于RFSM的健壮性测试技术研究

提出了一种系统实现协议健壮性测试的方法，该方法首先在分析BGP协议状态机的基础上，认为基本FSM对功能部分和健壮性处理部分未能严格区分。要提高FSM的健壮性，就需要通过增加状态、迁移和事件的基础上构造具有健壮性处理过程的RFSM（robustness finite state machines），把RFSM模型应用到BGP健壮性测试当中，文章详细构造了BGP冲击集合和RFSM，生成了反向测试集，并对测试特征序列和测试预言等问题进行了讨论。Cisco7200实际测试应用表明，用该方法生成的测试集与一致性测试集相比，其错误处理的覆盖率扩大了54％，检错能力提高了2．8倍。     

宇航元器件搭载试验研究与实践

元器件搭载是国内外航天器,特别是新技术试验卫星中的一类重要试验项目,也是推动元器件成熟和宇航应用的重要手段。从元器件搭载试验验证体制、天地联合验证方法、试验组织、试验结论发布和应用等方面,对元器件搭载试验提出了总体策略,对搭载试验任务内容和要求进行了分析,总结了元器件搭载试验的实践。研究工作对我国宇航元器件搭载试验相关工作具有较高的参考价值。     

The Role of Test Protocols in Automated Test Generation for Embedded-Core-Based System ICs

Modular testing is an attractive approach to testing large system ICs, especially if they are built from pre-designed reusable embedded cores. This paper describes an automated modular test development approach. The basis of this approach is that a core or module test is dissected into a test protocol and a test pattern list. A test protocol describes in detail how to apply one test pattern to the core, while abstracting from the specific test pattern stimulus and response values. Subsequent automation tasks, such as the expansion from core-level tests to system-chip-level tests and test scheduling, all work on test protocols, thereby greatly reducing the amount of compute time and data involved. Finally, an SOC-level test is assembled from the expanded and scheduled test protocols and the (so far untouched) test patterns. This paper describes and formalizes the notion of test protocols and the algorithms for test protocol expansion and scheduling. A running example is featured throughout the paper. We also elaborate on the industrial usage of the concepts described.     

Stochastic testing of processing cores in a many-core architecture

A promising solution to reliability challenges in nano-scale fabrication technologies is self-test and reconfiguration. In this direction, we propose an autonomous test mechanism for online detection of permanent faults in many-core processors. Several hardware test components are incorporated in the many-core architecture. Some of these components distribute software-based self-test routines among the processing cores and make each test routine accessible for a limited amount of time. A processing core that has an idle slot executes the test routine, otherwise it skips it without loss of test continuity. Several components of the proposed test architecture monitor behavior of the processing cores during execution of test routines, detect faulty cores, and make their omission from the system possible. We propose the use of an extended form of Petri NET modeling method to model and analyze the proposed test mechanism and tune our test architecture to preserve quality of test, and at the same time, manage the overall test time. Our experimental results show that test time and hardware overhead of the proposed test mechanism are low and its performance overhead is zero. Furthermore, the proposed test architecture can efficiently scale to a many-core with a large number of processing cores.     

数字T/ R 组件自动测试系统的设计

数字T/ R 组件是数字阵列雷达的重要组成部分,由于其集成度高、测试项目多,所以在研发生产中需要使用自动测试系统。文中针对数字T/ R 组件的测试需求,介绍了一种自动测试系统,内容包括硬件设计方案、参数的测试方法以及系统集成和试验,该系统已应用于数字T/ R 组件的测试。     

A knowledge-based test generator for standard cell and iterative array logic circuits

The use of Prolog for test generation is discussed and an implementation in Prolog of an automatic test generator, Protean, for stuck-at faults in scan-designed standard cell VLSI circuits and iterative logic arrays is described. Protean comprises a cell test generator, which generates test knowledge and propagation characteristics for cells, and a hierarchical test generator, which uses this high-level test knowledge in conjunction with low-level structural information to generate tests for the circuit.<>     

IEEE Standard 1500 Compatible Delay Test Framework

Rapid advances in semi-conductor technology have made timing-related defects increasingly crucial in core-based system-on-chip designs. Currently, modular test strategies based on IEEE Standard 1500 are applied to test the functionality of each embedded core in system-on-chip (SoC) designs but fail to verify the corresponding timing specifications. In this paper, to achieve high quality of delay tests, hardware implementation of an embedded Delay Test Framework including the modified test wrappers and the Embedded delay test mechanism is presented to build an entirely embedded delay test environment where at-speed clock is applied inside the chip to increase test accuracy. Additionally, the proposed delay test framework is capable of supporting all current solutions of core-based delay test. The experimental results successfully demonstrate the delay testing application using the proposed framework to a Crypto Processor with satisfying test quality and effectiveness.      

EPA协议中事件服务的实现和测试

EPA是我国第一个拥有自主知识产权并被国际电工委员会（IEC）认可的工业自动化领域国际标准。本文在严格按照EPA标准完全实现EPA事件服务组以及深入理解EPA协议一致性测试原理的基础上,着重研究了EPA协议中关于报警的事件服务的测试方法,提出了一种测试EPA事件服务的一致性测方法。测量中主机作为控制台,控制测试流程、设置测试参数,以及显示结果,测试代理借助协议栈的通信能力与主机测试软件进行测试命令的交互。     

Revised test that a distribution is new better than used

The modified test of NBU-ness given by Green and Tiwari (1) related to more general null and alternative hypotheses than the corresponding test given by Hollander and Proschan (2). The Green and Tiwari test used an upper bound for the basic of the basic criterion, resulting in the test not being very powerful. In this revised test, suitable estimate of the variance is used instead of an upper bound. This is appropriate because a large sample size is assumed. The resulting test is more powerful than the earlier Green-Tiwari test, and more generally applicable than the Hollander-Proschan test.     

基于TTCN的测试执行方法及其应用

测试执行是协议一致性测试系统中的主要部分，本文提出一种基于测试描述语言ＴＴＣＮ的操作语义对标准测试集进行了解释执行的测试执行方法，利用这种方法所实现的一致性测试系统具有很强的灵活性和独立性，同时大大提高了测试的效率，另外，我们还介绍了基于这种测试方法所完成的协议一致性测试系统（ＰＣＴＳ）的总体结构，设计思想以及测试配置。