A methodology for the design of SFS/SCD circuits for a class of unordered codes

We present two design methods that produce concurrently testable and cascadable combinational blocks for a given logic function. In the first method, the designed block is strongly fault-secure and code-disjoint. Any unordered coding scheme can be used for the input and output. The second method produces designs that are strongly fault-secure and strongly code-disjoint. Here the encoding requires some simple density properties that are seen to be satisfied by the commonly used coding schemes. This makes the method applicable to a larger class of coding schemes than the existing methods. We also show that our designs have lower hardware overhead.     

Approach to partially self-checking combinational circuits design

This paper presents a cost-effective, non-intrusive technique of partially self-checking combinational circuits design. The proposed technique is similar to duplication with comparison, wherein duplicated function module and comparator act as a function checker that detects any erroneous response of the original function module. However, instead of realizing checker with full error-detection capability, we select a subset of erroneous responses to implement partial, but simplified function checker. A heuristic procedure that tries to find the optimal sum-of-product expression for partial function checker that minimizes its area while providing specified error coverage is described here. Effectiveness of the technique is evaluated on a set of MCNC 91 benchmark combinational circuits.     

Evaluating the safety of self-checking circuits

In this paper, we consider the evaluation of the safety of a self-checking circuit with combinational logic. Since the circuit is tested under normal operation, it may stay in different states such as a perfect state in which any erroneous output can be detected, unstable states in which an erroneous output may be detected or may not, a safe-state when the erroneous output has been caught, and a fail-state because the erroneous output is undetected, as time goes on. Consequently, we propose a fail-safe evaluation, using a Markov model to describe the state transitions and predicate the probability of the circuit not being in the fail-state.We include a comparison with existing evaluation methods, the proposed approach being more practical because it estimates the safety of the circuit, which is reducing as time goes on, instead of giving a constant probability measure.This work was supported in part by Research Grant No. 5711 from the Natural Sciences and Engineering Research Council of Canada and by an equipment loan from the Canadian Microelectronics Corporation.     

Efficient Totally Self-Checking Shifter Design

Self-checking designs will gain increasing interest in industrial applications if they satisfy the following requirements: high fault coverage, reduced hardware cost and reduced design effort. This work is aimed to reach these requirements for the design of self-checking shifters and is part of a broader project concerning the design of self-checking data paths.     

基于Bose-Lin码的组合电路容错设计

应用Bose-Lin码实现了特定功能的组合电路容错设计，并采取在输入输出端加入缓存的方法，当电路出现故障时可以使系统恢复正常工作。为了方便电路的扩展，还进一步优化了输入输出端缓存的结构。     

Concurrent Delay Testing in Totally Self-Checking Systems

Prompt detection of even small delay faults, sometimes before causing critical paths to fail, gains importance since stricter test quality requirements for high performance and high density VLSI circuits have to be satisfied in critical applications. This can be achieved by using concurrent delay testing.In this paper a novel idea for concurrent detection of two-rail path delay faults is introduced. It is shown that TSC two-rail code error indicators that monitor pairs of paths with similar propagation delays can be used for concurrent delay testing. Our technique is applied to TSC two-rail code checkers as well as to duplication systems which are the most widely used TSC systems. The design of TSC two-rail code checkers and TSC duplication systems with respect to two-rail path delay faults is achieved for first time in the open literature.     

Design of self-testing and on-line fault detection combinational circuits with weakly independent outputs

In this article we propose a structure dependent method for the systematic design of combinational selftesting fault detection circuits that is well adapted to the arbitrarily chosen technical fault model. According to the fault model considered the outputs of the circuit are partitioned into different generally nondisjoint groups of weakly independent outputs. The parities of these groups of weakly independent outputs are compared in test mode as well as in normal operation mode with the corresponding predicted parities by use of a self-checking checker. For on-line detection, the hardware is in normal operation mode, and for testing, it is in test mode. In the test mode, these fault detection circuits guarantee a 100% fault coverage for single stuck-at-0/1 faults and a high fault coverage for arbitrary faults. In normal operation mode all technical faults considered will be detected possibly, with some degree of latency.Partially presented at the VLSI Test Symposium, Atlantic City, 1992.     

Modular implementation of efficient self-checking checkers for the Berger code

A technique for designing efficient checkers for conventional Berger code is proposed in this paper. The check bits are derived by partitioning the information bits into two blocks, and then using an addition array to sum the number of 1's in each block. The check bit generator circuit uses a specially designed 4-input 1's counter. Two other types of 1's counters having 2 and 3 inputs are also used to realize checkers for variable length information bits. Several variations of 2-bit adder circuits are used to add the number of 1's. The check bit generator circuit uses gates with fan-in of less than or equal to 4 to simplify implementation in CMOS. The technique achieves significant improvement in gate count as well as speed over existing approaches.     

Efficient UBIST implementation for microprocessor sequencing parts

In this paper we first present an improved self-checking solution for the sequencing part of the Motorola MC 68000 microprocessor. compared to previous self-checking proposals for this microprocessor, the present scheme decreases the area overhead and simplifies the complexity of both functional circuits and checkers. In addition, the unified BIST method introduced recently, is applied to this scheme. This method uses a merging of self-checking and BIST techniques and allows a high fault coverage for all tests needed for the integrated circuits, e.g. off-line test for fabrication faults and for maintenance, and on-line concurrent error detection in the field.     

Synthesis of Circuits with Low-Cost Concurrent Error Detection Based on Bose-Lin Codes

This paper presents a procedure for synthesizing sequential machines with concurrent error detection based on Bose-Lin codes. Bose-Lin codes are an efficient solution for providing concurrent error detection as they are separable codes and have a fixed number of check bits, independent of the number of information bits. Furthermore, Bose-Lin code checkers have a simple structure as they are based on modulo operations. Procedures are described for synthesizing circuits in a way that their structure ensures that all single-point faults can only cause errors that are detected by a Bose-Lin code. This paper presents an efficient scheme for concurrent error detection in sequential circuits with no constraint on the state encoding. Concurrent error detection for both the state bits and the output bits is based on a Bose-Lin code and their checking is combined such that one checker suffices. Results indicate low area overhead. The cost of concurrent error detection is reduced significantly compared to other methods based on other codes.     

Multiple fault detection in two-level multi-output circuits

It is often stated that in irredundant two-level logic circuits, a test set for all single stuck faults will also detect all multiple stuck faults. We show by a simple example that this result does not hold for multi-output circuits even when each output function is prime and irredundant. Using a result from the programmable logic array technology, we give an output ordering constraint that, if satisfied during test generation, will make a single stuck fault test set a valid multiple stuck fault test set for irredundant two-level multi-output circuits.     

Logical redundancies in irredundant combinational circuits

Some new types of logical redundancies that can occur in a combinational network are investigated. Three kinds of redundancy, namely a-redundancy, b-redundancy and c-redundancy are already well-known. This article presents two new types of redundancy called p-redundancy and n-redundancy in combinational networks which are otherwise known to be irredundant. A combinational circuit is calledp-redundant (n-redundant), if it is possible to realize the same function by permuting (inverting) some input terminals, in the presence of certain stuck-at faults in the circuit.     

钟控神经MOS管的改进及其在多值电路中的应用

首先对钟控神经MOS管进行研究,提出了相应的改进方法.然后采用此改进的钟控神经MOS管设计了一种新型多值触发器.与传统的触发器相比较,此多值触发器具有结构简单、速度快、功耗低等特点;而且无需改变电路结构就可实现不同基的多值触发器.PSPICE模拟证明了所设计的电路具有正确的逻辑功能.     

Large scale,flexible organic transistor arrays and circuits based on polyimide materials

Polyimide (PI) materials are lightweight, flexible, resistant strongly to heat and chemicals, and have been widely used in electronics industry such as working as electronic packaging materials in large-scale integrated circuits. In this letter, PI materials, for the first time, are introduced into organic field-effect transistors (OFETs) and circuits as insulator layers in order to be compatible with the photolithography process. Moreover, a novel method is developed to make the PI films strong enough to endure the critical processes of photolithography (e.g., the influence of developer on polyimide layer). Based on the intact PI insulator and the modified photolithographic technique, large scale, flexible transistor arrays and circuits were fabricated with high resolution and high performance (mobility up to 0.55 cm² V⁻¹ s⁻¹ for bottom-contact bottom-gate OFETs). It provides a new way for the fabrication of large-area organic devices and circuits beyond solution printed techniques, especially for the application of organic semiconductors with poor solubility, e.g., pentacene.     

Organic integrated circuits using room-temperature sintered silver nanoparticles as printed electrodes

Organic integrated circuits based on organic thin-film transistor (TFT) devices are fabricated with solution-based electrodes by using dense inks of silver nanoparticles, which can be sintered at room-temperature. The TFT devices fabricated at a sintering temperature of 30 °C exhibit good electrical characteristics. There is a strong relation between the sintering temperature of silver nanoparticle inks and transistor characteristics. A work function of silver electrodes can be controlled by changing the sintering temperature of silver nanoparticle inks, thereby threshold voltage of fabricated TFT devices are shifted accordingly. Fabricated pseudo-CMOS inverter circuits are successfully operated at low voltage with small hysteresis, and large gains are obtained. These results suggest that printed organic TFT devices fabricated with a low-temperature process enable large-area and low-cost integrated circuits by using these techniques in future applications.     

A Totally Self-Checking 1-out-of-3 Code Error Indicator

In this paper, an asynchronous TSC 1-out-of-3 (1/3) code error indicator is introduced that memorizes erroneous 1/3 code inputs 000, 011, 101, 110, 111 with time duration greater than a discrimination time T. Such an error indicator is used to discriminate transient erroneous 1/3 code inputs from real ones as well as to detect faults that cause logical errors and delay faults (short or long) altering the circuit delay outside its specified limits (upper or lower bounds) without causing logical errors. To our knowledge, this error indicator is the first TSC 1/3 code error indicator proposed in the open literature.     

Testability and test generation for majority voting fault-tolerant circuits

The testability of majority voting based fault-tolerant circuits is investigated and sufficient conditions for constructing circuits that are testable for all single and multiple stuck-at faults are established. The testability conditions apply to both combinational and sequential logic circuits and result in testable majority voting based fault-tolerant circuits without additional testability circuitry. Alternatively, the testability conditions facilitate the application of structured design for testability and Built-In Self-Test techniques to fault-tolerant circuits in a systematic manner. The complexity of the fault-tolerant circuit, when compared to the original circuit can significantly increase test pattern generation time when using traditional automatic test pattern generation software. Therefore, two test pattern generation algorithms are developed for detecting all single and multiple stuck-at faults in majority voting based circuits designed to satisfy the testability conditions. The algorithms are based on hierarchical test pattern generation using test patterns for the original, non-fault-tolerant circuit and structural knowledge of the majority voting based design. Efficiency is demonstrated in terms of test pattern generation time and cardinality of the resulting set of test patterns when compared to traditional automatic test pattern generation software.     

Design of Embedded Self-Testing Checkers for t-UED and BUED Codes

In this article we present a new method for designing self-testing checkers for t-UED and BUED codes. The main idea of this method is to map words of the considered code to words of a code of the same type in which the value of t or the number of check bits is reduced and repeating this with the obtained words until a parity code is obtained, or to translate the code words into words of a code for which such a mapping is possible. First we consider Borden codes for t = 2 ^k – 1, Bose, and Bose-Lin codes. The mapping operation is realized by averaging weights and check symbol values of the code words. The resulting checkers have a simple and regular structure. This structure is independent on the set of code words that is provided by the circuit under check. The checkers are very well suited for use as embedded checkers since they are self-testing with respect to single stuck-at faults under very weak assumptions. All three checker types can be tested with 2 or 3 code words. We also propose a novel approach to design checkers for Blaum codes that require much less code word tests than existing solutions.     

A switch-level test generation system for synchronous and asynchronous circuits

A switch-level test generation system for synchronous and asynchronous circuits has been developed in which a new algorithm for fully automatic switch-level test generation and an existing fault simulator have been integrated. For test generation, a switch-level circuit is modeled as a logic network that correctly models the behavior of the switch-level including bidirectionality, dynamic charge storage, and ratioed logic. The algorithm is able to generate tests for combinational and sequential circuits. BothnMOS and CMOS circuits can be modeled. In addition to the classical line stuck-at faults, the algorithm is able to handle stuck-open and stuck-closed faults on the transistors of the circuit.In synchronous circuits, the time-frame based algorithm uses asynchronous processing within each clock phase to achieve stability in the circuit and synchronous processing between clock phases to model the passage of time. In asynchronous circuits, the algorithm uses asynchronous processing to reach stability within and between modules. Unlike earlier time-frame based test generators for general sequential circuits, the test generator presented uses the monotonicity of the logic network to speed up the search for a solution. Results on benchmark circuits show that the test generator outperforms an existing switch-level test generator both in time and space requirements. The algorithm is adaptable to mixed-level test generation.