High-performance InGaAs junction field-effect transistor with P/Beco-implanted gate

InGaAs junction field-effect transistors (JFETs) are fabricated in metalorganic chemical-vapor-deposition (MOCVD)-grown n-InGaAs and semi-insulating Fe:InP layers on n⁺-InP substrate with a P/Be co-implanted p⁺ self-aligned gate. The device exhibits a transconductance of 245 mS/mm (intrinsic transconductance of 275 mS/mm) at zero gate bias and good pinch-off behavior for a gate length of 0.5 μm. The effective electron velocity is deduced to be 2.8×10⁷ cm/s, equal to the theoretical prediction     

A high current gain 4H-SiC NPN power bipolar junction transistor

This work reports the development of high power 4H-SiC bipolar junction transistors (BJTs) by using reduced implantation dose for p+ base contact region and annealing in nitric oxide of base-to-emitter junction passivation oxide for 2 hours at 1150/spl deg/C. The transistor blocks larger than 480 V and conducts 2.1 A (J/sub c/=239 A/cm/sup 2/) at V/sub ce/=3.4 V, corresponding to a specific on-resistance (R/sub sp on/) of 14 m/spl Omega/cm/sup 2/, based on a drift layer design of 12 /spl mu/m doped to 6/spl times/10/sup 15/cm/sup -3/. Current gain /spl beta//spl ges/35 has been achieved for collector current densities ranging from J/sub c/=40 A/cm/sup 2/ to 239 A/cm/sup 2/ (I/sub c/=2.1 A) with a peak current gain of 38 at J/sub c/=114 A/cm/sup 2/.     

A semi-insulated gate gallium-arsenide field-effect transistor

Proton bombardment has been used to make a semi-insulated gate gallium-arsenide field-effect transistor. This technique combines the simplicity of the metal semiconductor FET technique, the advantage of operating the device using positive as well as negative bias on the gate, and the possible use of higher conductivity material for the channel, which may result in a higher transconductance and a higher saturated current density.     

InGaAs metal-semiconductor field-effect transistor withLangmuir-Blodgett deposited gate structure

A high-transconductance n-channel, depletion-mode InGaAs metal-semiconductor field-effect transistor (MESFET) with a Langmuir-Blodgett deposited gate fabricated on organometallic chemical vapor deposition (OMCVD)-grown InGaAs lattice matched to InP is reported. The fabrication process is similar to epitaxial GaAs FET technology and is suitable for making optoelectronic integrated circuits (OEICs) for long-wavelength fiber-optic communications systems. Devices with 1-μm gate and 6×10¹⁶ channel doping achieved 162-mS/mm extrinsic transconductance and -1.8-V pinch-off voltage. The effective saturation velocity of electrons in the channel was measured to be between 3.5 and 3.9×10⁷ cm/s. The drain current ( I_dss), 300 mA/mm at V_ds=2.5 V, is the highest current capability reported for depletion-mode InGaAs MESFET devices with low pinch-off voltages     

Charge-storage junction field-effect transistor

A charge-storage junction FET (CSJFET) has been developed which is capable of storing a charge in its gate region. The storage time can be varied in the orders of several seconds to less than one microsecond by illumination or by hole injection. This function is given by the double-layered structure of the gate region. The stored negative space charge in the floating gate region controls the channel conductance of a CSJFET. An illumination-time convertor and a variable delay-time controller are the basic applications. CSJFET's can easily be fabricated by the bipolar-IC technology.     

4H-SiC normally-off vertical junction field-effect transistor with high current density

4H-silicon carbide (SiC) normally-off vertical junction field-effect transistor (JFET) is developed in a purely vertical configuration without internal lateral JFET gates. The 2.1-/spl mu/m vertical p/sup +/n junction gates are created on the side walls of deep trenches by tilted aluminum (Al) implantation. Normally-off operation with blocking voltage V/sub bl/ of 1 726 V is demonstrated with an on-state current density of 300 A/cm/sup 2/ at a drain voltage of 3 V. The low specific on-resistance R/sub on-sp/ of 3.6 m/spl Omega/cm/sup 2/ gives the V/sub bl//sup 2//R/sub on-sp/ value of 830 MW/cm/sup 2/, surpassing the past records of both unipolar and bipolar 4H-SiC power switches.     

A bilayer graphene nanoribbon field-effect transistor with a dual-material gate

This paper introduces dual-material gate (DMG) configuration on a bilayer graphene nanoribbon field-effect transistor (BLGNRFET). Its device characteristics based on nonequilibrium Green׳s function (NEGF) are explored and compared with a conventional single-material gate BLGNRFET. Results reveal that an on-off ratio of up to 10 is achievable as a consequence of both higher saturation and lower leakage currents. The advantages of our proposed DMG structure mainly lie in higher carrier transport efficiency by means of enhancing initial acceleration of incoming carriers in the channel region and the suppression of short channel effects. Drain-induced barrier lowering, subthreshold swing and hot electron effect as the key short channel parameters have been improved in the DMG-based BLGNRFET.     

An ion-implanted Schottky-barrier gate field-effect transistor

Techniques of fabricating an n-channel silicon field-effect transistor using phosphorus ion implantation and a platinum silicide Schottky-barrier gate (SB-FET) have been developed. The platinum silicide Schottky-barrier top gate is part of the contact metallization process. The phosphorus-doped channel is obtained by using a 50-keV ion-implanted predeposition and an 1100°C drive-in. A range of implantation doses and drive-in times were used to achieve various SB-FET characteristics. A threshold/pinchoff voltage range of +0.4 to -7.5 V has been obtained with typical spreads of approximately 0.1 V across the slice. A positive threshold voltage represents a SB-FET that is normally off and is turned on by a forward-biased gate. Results have been obtained for     

A stable indium-phosphide diffused junction field-effect transistorwith high gain and low leakage

The fabrication and performance of a JFET which is made by diffusing zinc into an epitaxial channel of indium phosphide grown by MOCVD on a semi-insulating InP(Fe) substrate are presented. The total gate length is 2.4 μm. At 0-V gate bias the transconductance is 140 mS/mm, the gate-source capacitance is 3.0 pF/mm, and the output conductance is less than 0.5 mS/mm. At -2-V gate bias the leakage from gate to source is 4 nA/mm. The drift in drain-source current is less than ±1% after 10⁶ s under continual DC bias     

j-MOS: A versatile power field-effect transistor

A novel field-effect transistor (FET) structure that is attractive for power control applications is proposed and demonstrated. It combines MOSFET structural features and junction FET function in a simple, self-aligned structure that we refer to as j-MOS. Lateral j-MOS transistors were fabricated in silicon-on-sapphire (SOS) with on-resistance as low as 2.5 Ω in 1 cm of channel width. From this result, we project that a vertical version of j-MOS can be fabricated in silicon-on-buried insulator (SOI) with a specific on-resistance ≤ 1 m Ω.cm², approximately a factor of two improvement over current power FET technology.     

Organic field-effect transistor with extended indium tin oxide gate structure for selective pH sensing

In this study, organic field-effect transistors (OFETs) with extended gate structure were fabricated for selective pH sensing applications. Indium tin oxide (ITO) was used as extended gate electrode as well as an active layer for H⁺ sensing. The threshold voltage of the fabricated ion-selective OFET was varied by the changes in the electrochemical potential at the ITO electrode surface upon its exposure to buffer solutions with variable pH values. The sensor showed excellent linearity and a high sensitivity of 57–59 mV/pH in the pH range of 2–12. The selectivity of the ITO sensing layer to H⁺ ions was also investigated by measuring the interfering effect of Ca²⁺ and K⁺ ions in the buffer pH solutions. The results showed that the Ca²⁺ and K⁺ ions weakly interfere with the selective pH sensing of the ITO-extended gate OFET sensor device.     

A PNPN tunnel field-effect transistor with high-k gate and Iow-k fringe dielectrics

A PNPN tunnel field effect transistor(TFET) with a high-k gate dielectric and a low-k fringe dielectric is introduced.The effects of the gate and fringe electric fields on the TFET’s performance were investigated through two-dimensional simulations.The results showed that a high gate dielectric constant is preferable for enhancing the gate control over the channel,while a low fringe dielectric constant is useful to increase the band-to-band tunneling probability.The TFET device with the proposed structure has good switching characteristics,enhanced on-state current,and high process tolerance.It is suitable for low-power applications and could become a potential substitute in next-generation complementary metal-oxide-semiconductor technology.     

Normally-off InGaAs junction field-effect transistor with InGaAs buffer layer

InGaAs junction field-effect transistors (JFET's) with 1-µm gate length were successfully fabricated with an n⁺-InGaAs active layer (8 × 10¹⁶cm^-3) and an undoped InGaAs buffer layer grown on semi-insulating InP:Fe substrate by liquid-phase epitaxy. The device showed good pinch-off behavior with a threshold voltage of 0.25 V, a low drain current of 1 µA at zero gate-source voltage, and a very high transconductance of 553 mS/mm at room temperature. This is one of the highest transconductance values ever reported for a 1-µm gate-length FET.     

High-frequency noise of the junction field-effect transistor

Based on Geurst's treatment of the high-frequency value of the admittances of the junction field-effect transistor, the high-frequency noise of the device has been computed, assuming that the noise source is of thermal origin. By applying an appropriate series expansion of the current it is possible to express the noise of the drain and gate current in terms of known quantities, as steady-state transconductance, gate capacitance, and frequency. At low frequencies the noise spectrum of the drain current is independent of the frequency and is much larger than the noise of the gate current; however, at high frequencies the noise spectra of the gate and drain current both vary by ω²and are of the same order of magnitude.     

Input capacity of a junction field-effect transistor

A new expression is obtained for the input capacity of a junction field-effect transistor (JFET) in the prepinch-off region, by taking into consideration the effect of field-dependent mobility.     

Channel shape in a insulated gate field-effect transistor

By defining the channel thickness of an IGFET in terms of the total mobile charge in the channel, it is shown that the channel thickness decreases with increasing surface field and increases from source to drain, being undefined beyond the pinch-off point if the IGFET is operated in saturation.     

A new LDD transistor with inverse-T gate structure

A new submicrometer inverse-T lightly doped drain (ITLDD) transistor structure for alleviating hot-electron effects is demonstrated. A thin extension of the polysilicon gate under the oxide sidewall spacer is formed, giving the gate cross section the appearance of an inverted letter T. Due to the unique self-aligned n+ T-to-gate feature facilitated by the conducting polysilicon extension, the "spacer-induced degradation" existing in a conventional LDD transistor is eliminated in ITLDD devices. This allows the use of low n- LDD doses for optimum channel electric field reduction and minimum post-implant drive-in for future VLSI compatibility. Submicrometer ITLDD transistors with good transconductance and hot-electron reliability have been achieved. The new ITLDD transistor offers a promising device structure for future VLSI applications.     

V-groove power junction field-effect transistor for v.h.f. applications

A new high-power, high-frequency junction field-effect transistor with a nonplanar V-shaped channel fabricated by preferential etching of ?100? silicon is described. The structure of this transistor is very simple, requires only three photolithographic masking steps and results in a very high packing density. A device having an effective channel length of 2 ?m was fabricated. This transistor exhibits a low-frequency transconductance of 9.6 mS/mm, a cutoff frequency of 0.9 GHz and an output power density of 25 W/mm2 of chip area.     

Harmonic distortion in the junction field-effect transistor with field-dependent mobility

It has been found that a harmonic analysis of the usual power-law transfer characteristic of the JFET does not yield equations which accurately predict the third-harmonic distortion products for short-gate structures. However, if field-dependent mobility in the drain-source channel is taken into consideration in the equations for the drain current, a transfer characteristic is obtained of the form3Z_{D}(1-e^{-r})/ Gamma^{2}, where ZDis the normalized channel height and Γ is the field factor. Equations for the distortion products M2and M3, which are derived from this type of characteristic, accurately predict M2and M3for actual devices as a function of physical parameters. Lower limits on the values of M2and M3which can be achieved in a practical JFET are presented.