Sub-quarter-micrometer CMOS on ultrathin (400 Å) SOI

MOS transistors with effective channel lengths down to 0.2 μm have been fabricated in fully depleted, ultrathin (400 Å) silicon-on-insulator (SOI) films. These devices do not exhibit punchthrough, even for the smallest channel lengths, and have performance characteristics comparable to deep-submicrometer bulk transistors. The NMOS devices have a p⁺-polysilicon gate, and the PMOS devices have an n⁺-polysilicon gate, giving threshold voltages close to 1 V with very light channel doping. Because the series resistance associated with the source and drain regions can be very high in such thin SOI films, a titanium salicide process was used using a 0.25 μm oxide spacer. With this process, the sheet resistance of the silicided SOI layer is approximately 5 Ω/□. However, the devices still exhibit significant series resistance, which is likely due to contact resistance between the silicide and silicon source/drain regions     

Suppression of parasitic bipolar effects in thin-film SOItransistors

In order to correctly estimate the bipolar holding voltage of thin-film SOI transistors with submicrometer gate lengths, it is necessary to obtain the correct balance between the bipolar current gain and impact ionization. The bipolar current gain was found to be strongly dependent upon bandgap narrowing in the heavily doped source, while impact ionization may be most accurately modeled with a nonlocal ballistic model employing a composite electron mean-free path of 9.2 nm. Simulation with the improved models suggests that a reduction in the lateral electric field of the n^- drain region, and hence an increased bipolar holding voltage, may be achieved by using ultrathin highly doped SOI films. For a 0.5-μm gate length, a maximum holding voltage in excess of 6 V has been simulated     

Bulk traps in ultrathin SIMOX MOSFET's by current DLTS

Bulk traps in very thin ( ~100-nm) SIMOX films have been studied by applying current deep-level transient spectroscopy (DLTS) to fully depleted, enhancement MOS transistors, fabricated in these films. The effect of states at both the front and back SiO₂-Si interfaces is eliminated by suitable biasing. Using this technique, a bulk trap with energy level 0.44 eV above the valence-band edge, capture cross section ~10^-17 cm², and concentration ~10 ¹⁵ cm^-3, which is believed to be due to iron contamination, has been identified     

Inverted thin-film transistors with a simple self-aligned lightlydoped drain structure

The I-V characteristics of inverted thin-film transistors (TFT) are studied. A simple lightly doped drain (LDD) structure is utilized to control the channel electric field at the drain junction and to improve the performance of the TFTs. The LDD region is self-aligned to the channel and the source/drain regions. It is created by a spacer around an oxide mask which exclusively defines the channel length L_ch. Experimental data show that the leakage current, subthreshold swing SS, saturation current, and on/off current ratio of the inverted TFTs are closed related to L_ch, L_LDD, the drain bias, gate voltage, and LDD dose. With a gate deposited at low temperature, a saturation current of ~1.25 μA at 5 V and a leakage current of ~0.03 pA per micrometer of channel width were achieved. The current ratio therefore exceeds seven orders of magnitude, with an SS of 380 mV/decade. At 3.3 V, the current ratio is ~7×10⁶     

Recessed-channel structure for fabricating ultrathin SOI MOSFETwith low series resistance

A new recessed-channel SOI (RCSOI) technology has been developed for fabricating ultrathin SOI MOSFET's with low source/drain series resistance. Thin-film fully depleted SOI MOSFET's with channel film thickness of 72 nm have been fabricated with the RCSOI technology. The new structure demonstrated a 70% reduction in source/drain series resistance compared with conventional processes. In the deep-submicron region, more than 80% improvement in saturation drain current and transconductance over conventional devices was achieved using the RCSOI technology. The new technology would also facilitate the use of silicide for further reducing the series resistance     

Low-power and high-stability SRAM technology using alaser-recrystallized p-channel SOI MOSFET

Laser recrystallization of p-channel SOI MOSFETs on an undulated insulating layer is demonstrated for SRAMs with low power and high stability. Self-aligned p-channel SOI MOSFETs for loads are stacked over bottom n-channel bulk MOSFETs for both drivers and transfer gates. A sufficient laser power assures the same leakage currents between SOI MOSFETs fabricated on an undulated insulating layer in memory cell regions and on an even insulating layer in field regions. The on/off ratio of the SOI MOSFETs is increased by a factor of 10⁴, and the source-drain leakage current is decreased by a factor of 10-10² compared with those of polysilicon thin-film transistors (TFTs) fabricated by using low-temperature regrowth of amorphous silicon. A test 256-kb SRAM fabricated this technology shows improved stand-by power dissipation and cell stability. The process steps can be decreased to 83% of those TFT load SRAMs if both the peripheral circuit and memory cells are made with p-channel SOI and n-channel bulk MOSFETs     

Vertical bipolar transistors on buried silicon nitride layers

The letter reports on the integration of vertically operating n-p-n-bipolar transistors with base widths of about 1 µm in silicon-on-insulator (SOI) structures. Nitrogen ion implantation at substrate temperatures of 550°C and subsequent SiCl4epitaxy provide SOI films with excellent crystalline quality. Conventional bipolar diffusion processes have been applied in order to fabricate diodes and vertical bipolar transistor arrays on thus isolated epitaxial layers. The leakage current of SOI diodes exceeds the value for bulk devices only by a factor of 2. The transistors exhibit emitter current gains of up to 100 and emitter-collector breakdown voltages of up to 35 V.     

Suppression of the floating-body effect in partially-depleted SOIMOSFETs with SiGe source structure and its mechanism

SiGe layers were formed in source regions of partially-depleted 0.25-μm SOI MOSFETs by Ge implantation, and the floating-body effect was investigated for this SiGe source structure. It is found that the increase of the Ge implantation dosage suppresses kinks in I_d-V_d characteristics and that the kinks disappear for devices with a Ge dose of 3×10¹⁶ cm^-2. The lowering of the drain breakdown voltage and the anomalous decrease of the subthreshold swing are also suppressed with this structure. It is confirmed that this suppression effect originates from the decrease of the current gain for source/channel/drain lateral bipolar transistors (LBJTs) with the SiGe source structure. The temperature dependence of the base current indicates that the decrease of the current gain is ascribed to the bandgap narrowing of the source region     

High-current small-parasitic-capacitance MOSFET on a poly-Siinterlayered (PSI:Ψ) SOI wafer

A new type of silicon-on insulator (SOI) structure has been fabricated by using direct bonding technology to bury multilayered films consisting of poly-Si and SiO₂. A device with an ideal epitaxial channel structure was fabricated using a conventional MOS process on this novel multilayered SOI (100-nm SOI/10-nm SiO₂/poly-Si/500-nm SiO₂) wafer. In this device, the highly concentrated p⁺ poly-Si just beneath the nMOS channel region acts as a punchthrough stopper, and the buried thin backgate oxide under the SOI layer acts as an impurity diffusion barrier, keeping the impurity concentration in the SOI film at its original low level. The device fabricated was an ultrathin SOI MOSFET capable of operating at a current 1.5 times that of conventional hundred-nm devices at low voltages     

Thin-film transistors in polycrystalline silicon by blanket andlocal source/drain hydrogen plasma-seeded crystallization

Thin film n-channel transistors have been fabricated in polycrystalline silicon films crystallized using hydrogen plasma seeding, by using several processing techniques with 600 to 625°C or 1000°C as the maximum process temperature. The TFTs from hydrogen plasma-treated films with a maximum process temperature of 600°C, have a linear field-effect mobility of ~35 cm²/Vs and an ON/OFF current ratio of ~10⁶, and TFTs with a maximum process temperature of 1000°C, have a linear field-effect mobility of ~100 cm²/Vs and an ON/OFF current ratio of ~10⁷. A hydrogen plasma has also then been applied selectively a in the source and drain regions to seed large crystal grains in the channel. Transistors made with this method with maximum temperature of 600°C showed a nearly twofold improvement in mobility (72 versus 37 cm² /Vs) over the unseeded devices at short channel lengths. The dominant factor in determining the field-effect mobility in all cases was the grain size of the polycrystalline silicon, and not the gate oxide growth/deposition conditions. Significant increases in mobility are observed when the grain size is in order of the channel length. However the gate oxide plays an important role in determining the subthreshold slope and the leakage current     

High-performance sub-quarter-micrometer PMOSFET's on SOI

PMOS transistors with effective channel lengths down to 0.15 μm have been fabricated on silicon-on-insulator (SOI) films. Gate oxide thicknesses of 5.5 and 10 nm are used. These P⁺ gate PMOS devices exhibit excellent short-channel behavior, low-source-drain resistance, and remarkably large current drive and transconductance. for T_ox=5.5 nm, saturation transconductances of 274 mS/mm at 300 K and 352 mS/mm at 80 K are achieved, which are the highest reported values for this oxide thickness. The result is attributed to low series resistance, forward-bias body effect, and the reduction of body charge effect     

Interface characterization of fully depleted SOI MOSFETs by thedynamic transconductance technique

The dynamic transconductance technique of MOSFET interface characterization is adapted to fully depleted silicon-on-insulator (SOI) transistors and is used to measure the interface-state density energy profiles in several SIMOX (separation by implanted oxygen) transistors. By making measurements first with the current flowing through the channel under measurement and then through the opposite channel, much of the energy gap (from accumulation to well into weak inversion) can be probed. Remarkably high sensitivity is achieved by utilizing the imaginary part of the dynamic transconductance. Measured interface trap densities were in the region of ~10¹⁰-10¹¹ eV^-1-cm^-2     

An investigation of laser annealed and metal-induced crystallizedpolycrystalline silicon thin-film transistors

We report results on thin-film transistors (TFTs) made from a new hybrid process in which amorphous silicon (a-Si) is first converted to polycrystalline silicon (poly-Si) using Ni-metal-induced lateral crystallization (MILC), and then improved using excimer laser annealing (laser MILC or L-MILC). With only a very low shot laser process, we demonstrate that laser annealing of MILC material can improve the electron mobility from 80 to 170 cm²/Vs, and decrease the minimum leakage current by one to two orders of magnitude at a drain bias of 5 V. Similar trends occur for both p- and n-type material. A shift in threshold voltage upon laser annealing indicates the existence of a net positive charge in Ni-MILC material, which is neutralised upon laser exposure. The MILC material in particular exhibits a very high generation state density of ~10¹⁹ cm^-3 which is reduced by an order of magnitude in L-MILC material. The gate and drain field dependences of leakage current indicate that the leakage current in MILC transistors is related to this high defect level and the abruptness of the channel/drain junction. This can be improved with a lightly doped drain (LDD) implant, as in other poly-Si transistors     

New aspects and mechanism of kink effect in static back-gatetransconductance characteristics in fully-depleted SOI MOSFETs onhigh-dose SIMOX wafers

An extraordinary kink phenomenon in static back-gate transconductance characteristics of fully-depleted SOI MOSFETs has been experimentally investigated and characterized for the first time. This kink phenomenon has been observed in both NMOS and PMOS on high-dose SIMOX wafers under steady-state conditions at room temperature. It was also found that the back-gate characteristics for both NMOS and PMOS show anomalous shift phenomenon in drain current-back gate voltage (I _D-V_G2) curve at the back-gate voltage corresponding to the kink phenomenon. This kink phenomenon has been attributed to the presence of energetically-localized trap states at SOI/BOX interface. In order to clarify the energy level of the trap states at SOI/BOX interface corresponding to the kink, we have developed a new formula of surface potential in thin-film SOI MOS devices, in which the potential drop across semiconductor-substrate is taken into account. By using this new formula, me have demonstrated that high-dose SIMOX wafers have donor-like electron trap states at ~0.33 eV above the Si midgap with the density of ~N6.0~10¹² cm^-2 eV ^-1 and donor-like hole trap states at ~0.35 eV below the Si midgap with density of ~1.5×10¹² cm^-2 eV^-1 at SOI/BOX interface     

Study of the Drain Leakage Current in Bottom-Gated Nanocrystalline Silicon Thin-Film Transistors by Conduction and Low-Frequency Noise Measurements

The drain leakage current in n-channel bottom-gated nanocrystalline silicon (nc-Si) thin-film transistors is investigated systematically by conduction and low-frequency noise measurements. The presented results indicate that the leakage current, controlled by the reverse biased drain junction, is due to Poole-Frenkel emission at low electric fields and band-to-band tunneling at large electric fields. The leakage current is correlated with single-energy traps and deep grain boundary trap levels with a uniform energy distribution in the band gap of the nc-Si. Analysis of the leakage current noise spectra indicates that the grain boundary trap density of 8.5 times 10¹² cm ^-2 in the upper part of the nc-Si film is reduced to 2.1 times 10¹² cm^-2 in the lower part of the film, which is attributed to a contamination of the nc-Si bulk by oxygen     

New channel engineering for sub-100 nm MOS devices considering bothcarrier velocity overshoot and statistical performance fluctuations

We introduce a new channel engineering design for nano-region SOI and bulk MOSFETs taking into account both carrier velocity overshoot and statistical performance fluctuations. For types of both device, in the high gate drive region, the high field carrier velocity υ_e is not degraded at channel dopant density N_a lower than 1×10¹⁷ cm^-3, according to an experimental universal relationship between υ_e and the low field mobility. On the other hand, there is a most suitable N_a condition for suppression of statistical threshold voltage fluctuations. This most suitable N_a is slightly higher for SOI devices than that for bulk MOSFETs, but it is lower than 1×10 ¹⁷ cm^-3 in both cases. Therefore, this most suitable N_a condition is consistent with the above N_a condition for carrier velocity. Consequently, new N_a conditions for nano region devices are introduced in this study. N_a should be designed to be of the order of 1×10¹⁶ cm^-3 rather than rising by the usual scaling rule, but it is necessary to suppress the short channel effects of SOI and bulk MOSFETs by scaling down the SOI thickness, and to use source/drain junction depth scaling or surface low impurity structures in bulk MOSFETs, respectively     

A method for the prediction of hot-carrier lifetime in floating SOINMOSFETs

A concept was presented for the prediction of the device lifetimes for the hot-carrier effect (hot-carrier lifetimes) in floating SOI MOSFETs. The concept is that hot-carrier lifetimes in floating SOI MOSFETs can be predicted by estimating the hole current. In order to verify the validity of this concept, the hole current was investigated using device simulation. The results showed that the ratio of the hole current to the drain current in a floating-body SOI MOSFET is approximately equal to the ratio of substrate current to drain current in a body-tied one. Based on this fact, a method for accurately predicting the hot-carrier lifetime in floating-body SOI MOSFETs was proposed. The hot-carrier lifetime predicted with this method agreed well with the experimental results. This study showed that only the drain current difference between floating and body-tied structures results in lifetime differences, and there is no special effect on hot-carrier degradation in floating SOI MOSFETs. In this prediction, therefore, floating SOI MOSFETs can be treated in the same way as bulk MOSFETs. Hot-carrier lifetimes in floating SOI MOSFETs can be predicted using the hole current, while substrate currents are used in bulk MOSFETs     

Fully-depleted SOI devices with TaSiN gate, HfO/sub 2/ gate dielectric, and elevated source/drain extensions

We report for the first time the performance of ultrathin film fully-depleted (FD) silicon-on-insulator (SOI) CMOS transistors using HfO/sub 2/ gate dielectric and TaSiN gate material. The transistors feature 100-150 /spl Aring/ silicon film thickness and selective epitaxial silicon growth in the source/drain extension regions. TaSiN-gate shows good threshold voltage control using an undoped channel, which reduces threshold voltage variation with silicon film thickness and discrete, random dopant placement. Device processing for CMOS fabrication is drastically simplified by the use of the same gate material for both n- and p-MOSFETs. Electrical characterization results illustrate the combined impact of using high-k dielectric and metal gate on the performance of ultrathin film FD SOI devices.     

Improved subthreshold characteristics of n-channel SOI transistors

It has been found that certain n-channel MOSFET's fabricated on silicon-on-insulator (SOI) substrates formed by oxygen implantation can havelog (I_{d}): V_{gs}, characteristics with very steep slopes in the subthreshold region. In contradiction to normal models for short-channel transistors on bulk silicon, the slope becomes steeper for shorter gate lengths or higher drain voltages. This effect is shown to be related to the kink in the output characteristics of transistors with floating islands.     

DC self-heating effects modelling in SOI and bulk FinFETs

DC thermal effects modelling for nanometric silicon-on-insulator (SOI) and bulk fin-shaped field-effect transistors (FinFETs) is presented. Among other features, the model incorporates self-heating effects (SHEs), velocity saturation and short-channel effects. SHEs are analysed in depth by means of thermal resistances, which are determined through an equivalent thermal circuit, accounting for the degraded thermal conductivity of the ultrathin films within the device. Once the thermal resistance for single-fin devices has been validated for different gate lengths and biases, comparing the modelled output characteristics and device temperatures with numerical simulations obtained using Sentaurus Device, the thermal model is extended by circuital analysis to multi-fin devices with multiple fingers.